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[189.204.200.163]) by smtp.gmail.com with ESMTPSA id s5sm8500553qkg.88.2021.05.16.05.34.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 05:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wol0hIlUZMDB7Lxhd/OO6iyKqSE57dtkR8dBi3DQOxs=; b=nmQSaScX4wqOhCdaIMXUa4I7PD/kxZS5aTIi/TR+Anzu/VrZ81ANJwvyyvRw3TbkQi xEUtxTgSSDIuegCDQtm0xZwnC/pj6kxIbckFkJS+05c9ezOPf8AESNm/bFhJ2FCLnzaQ 2bQcXmpoeC1agSKbq9PPeAabkj+RQpR+Cei8hi3xFsD2Ni01duBDJL20AhjAyivRqB8+ JuLRCYRp/afer/3hGD9Z2CXxGSdYzjlQxjRXOy0FowQjr3ZbfbEW574qEtb+r+5+HwNi Cg+Q9ZmvYNYDv+kuVN9I7sy/MTXYXioJr0LH/C6qVEKk8DG+aP2RdlkIYCkoYX5dOYoK cMNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wol0hIlUZMDB7Lxhd/OO6iyKqSE57dtkR8dBi3DQOxs=; b=eIJZkH6ddkM7uoXHh+gY02VWuyeSg//0DmlRlxuWOoV6IcR2/aHz7mbLvr1wAnaU7c 9U6W02KLRhHSEu6XyHIIGke8UqHa79bAtzMZE8Z+JudicrvFTNKVdTHaWs+0/wNX5D4g xQO6bp3F3FpuGUF4VfY/61fdIUnBhu7IQeX/fVUst4XzrAFS58g2Bp01dWSMerPFjeyR ShPz53dCbrsorYtrwJWD2p48LdJSjS7i7aJqS8Yhhic1drjL6yDdrdF5T5UI0+gyWQ3R WOsu2yW5qhJ9cuvZMnqly2lOV8I/KtuvL3KT1Pu+nrzRGjvEuk4oWTyjg0pM4saKLmcz rDvw== X-Gm-Message-State: AOAM532e3dWr78PGbDGNBamo1ODMubS5XVIC5jt5k8/T0EHDTaELabn6 KbNLJATQD7QCgTh2PR32ON367ioP83/B0CnEpik= X-Google-Smtp-Source: ABdhPJzGmvtL9UPdnLRtsBTOYc9UTLxIWU+8sscDjWAtfVypW5Z0mfC0vI8RRWkhBmLrBs7nJ7wQHQ== X-Received: by 2002:ac8:7c4b:: with SMTP id o11mr25766242qtv.336.1621168494468; Sun, 16 May 2021 05:34:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/46] softfloat: Convert float128_silence_nan to parts Date: Sun, 16 May 2021 07:34:11 -0500 Message-Id: <20210516123431.718318-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210516123431.718318-1-richard.henderson@linaro.org> References: <20210516123431.718318-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is the minimal change that also introduces float128_params, float128_unpack_raw, and float128_pack_raw without running into unused symbol Werrors. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- fpu/softfloat.c | 96 +++++++++++++++++++++++++++++----- fpu/softfloat-specialize.c.inc | 25 +++------ 2 files changed, 89 insertions(+), 32 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ee609540aa..f8f4ef51e8 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -500,14 +500,12 @@ static inline __attribute__((unused)) bool is_qnan(Fl= oatClass c) } =20 /* - * Structure holding all of the decomposed parts of a float. The - * exponent is unbiased and the fraction is normalized. All - * calculations are done with a 64 bit fraction and then rounded as - * appropriate for the final format. + * Structure holding all of the decomposed parts of a float. + * The exponent is unbiased and the fraction is normalized. * - * Thanks to the packed FloatClass a decent compiler should be able to - * fit the whole structure into registers and avoid using the stack - * for parameter passing. + * The fraction words are stored in big-endian word ordering, + * so that truncation from a larger format to a smaller format + * can be done simply by ignoring subsequent elements. */ =20 typedef struct { @@ -527,6 +525,15 @@ typedef struct { }; } FloatParts64; =20 +typedef struct { + FloatClass cls; + bool sign; + int32_t exp; + uint64_t frac_hi; + uint64_t frac_lo; +} FloatParts128; + +/* These apply to the most significant word of each FloatPartsN. */ #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) =20 @@ -562,11 +569,11 @@ typedef struct { .exp_bias =3D ((1 << E) - 1) >> 1, \ .exp_max =3D (1 << E) - 1, \ .frac_size =3D F, \ - .frac_shift =3D DECOMPOSED_BINARY_POINT - F, \ - .frac_lsb =3D 1ull << (DECOMPOSED_BINARY_POINT - F), \ - .frac_lsbm1 =3D 1ull << ((DECOMPOSED_BINARY_POINT - F) - 1), \ - .round_mask =3D (1ull << (DECOMPOSED_BINARY_POINT - F)) - 1, \ - .roundeven_mask =3D (2ull << (DECOMPOSED_BINARY_POINT - F)) - 1 + .frac_shift =3D (-F - 1) & 63, \ + .frac_lsb =3D 1ull << ((-F - 1) & 63), \ + .frac_lsbm1 =3D 1ull << ((-F - 2) & 63), \ + .round_mask =3D (1ull << ((-F - 1) & 63)) - 1, \ + .roundeven_mask =3D (2ull << ((-F - 1) & 63)) - 1 =20 static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) @@ -589,6 +596,10 @@ static const FloatFmt float64_params =3D { FLOAT_PARAMS(11, 52) }; =20 +static const FloatFmt float128_params =3D { + FLOAT_PARAMS(15, 112) +}; + /* Unpack a float to parts, but do not canonicalize. */ static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t ra= w) { @@ -623,6 +634,20 @@ static inline void float64_unpack_raw(FloatParts64 *p,= float64 f) unpack_raw64(p, &float64_params, f); } =20 +static void float128_unpack_raw(FloatParts128 *p, float128 f) +{ + const int f_size =3D float128_params.frac_size - 64; + const int e_size =3D float128_params.exp_size; + + *p =3D (FloatParts128) { + .cls =3D float_class_unclassified, + .sign =3D extract64(f.high, f_size + e_size, 1), + .exp =3D extract64(f.high, f_size, e_size), + .frac_hi =3D extract64(f.high, 0, f_size), + .frac_lo =3D f.low, + }; +} + /* Pack a float from parts, but do not canonicalize. */ static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt) { @@ -656,6 +681,18 @@ static inline float64 float64_pack_raw(const FloatPart= s64 *p) return make_float64(pack_raw64(p, &float64_params)); } =20 +static float128 float128_pack_raw(const FloatParts128 *p) +{ + const int f_size =3D float128_params.frac_size - 64; + const int e_size =3D float128_params.exp_size; + uint64_t hi; + + hi =3D (uint64_t)p->sign << (f_size + e_size); + hi =3D deposit64(hi, f_size, e_size, p->exp); + hi =3D deposit64(hi, 0, f_size, p->frac_hi); + return make_float128(hi, p->frac_lo); +} + /*------------------------------------------------------------------------= ---- | Functions and definitions to determine: (1) whether tininess for underf= low | is detected before or after rounding by default, (2) what (if anything) @@ -666,8 +703,30 @@ static inline float64 float64_pack_raw(const FloatPart= s64 *p) *-------------------------------------------------------------------------= ---*/ #include "softfloat-specialize.c.inc" =20 +#define PARTS_GENERIC_64_128(NAME, P) \ + QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) + #define parts_default_nan parts64_default_nan -#define parts_silence_nan parts64_silence_nan +#define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P,= S) + + +/* + * Helper functions for softfloat-parts.c.inc, per-size operations. + */ + +static void frac128_shl(FloatParts128 *a, int c) +{ + shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shl(A, C) frac128_shl(A, C) + +static void frac128_shr(FloatParts128 *a, int c) +{ + shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shr(A, C) frac128_shr(A, C) =20 /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *par= m, @@ -3851,6 +3910,17 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_stat= us *status) return bfloat16_pack_raw(&p); } =20 +float128 float128_silence_nan(float128 a, float_status *status) +{ + FloatParts128 p; + + float128_unpack_raw(&p, a); + frac_shl(&p, float128_params.frac_shift); + parts_silence_nan(&p, status); + frac_shr(&p, float128_params.frac_shift); + return float128_pack_raw(&p); +} + /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 4038955379..5b85b843c2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -197,6 +197,12 @@ static void parts64_silence_nan(FloatParts64 *p, float= _status *status) p->cls =3D float_class_qnan; } =20 +static void parts128_silence_nan(FloatParts128 *p, float_status *status) +{ + p->frac_hi =3D parts_silence_nan_frac(p->frac_hi, status); + p->cls =3D float_class_qnan; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated extended double-precision NaN. *-------------------------------------------------------------------------= ---*/ @@ -1062,25 +1068,6 @@ bool float128_is_signaling_nan(float128 a, float_sta= tus *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the quadruple-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_silence_nan(float128 a, float_status *status) -{ - if (no_signaling_nans(status)) { - g_assert_not_reached(); - } else { - if (snan_bit_is_one(status)) { - return float128_default_nan(status); - } else { - a.high |=3D UINT64_C(0x0000800000000000); - return a; - } - } -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point = NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid --=20 2.25.1