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Tsirkin" , Igor Mammedov , Shannon Zhao , "Alistair Francis" , David Gibson , , Subject: [RFC PATCH v3 6/9] hw/arm/virt-acpi-build: Use possible cpus in generation of MADT Date: Sun, 16 May 2021 18:28:57 +0800 Message-ID: <20210516102900.28036-7-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210516102900.28036-1-wangyanan55@huawei.com> References: <20210516102900.28036-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=wangyanan55@huawei.com; helo=szxga07-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , zhukeqian1@huawei.com, yangyicong@huawei.com, prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When building ACPI tables regarding CPUs we should always build them for the number of possible CPUs, not the number of present CPUs. So we create gicc nodes in MADT for possible cpus and then ensure only the present CPUs are marked ENABLED. Furthermore, it also needed if we are going to support CPU hotplug in the future. Co-developed-by: Andrew Jones Signed-off-by: Andrew Jones Co-developed-by: Ying Fang Signed-off-by: Ying Fang Co-developed-by: Yanan Wang Signed-off-by: Yanan Wang --- hw/arm/virt-acpi-build.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index a2d8e87616..4d64aeb865 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -481,6 +481,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) const int *irqmap =3D vms->irqmap; AcpiMadtGenericDistributor *gicd; AcpiMadtGenericMsiFrame *gic_msi; + MachineClass *mc =3D MACHINE_GET_CLASS(vms); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(MACHI= NE(vms)); + bool pmu; int i; =20 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); @@ -491,11 +494,21 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) gicd->base_address =3D cpu_to_le64(memmap[VIRT_GIC_DIST].base); gicd->version =3D vms->gic_version; =20 - for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { + for (i =3D 0; i < possible_cpus->len; i++) { AcpiMadtGenericCpuInterface *gicc =3D acpi_data_push(table_data, sizeof(*gicc)); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); =20 + /* + * PMU should have been either implemented for all CPUs or not, + * so we only get information from the first CPU, which could + * represent the others. + */ + if (i =3D=3D 0) { + pmu =3D arm_feature(&armcpu->env, ARM_FEATURE_PMU); + } + assert(!armcpu || arm_feature(&armcpu->env, ARM_FEATURE_PMU) =3D= =3D pmu); + gicc->type =3D ACPI_APIC_GENERIC_CPU_INTERFACE; gicc->length =3D sizeof(*gicc); if (vms->gic_version =3D=3D 2) { @@ -504,11 +517,19 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) gicc->gicv_base_address =3D cpu_to_le64(memmap[VIRT_GIC_VCPU].= base); } gicc->cpu_interface_number =3D cpu_to_le32(i); - gicc->arm_mpidr =3D cpu_to_le64(armcpu->mp_affinity); + gicc->arm_mpidr =3D cpu_to_le64(possible_cpus->cpus[i].arch_id); gicc->uid =3D cpu_to_le32(i); - gicc->flags =3D cpu_to_le32(ACPI_MADT_GICC_ENABLED); =20 - if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { + /* + * ACPI spec says that LAPIC entry for non present CPU may be + * omitted from MADT or it must be marked as disabled. Here we + * choose to also keep the disabled ones in MADT. + */ + if (possible_cpus->cpus[i].cpu !=3D NULL) { + gicc->flags =3D cpu_to_le32(ACPI_MADT_GICC_ENABLED); + } + + if (pmu) { gicc->performance_interrupt =3D cpu_to_le32(PPI(VIRTUAL_PMU_IR= Q)); } if (vms->virt) { --=20 2.19.1