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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id d16sm247484ilo.12.2021.05.12.11.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 11:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E98zYgOb8svCo31J0cZx6NXuFYRvLAQi1ckb6DzE2jE=; b=d6yRBqVmHDZpfjAwNSNtYCIRbKLIxar8oc4mtq32Q3Yr8Zpz6f2tZ4eXl1NUm4mhs+ yoOkvhYWzLVHOy+UhbfRELjGvisLBo1OmDTBiTM3hninDSVwTWmRKKaLB/qqYGLF/14Q AF31oR/4G8/ptJjWGSMsfEwBkseyDA5+yBsrWx9q7jEX8mzA1aPVcezkAtHniZJcuxGK +aSQnkCy0gLqU3lBkIlShOR8CYQXcDrf4m2kAIDKg9CiybJG23U9pF78dZbgNLRNeeAw TZjXWCd0FU9DyO4UBdlQJ39bfNLGe3Sg7enV0BtZaKYlPDjMFzhe2lDfJfod7bIV+OUO 6lPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E98zYgOb8svCo31J0cZx6NXuFYRvLAQi1ckb6DzE2jE=; b=i7FPDcEW6YYZi2OHa537/OOgMFN/g8LS3b5O3QSbp3E1SY8iKnjG0muHp8QrBdJc63 4++nzmd1d5mQ01WvxMbx3v/FECjRjt1eMUFwmUjveCPDpS39F/eHy8+pe3BlnePQ1Ynj m5ubRrTLHwKC6KmKmH5shBcoVowRngJcsP8Sv6Pup3zkCEXZ5H42GU5R80ba0V5c828i K+hI0/0osSXGYxKN2vxM4SjiebVk+wB5UkYyKYcO5h2m6D6UEM4arJ5a0mh7KQ5KgSyl FSbL0tV8fy/f1Q7gzFEqxQQstXyEiu2fCCI5GF5tFzw8pKmWGksEke3mv/MWCVsRcvx1 L8Ug== X-Gm-Message-State: AOAM532ExEUYJxXCSp9/gP5+b2YHCpPOCPoXJA3OmxWgm88avlNGyl7l 7Yp25IApbR4M8LkmrrocWKvs8RV0AWf5WsCVQIlHw3TyWJsWwzpdSP04LOq4CmZHwzUelEVbuKW tddWVoWSxLgfFYW9lgzakP2kCDffhCbHLIJkbgmMZwpIklcTtU4v/ePTBu41U0dcSrXrWTIeNHg == X-Google-Smtp-Source: ABdhPJzZ3Kx2rEaaN/Isoto4oF8Ugeq6CDpryB6ZUAtPNSmCCnOMg9PKYOJV6CMCsmtM1JbZP0TPqQ== X-Received: by 2002:a92:c8d2:: with SMTP id c18mr32812839ilq.81.1620843827933; Wed, 12 May 2021 11:23:47 -0700 (PDT) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v9 2/3] target/arm: Add support for FEAT_TLBIOS Date: Wed, 12 May 2021 12:23:36 -0600 Message-Id: <20210512182337.18563-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210512182337.18563-1-rebecca@nuviainc.com> References: <20210512182337.18563-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::133; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x133.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , Richard Henderson , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 43 ++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5802798c3069..7986a217acdd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4076,6 +4076,11 @@ static inline bool isar_feature_aa64_tlbirange(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4adb017f81a2..59e9847133a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7198,6 +7198,46 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8570,6 +8610,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2