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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id d16sm247484ilo.12.2021.05.12.11.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 11:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lSeaVPE5uPZmfHK6wI0ew2xFQvqO9fhC+YLXT9cj1PE=; b=EUgbY/L+95MNr6It5lnKKBdPgaY4UeRNVdrcWUrR3aXMr1eXQ0cYPSDqM2hbJzrqSf C0UA8TvwMEpE0alQlRWFMvKPHsNtSGrovYj3xNcf5WxNPnab7a7AKC1qvHCYedupEQg7 O9CpjJp0f83oA1vytYI64XtoZPvirGA4t9t9mQopQpRwp5rg0sOV7bAQEMTzcW14xSUx rbzPYIZaRmmDkx57EbAVceB3xkSbodIJPdiSfCFK3qubwFC9KQ7lVluEdh6CBCHx1Kuc Q8BWwfklHh2uC1AQ73epkzizcwPsP6IGwBHvP6ibzNzFlZxSFTnz1xnFq6JHiEyc4fUj TpYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lSeaVPE5uPZmfHK6wI0ew2xFQvqO9fhC+YLXT9cj1PE=; b=GIWw0an93mIleRUFosxwxYHa6UEf0nG5Dc2E0FNqJ+y8PjbvSKc6TBtWsuSbW5uIGQ D7jjhqUcwPhIfo02ju1j4uhR5bt73ilQgpppHWj1CvEkBtLXc2IM+KJwBC6V/VZyL39i RHBVJk1l4zH55pjhJ0w+dNmCdZxhgUo9PDL1GXvgUpSayT3j2PXWiEnWXUcNGsYcvBEZ PYGOq2ayDQBabAa4Y4DJwlmFYYxEqSKVcNXjtGTJVixBeAdkEMVCWjmIZzBkCNPfMsPK ReJvV2Hy85QK0Zs5VnUlxAtyPO0a0J3Wd45WAKnqiipB0gCLC+yXdo4X0WtEnzdarALH cpkQ== X-Gm-Message-State: AOAM531o3Z3Zl89AQ0vb7fQznDMOtcXoMmlYBNF0P2dKyIwGBxyIQRH4 gE5NzYjRXsmBjIE6IkZl39JCVcUG/xcTBU1F1PButhXFOa7zkdllRiCXF8gg961sH1jJQwKws1j K8nttT19/ZdTZDbnrZXh0Lu0PMb5wWp4JT9pTGzupHh+wfPncZ//tj4TvDU++F68x7Xga7n1t9g == X-Google-Smtp-Source: ABdhPJyeLPo7IpaSsA7mLdm6qyaMnMd4Wuaq7v5egxXqZ04hJaefQGbNkMUzl9ChGyzAmVsmRg1Pgw== X-Received: by 2002:a92:de49:: with SMTP id e9mr30766510ilr.132.1620843826940; Wed, 12 May 2021 11:23:46 -0700 (PDT) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v9 1/3] target/arm: Add support for FEAT_TLBIRANGE Date: Wed, 12 May 2021 12:23:35 -0600 Message-Id: <20210512182337.18563-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210512182337.18563-1-rebecca@nuviainc.com> References: <20210512182337.18563-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::129; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x129.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , Richard Henderson , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/helper.c | 281 ++++++++++++++++++++ 2 files changed, 286 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b39325347..5802798c3069 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4071,6 +4071,11 @@ static inline bool isar_feature_aa64_pauth_arch(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; } =20 +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 3b365a78cbc3..4adb017f81a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4759,6 +4759,172 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } =20 +#ifdef TARGET_AARCH64 +static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, + uint64_t value) +{ + unsigned int page_shift; + unsigned int page_size_granule; + uint64_t num; + uint64_t scale; + uint64_t exponent; + uint64_t length; + + num =3D extract64(value, 39, 4); + scale =3D extract64(value, 44, 2); + page_size_granule =3D extract64(value, 46, 2); + + page_shift =3D page_size_granule * 2 + 12; + + if (page_size_granule =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + return 0; + } + + exponent =3D (5 * scale) + 1; + length =3D (num + 1) << (exponent + page_shift); + + return length; +} + +static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, + bool two_ranges) +{ + /* TODO: ARMv8.7 FEAT_LPA2 */ + uint64_t pageaddr; + + if (two_ranges) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + + return pageaddr; +} + +static void do_rvae_write(CPUARMState *env, uint64_t value, + int idxmap, bool synced) +{ + ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap); + bool two_ranges =3D regime_has_2_ranges(one_idx); + uint64_t baseaddr, length; + int bits; + + baseaddr =3D tlbi_aa64_range_get_base(env, value, two_ranges); + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, one_idx, baseaddr); + + if (synced) { + tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), + baseaddr, + length, + idxmap, + bits); + } else { + tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, + length, idxmap, bits); + } +} + +static void tlbi_aa64_rvae1_write(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + + do_rvae_write(env, value, vae1_tlbmask(env), + tlb_force_broadcast(env)); +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + + do_rvae_write(env, value, vae1_tlbmask(env), true); +} + +static int vae2_tlbmask(CPUARMState *env) +{ + return (arm_is_secure_below_el3(env) + ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + + do_rvae_write(env, value, vae2_tlbmask(env), + tlb_force_broadcast(env)); + + +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, + * since we don't support flush-for-specific-ASID-only, + * flush-last-level-only or inner/outer shareable specific flushes. + */ + + do_rvae_write(env, value, vae2_tlbmask(env), true); + +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + + do_rvae_write(env, value, ARMMMUIdxBit_SE3, + tlb_force_broadcast(env)); +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, + * since we don't support flush-for-specific-ASID-only, + * flush-last-level-only or inner/outer specific flushes. + */ + + do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); +} +#endif + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { @@ -6920,6 +7086,118 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbirange_reginfo[] =3D { + { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8289,6 +8567,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_tlbirange, cpu)) { + define_arm_cp_regs(cpu, tlbirange_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Fri May 17 05:00:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1620844800; cv=none; d=zohomail.com; s=zohoarc; b=Oz6zCyxze9OKR/6mva5Lo6P0QkbRiHsJvMw7T63MAJTwP0FClc9MZDKBk3UYTao+hpsQWeLfiwxs/5U7xowXSTtvKDsyvnPV/yUTwdlVyE8t3DS6r6IkcjpdBjaJ5t8/zfe/VFJC3AIrNRY71mQB896wQrOTLjZkTTA/K+bmHE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620844800; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id d16sm247484ilo.12.2021.05.12.11.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 11:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E98zYgOb8svCo31J0cZx6NXuFYRvLAQi1ckb6DzE2jE=; b=d6yRBqVmHDZpfjAwNSNtYCIRbKLIxar8oc4mtq32Q3Yr8Zpz6f2tZ4eXl1NUm4mhs+ yoOkvhYWzLVHOy+UhbfRELjGvisLBo1OmDTBiTM3hninDSVwTWmRKKaLB/qqYGLF/14Q AF31oR/4G8/ptJjWGSMsfEwBkseyDA5+yBsrWx9q7jEX8mzA1aPVcezkAtHniZJcuxGK +aSQnkCy0gLqU3lBkIlShOR8CYQXcDrf4m2kAIDKg9CiybJG23U9pF78dZbgNLRNeeAw TZjXWCd0FU9DyO4UBdlQJ39bfNLGe3Sg7enV0BtZaKYlPDjMFzhe2lDfJfod7bIV+OUO 6lPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E98zYgOb8svCo31J0cZx6NXuFYRvLAQi1ckb6DzE2jE=; b=i7FPDcEW6YYZi2OHa537/OOgMFN/g8LS3b5O3QSbp3E1SY8iKnjG0muHp8QrBdJc63 4++nzmd1d5mQ01WvxMbx3v/FECjRjt1eMUFwmUjveCPDpS39F/eHy8+pe3BlnePQ1Ynj m5ubRrTLHwKC6KmKmH5shBcoVowRngJcsP8Sv6Pup3zkCEXZ5H42GU5R80ba0V5c828i K+hI0/0osSXGYxKN2vxM4SjiebVk+wB5UkYyKYcO5h2m6D6UEM4arJ5a0mh7KQ5KgSyl FSbL0tV8fy/f1Q7gzFEqxQQstXyEiu2fCCI5GF5tFzw8pKmWGksEke3mv/MWCVsRcvx1 L8Ug== X-Gm-Message-State: AOAM532ExEUYJxXCSp9/gP5+b2YHCpPOCPoXJA3OmxWgm88avlNGyl7l 7Yp25IApbR4M8LkmrrocWKvs8RV0AWf5WsCVQIlHw3TyWJsWwzpdSP04LOq4CmZHwzUelEVbuKW tddWVoWSxLgfFYW9lgzakP2kCDffhCbHLIJkbgmMZwpIklcTtU4v/ePTBu41U0dcSrXrWTIeNHg == X-Google-Smtp-Source: ABdhPJzZ3Kx2rEaaN/Isoto4oF8Ugeq6CDpryB6ZUAtPNSmCCnOMg9PKYOJV6CMCsmtM1JbZP0TPqQ== X-Received: by 2002:a92:c8d2:: with SMTP id c18mr32812839ilq.81.1620843827933; Wed, 12 May 2021 11:23:47 -0700 (PDT) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v9 2/3] target/arm: Add support for FEAT_TLBIOS Date: Wed, 12 May 2021 12:23:36 -0600 Message-Id: <20210512182337.18563-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210512182337.18563-1-rebecca@nuviainc.com> References: <20210512182337.18563-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::133; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x133.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , Richard Henderson , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 43 ++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5802798c3069..7986a217acdd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4076,6 +4076,11 @@ static inline bool isar_feature_aa64_tlbirange(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4adb017f81a2..59e9847133a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7198,6 +7198,46 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8570,6 +8610,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Fri May 17 05:00:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1620844870; cv=none; d=zohomail.com; s=zohoarc; b=WSTdYnryOIL6NqRUobT5jhnBsVYDzioWw/55wqr4w7TprwJ+G5n6lCiYMKkXTEsJzeVzYmyr0xQ0TngP7rMKG7+xDrU2Y4ztwXSdgBICTeVNSnR+6tbq/ruA1LigB0gj1B0clH7qmxl46NLBJ0fHxPWv5ulIDj+GmTmNAcik1Ws= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id d16sm247484ilo.12.2021.05.12.11.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 11:23:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uNizM5dd+njefSGglfwPGotA4yVew4h3gSREpFzckEs=; b=sKhSZnjtpQN1Bkj9TABCzW4bl2ROCU2Xn7FBiFOxCvfHmKB41DZVJBGM/04FZjgu4y APf8HDOAZOolZ59NNO+KSwTLK9wsmclu9LOnVkbfCX2NJUrAyB01AZJKF+7UVZcG61cD oPRJCMBa4lV6j+VqIIKp4AaZ+bRjlVrI3Rf+CMxsicySQDO7BiLRNVD5fEYIEf3sOWMq CvuTSMM8LmsIcgQTYsPHuJJ7UqMWD3TaRRtP6kOKZXCPjdEO4V0aPV+bo/njF1RF3Bil 9OTaE6mkGhvmskS8rn0IAWGZWXyguJfNMiTSnShHAhgk3WGdpvhH9tF/eMvjOpO5Dhbi qM/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uNizM5dd+njefSGglfwPGotA4yVew4h3gSREpFzckEs=; b=ShhDLofxd4sX34Ayi/k9u9BM1cWc0vdDyAiW/iESfJWPrCvuJO9KMSkM6QZ8RH1mFJ BODmeeJBAyxCIfPYHcHkYrVtf1hHnmPWJHlhsSQXXhmMGJYY25kuLh2XjDg4/x2PiJGo QcCbvd88542IoLvPqQr/nTHBNkrJnk27uMknIoXW5SSGjytH25nyeO2yQvEL4+8rsKK7 r8LV3ixt9XM49T+qcB/dXo+IatkNbonQZ5HzHR9yGr2ar5SB0EA35q8yPMhFpbb+0/1h udf/PKMTa6gONB+sTprkjK6vNYJD4BFxArd0StYFmMKVKhwpxuYhbpYJy9Ve0SwQbb3T eBJQ== X-Gm-Message-State: AOAM5308292b4XsHZP1KvLc9ov6Cc0ez7bHk5SVboXyp+1DLegme09pD rYQ+aeIgYuzya8y86R8wHmCGZ7gNI+2Gk0WvFpfquGIINCVT0xrd1uElmZzogSzK16xLW8H11Yj GQEirbcQ4Q5Y+uTxvkCfLt1EMzoNCGFMs77qI4n6ZGdZuvRjFGgkfxuAfH93jpzGDyd7Uv3Nzpw == X-Google-Smtp-Source: ABdhPJw2zSbk+xUb0ahOJouGM86Q/zVWCAenO2znq1iaRm87YI/boytzyWIhg7taDsChee3/e7m1HQ== X-Received: by 2002:a05:6e02:118b:: with SMTP id y11mr31944521ili.163.1620843829298; Wed, 12 May 2021 11:23:49 -0700 (PDT) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH v9 3/3] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Date: Wed, 12 May 2021 12:23:37 -0600 Message-Id: <20210512182337.18563-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210512182337.18563-1-rebecca@nuviainc.com> References: <20210512182337.18563-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x130.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , Richard Henderson , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9c1..f42803ecaf1d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 =3D t; =20 --=20 2.26.2