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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 05/42] target/riscv: Add Shakti C class CPU
Date: Tue, 11 May 2021 20:19:14 +1000
Message-Id: <20210511101951.165287-6-alistair.francis@wdc.com>
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Cc: Vijai Kumar K <vijai@behindbytes.com>, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>, qemu-devel@nongnu.org
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From: Vijai Kumar K <vijai@behindbytes.com>
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 311b1db875..8079da8fa8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -38,6 +38,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 047d6344fe..6842626c69 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -708,6 +708,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D {
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
#endif
};
=20
--=20
2.31.1