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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro
Date: Tue, 11 May 2021 20:19:43 +1000
Message-Id: <20210511101951.165287-35-alistair.francis@wdc.com>
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Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>, qemu-devel@nongnu.org,
Bin Meng <bmeng.cn@gmail.com>
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This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistai=
r.francis@wdc.com
---
target/riscv/cpu_bits.h | 6 ------
target/riscv/csr.c | 9 ++++++++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 24d89939a0..3a0e79e545 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -403,12 +403,6 @@
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000ULL
=20
-#if defined(TARGET_RISCV32)
-#define SSTATUS_SD SSTATUS32_SD
-#elif defined(TARGET_RISCV64)
-#define SSTATUS_SD SSTATUS64_SD
-#endif
-
/* hstatus CSR bits */
#define HSTATUS_VSBE 0x00000020
#define HSTATUS_GVA 0x00000040
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 97ceff718f..41951a0a84 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -459,7 +459,7 @@ static const target_ulong delegable_excps =3D
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI=
E |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ SSTATUS_SUM | SSTATUS_MXR;
static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_=
UEIP;
static const target_ulong hip_writable_mask =3D MIP_VSSIP;
static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M=
IP_VSEIP;
@@ -788,6 +788,13 @@ static RISCVException read_sstatus(CPURISCVState *env,=
int csrno,
target_ulong *val)
{
target_ulong mask =3D (sstatus_v1_10_mask);
+
+ if (riscv_cpu_is_32bit(env)) {
+ mask |=3D SSTATUS32_SD;
+ } else {
+ mask |=3D SSTATUS64_SD;
+ }
+
*val =3D env->mstatus & mask;
return RISCV_EXCP_NONE;
}
--=20
2.31.1