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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 32/42] target/riscv: fix a typo with interrupt names
Date: Tue, 11 May 2021 20:19:41 +1000
Message-Id: <20210511101951.165287-33-alistair.francis@wdc.com>
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From: Emmanuel Blot <emmanuel.blot@sifive.com>
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bf6a00636..04ac03f8c9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] =3D {
"vs_timer",
"m_timer",
"u_external",
+ "s_external",
"vs_external",
- "h_external",
"m_external",
"reserved",
"reserved",
--=20
2.31.1