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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 29/42] target/riscv: fix exception index on instruction
access fault
Date: Tue, 11 May 2021 20:19:38 +1000
Message-Id: <20210511101951.165287-30-alistair.francis@wdc.com>
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From: Emmanuel Blot <emmanuel.blot@sifive.com>
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 659ca8a173..1018c0036d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwa=
ddr physaddr,
=20
if (access_type =3D=3D MMU_DATA_STORE) {
cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
- } else {
+ } else if (access_type =3D=3D MMU_DATA_LOAD) {
cs->exception_index =3D RISCV_EXCP_LOAD_ACCESS_FAULT;
+ } else {
+ cs->exception_index =3D RISCV_EXCP_INST_ACCESS_FAULT;
}
=20
env->badaddr =3D addr;
--=20
2.31.1