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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 28/42] target/riscv: fix vrgather macro index variable type
bug
Date: Tue, 11 May 2021 20:19:37 +1000
Message-Id: <20210511101951.165287-29-alistair.francis@wdc.com>
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Cc: Frank Chang <frank.chang@sifive.com>, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>,
Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
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From: Frank Chang <frank.chang@sifive.com>
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419060302.14075-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 356cef8a09..4651a1e224 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4796,7 +4796,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void=
*vs2, \
uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; =
\
uint32_t vm =3D vext_vm(desc); =
\
uint32_t vl =3D env->vl; =
\
- uint32_t index, i; \
+ uint64_t index; \
+ uint32_t i; \
\
for (i =3D 0; i < vl; i++) { =
\
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
@@ -4826,7 +4827,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1=
, void *vs2, \
uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; =
\
uint32_t vm =3D vext_vm(desc); =
\
uint32_t vl =3D env->vl; =
\
- uint32_t index =3D s1, i; =
\
+ uint64_t index =3D s1; =
\
+ uint32_t i; \
\
for (i =3D 0; i < vl; i++) { =
\
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
--=20
2.31.1