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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP)
Date: Tue, 11 May 2021 20:19:33 +1000
Message-Id: <20210511101951.165287-25-alistair.francis@wdc.com>
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Cc: Hou Weiying <weiying_hou@outlook.com>, qemu-devel@nongnu.org,
 Hongzheng-Li <Ethan.Lee.QNL@gmail.com>,
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From: Hou Weiying <weiying_hou@outlook.com>

This commit adds support for ePMP v0.9.1.

The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUz=
bvc8

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistai=
r.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Update to latest spec
 - Use a switch case to handle ePMP MML permissions
 - Fix a few bugs
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 154 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 146 insertions(+), 8 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e35988eec2..e1f5776316 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -90,11 +90,42 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, =
uint32_t pmp_index)
 static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t =
val)
 {
     if (pmp_index < MAX_RISCV_PMPS) {
-        if (!pmp_is_locked(env, pmp_index)) {
-            env->pmp_state.pmp[pmp_index].cfg_reg =3D val;
-            pmp_update_rule(env, pmp_index);
+        bool locked =3D true;
+
+        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+            /* mseccfg.RLB is set */
+            if (MSECCFG_RLB_ISSET(env)) {
+                locked =3D false;
+            }
+
+            /* mseccfg.MML is not set */
+            if (!MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, pmp_index))=
 {
+                locked =3D false;
+            }
+
+            /* mseccfg.MML is set */
+            if (MSECCFG_MML_ISSET(env)) {
+                /* not adding execute bit */
+                if ((val & PMP_LOCK) !=3D 0 && (val & PMP_EXEC) !=3D PMP_E=
XEC) {
+                    locked =3D false;
+                }
+                /* shared region and not adding X bit */
+                if ((val & PMP_LOCK) !=3D PMP_LOCK &&
+                    (val & 0x7) !=3D (PMP_WRITE | PMP_EXEC)) {
+                    locked =3D false;
+                }
+            }
         } else {
+            if (!pmp_is_locked(env, pmp_index)) {
+                locked =3D false;
+            }
+        }
+
+        if (locked) {
             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked=
\n");
+        } else {
+            env->pmp_state.pmp[pmp_index].cfg_reg =3D val;
+            pmp_update_rule(env, pmp_index);
         }
     } else {
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -217,6 +248,32 @@ static bool pmp_hart_has_privs_default(CPURISCVState *=
env, target_ulong addr,
 {
     bool ret;
=20
+    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+        if (MSECCFG_MMWP_ISSET(env)) {
+            /*
+             * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
+             * so we default to deny all, even for M-mode.
+             */
+            *allowed_privs =3D 0;
+            return false;
+        } else if (MSECCFG_MML_ISSET(env)) {
+            /*
+             * The Machine Mode Lockdown (mseccfg.MML) bit is set
+             * so we can only execute code in M-mode with an applicable
+             * rule. Other modes are disabled.
+             */
+            if (mode =3D=3D PRV_M && !(privs & PMP_EXEC)) {
+                ret =3D true;
+                *allowed_privs =3D PMP_READ | PMP_WRITE;
+            } else {
+                ret =3D false;
+                *allowed_privs =3D 0;
+            }
+
+            return ret;
+        }
+    }
+
     if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode =3D=3D PRV_M)) {
         /*
          * Privileged spec v1.10 states if HW doesn't implement any PMP en=
try
@@ -294,13 +351,94 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul=
ong addr,
             pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
=20
         /*
-         * If the PMP entry is not off and the address is in range, do the=
 priv
-         * check
+         * Convert the PMP permissions to match the truth table in the
+         * ePMP spec.
          */
+        const uint8_t epmp_operation =3D
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
+            (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
+            ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
+
         if (((s + e) =3D=3D 2) && (PMP_AMATCH_OFF !=3D a_field)) {
-            *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC;
-            if ((mode !=3D PRV_M) || pmp_is_locked(env, i)) {
-                *allowed_privs &=3D env->pmp_state.pmp[i].cfg_reg;
+            /*
+             * If the PMP entry is not off and the address is in range,
+             * do the priv check
+             */
+            if (!MSECCFG_MML_ISSET(env)) {
+                /*
+                 * If mseccfg.MML Bit is not set, do pmp priv check
+                 * This will always apply to regular PMP.
+                 */
+                *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC;
+                if ((mode !=3D PRV_M) || pmp_is_locked(env, i)) {
+                    *allowed_privs &=3D env->pmp_state.pmp[i].cfg_reg;
+                }
+            } else {
+                /*
+                 * If mseccfg.MML Bit set, do the enhanced pmp priv check
+                 */
+                if (mode =3D=3D PRV_M) {
+                    switch (epmp_operation) {
+                    case 0:
+                    case 1:
+                    case 4:
+                    case 5:
+                    case 6:
+                    case 7:
+                    case 8:
+                        *allowed_privs =3D 0;
+                        break;
+                    case 2:
+                    case 3:
+                    case 14:
+                        *allowed_privs =3D PMP_READ | PMP_WRITE;
+                        break;
+                    case 9:
+                    case 10:
+                        *allowed_privs =3D PMP_EXEC;
+                        break;
+                    case 11:
+                    case 13:
+                        *allowed_privs =3D PMP_READ | PMP_EXEC;
+                        break;
+                    case 12:
+                    case 15:
+                        *allowed_privs =3D PMP_READ;
+                        break;
+                    }
+                } else {
+                    switch (epmp_operation) {
+                    case 0:
+                    case 8:
+                    case 9:
+                    case 12:
+                    case 13:
+                    case 14:
+                        *allowed_privs =3D 0;
+                        break;
+                    case 1:
+                    case 10:
+                    case 11:
+                        *allowed_privs =3D PMP_EXEC;
+                        break;
+                    case 2:
+                    case 4:
+                    case 15:
+                        *allowed_privs =3D PMP_READ;
+                        break;
+                    case 3:
+                    case 6:
+                        *allowed_privs =3D PMP_READ | PMP_WRITE;
+                        break;
+                    case 5:
+                        *allowed_privs =3D PMP_READ | PMP_EXEC;
+                        break;
+                    case 7:
+                        *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC;
+                        break;
+                    }
+                }
             }
=20
             ret =3D ((privs & *allowed_privs) =3D=3D privs);
--=20
2.31.1