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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 01/42] target/riscv: Remove privilege v1.9 specific CSR
related code
Date: Tue, 11 May 2021 20:19:10 +1000
Message-Id: <20210511101951.165287-2-alistair.francis@wdc.com>
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From: Atish Patra <atish.patra@wdc.com>
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
[Changes by AF:
- Rebase on latest patches
- Bump the vmstate_riscv_cpu version_id and minimum_version_id
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 +---
target/riscv/cpu_bits.h | 23 ---------------------
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 12 +++++------
target/riscv/csr.c | 42 ++++++++++-----------------------------
target/riscv/machine.c | 8 +++-----
target/riscv/translate.c | 4 ++--
7 files changed, 23 insertions(+), 72 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba..311b1db875 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -163,10 +163,8 @@ struct CPURISCVState {
target_ulong mie;
target_ulong mideleg;
=20
- target_ulong sptbr; /* until: priv-1.9.1 */
target_ulong satp; /* since: priv-1.10.0 */
- target_ulong sbadaddr;
- target_ulong mbadaddr;
+ target_ulong stval;
target_ulong medeleg;
=20
target_ulong stvec;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index caf4599207..b42dd4f8d8 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -153,12 +153,6 @@
/* 32-bit only */
#define CSR_MSTATUSH 0x310
=20
-/* Legacy Counter Setup (priv v1.9.1) */
-/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
-#define CSR_MUCOUNTEREN 0x320
-#define CSR_MSCOUNTEREN 0x321
-#define CSR_MHCOUNTEREN 0x322
-
/* Machine Trap Handling */
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
@@ -166,9 +160,6 @@
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
=20
-/* Legacy Machine Trap Handling (priv v1.9.1) */
-#define CSR_MBADADDR 0x343
-
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
@@ -184,9 +175,6 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
=20
-/* Legacy Supervisor Trap Handling (priv v1.9.1) */
-#define CSR_SBADADDR 0x143
-
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
@@ -354,14 +342,6 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
=20
-/* Legacy Machine Protection and Translation (priv v1.9.1) */
-#define CSR_MBASE 0x380
-#define CSR_MBOUND 0x381
-#define CSR_MIBASE 0x382
-#define CSR_MIBOUND 0x383
-#define CSR_MDBASE 0x384
-#define CSR_MDBOUND 0x385
-
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -375,10 +355,8 @@
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
-#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
#define MSTATUS_MXR 0x00080000
-#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
@@ -416,7 +394,6 @@
#define SSTATUS_SPP 0x00000100
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
-#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
#define SSTATUS_MXR 0x00080000
=20
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..86e7dbeb20 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -282,7 +282,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,=
int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscaus=
e);
}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21c54ef561..503c2559f8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -136,8 +136,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
env->vscause =3D env->scause;
env->scause =3D env->scause_hs;
=20
- env->vstval =3D env->sbadaddr;
- env->sbadaddr =3D env->stval_hs;
+ env->vstval =3D env->stval;
+ env->stval =3D env->stval_hs;
=20
env->vsatp =3D env->satp;
env->satp =3D env->satp_hs;
@@ -159,8 +159,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
env->scause_hs =3D env->scause;
env->scause =3D env->vscause;
=20
- env->stval_hs =3D env->sbadaddr;
- env->sbadaddr =3D env->vstval;
+ env->stval_hs =3D env->stval;
+ env->stval =3D env->vstval;
=20
env->satp_hs =3D env->satp;
env->satp =3D env->vsatp;
@@ -1023,7 +1023,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mstatus =3D s;
env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS =
- 1));
env->sepc =3D env->pc;
- env->sbadaddr =3D tval;
+ env->stval =3D tval;
env->htval =3D htval;
env->pc =3D (env->stvec >> 2 << 2) +
((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0);
@@ -1054,7 +1054,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mstatus =3D s;
env->mcause =3D cause | ~(((target_ulong)-1) >> async);
env->mepc =3D env->pc;
- env->mbadaddr =3D tval;
+ env->mtval =3D tval;
env->mtval2 =3D mtval2;
env->pc =3D (env->mtvec >> 2 << 2) +
((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..de7427d8f8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -644,26 +644,6 @@ static int write_mcounteren(CPURISCVState *env, int cs=
rno, target_ulong val)
return 0;
}
=20
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
-static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v=
al)
-{
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- *val =3D env->mcounteren;
- return 0;
-}
-
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
-static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v=
al)
-{
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- env->mcounteren =3D val;
- return 0;
-}
-
/* Machine Trap Handling */
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -701,15 +681,15 @@ static int write_mcause(CPURISCVState *env, int csrno=
, target_ulong val)
return 0;
}
=20
-static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
{
- *val =3D env->mbadaddr;
+ *val =3D env->mtval;
return 0;
}
=20
-static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
{
- env->mbadaddr =3D val;
+ env->mtval =3D val;
return 0;
}
=20
@@ -853,15 +833,15 @@ static int write_scause(CPURISCVState *env, int csrno=
, target_ulong val)
return 0;
}
=20
-static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
+static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
{
- *val =3D env->sbadaddr;
+ *val =3D env->stval;
return 0;
}
=20
-static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
+static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
{
- env->sbadaddr =3D val;
+ env->stval =3D val;
return 0;
}
=20
@@ -1419,13 +1399,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
=20
[CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m=
statush },
=20
- [CSR_MSCOUNTEREN] =3D { "msounteren", any, read_mscounteren, write_m=
scounteren },
-
/* Machine Trap Handling */
[CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch },
[CSR_MEPC] =3D { "mepc", any, read_mepc, write_mepc },
[CSR_MCAUSE] =3D { "mcause", any, read_mcause, write_mcause },
- [CSR_MBADADDR] =3D { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
+ [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip },
=20
/* Supervisor Trap Setup */
@@ -1438,7 +1416,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
[CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch =
},
[CSR_SEPC] =3D { "sepc", smode, read_sepc, write_sepc =
},
[CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause =
},
- [CSR_SBADADDR] =3D { "sbadaddr", smode, read_sbadaddr, write_sbadaddr =
},
+ [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval },
[CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip =
},
=20
/* Supervisor Protection and Translation */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 44d4015bd6..16a08302da 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper =3D {
=20
const VMStateDescription vmstate_riscv_cpu =3D {
.name =3D "cpu",
- .version_id =3D 1,
- .minimum_version_id =3D 1,
+ .version_id =3D 2,
+ .minimum_version_id =3D 2,
.fields =3D (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -165,10 +165,8 @@ const VMStateDescription vmstate_riscv_cpu =3D {
VMSTATE_UINT32(env.miclaim, RISCVCPU),
VMSTATE_UINTTL(env.mie, RISCVCPU),
VMSTATE_UINTTL(env.mideleg, RISCVCPU),
- VMSTATE_UINTTL(env.sptbr, RISCVCPU),
VMSTATE_UINTTL(env.satp, RISCVCPU),
- VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
- VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.stval, RISCVCPU),
VMSTATE_UINTTL(env.medeleg, RISCVCPU),
VMSTATE_UINTTL(env.stvec, RISCVCPU),
VMSTATE_UINTTL(env.sepc, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2f9f5ccc62..26eccc5eb1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -116,7 +116,7 @@ static void generate_exception(DisasContext *ctx, int e=
xcp)
ctx->base.is_jmp =3D DISAS_NORETURN;
}
=20
-static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
+static void generate_exception_mtval(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
@@ -160,7 +160,7 @@ static void gen_exception_illegal(DisasContext *ctx)
=20
static void gen_exception_inst_addr_mis(DisasContext *ctx)
{
- generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
+ generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
=20
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
--=20
2.31.1