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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a
debugger context
Date: Tue, 11 May 2021 20:19:26 +1000
Message-Id: <20210511101951.165287-18-alistair.francis@wdc.com>
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From: Jade Fink <qemu@jade.fyi>
Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.
Signed-off-by: Jade Fink <qemu@jade.fyi>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 99cc388db9..659ca8a173 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -342,12 +342,14 @@ static int get_physical_address_pmp(CPURISCVState *en=
v, int *prot,
* @first_stage: Are we in first stage translation?
* Second stage is used for hypervisor guest translation
* @two_stage: Are we going to perform two stage translation
+ * @is_debug: Is this access from a debugger or the monitor?
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
target_ulong *fault_pte_addr,
int access_type, int mmu_idx,
- bool first_stage, bool two_stage)
+ bool first_stage, bool two_stage,
+ bool is_debug)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -416,7 +418,7 @@ static int get_physical_address(CPURISCVState *env, hwa=
ddr *physical,
widened =3D 2;
}
/* status.SUM will be ignored if execute on background */
- sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background;
+ sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background || is_d=
ebug;
switch (vm) {
case VM_1_10_SV32:
levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break;
@@ -475,7 +477,8 @@ restart:
/* Do the second stage translation on the base PTE address. */
int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro=
t,
base, NULL, MMU_DATA_LOAD,
- mmu_idx, false, true);
+ mmu_idx, false, true,
+ is_debug);
=20
if (vbase_ret !=3D TRANSLATE_SUCCESS) {
if (fault_pte_addr) {
@@ -666,13 +669,13 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, va=
ddr addr)
int mmu_idx =3D cpu_mmu_index(&cpu->env, false);
=20
if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id=
x,
- true, riscv_cpu_virt_enabled(env))) {
+ true, riscv_cpu_virt_enabled(env), true)) {
return -1;
}
=20
if (riscv_cpu_virt_enabled(env)) {
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
- 0, mmu_idx, false, true)) {
+ 0, mmu_idx, false, true, true)) {
return -1;
}
}
@@ -768,7 +771,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in=
t size,
/* Two stage lookup */
ret =3D get_physical_address(env, &pa, &prot, address,
&env->guest_phys_fault_addr, access_typ=
e,
- mmu_idx, true, true);
+ mmu_idx, true, true, false);
=20
/*
* A G-stage exception may be triggered during two state lookup.
@@ -790,7 +793,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in=
t size,
im_address =3D pa;
=20
ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL=
L,
- access_type, mmu_idx, false, true);
+ access_type, mmu_idx, false, true,
+ false);
=20
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physica=
l "
@@ -825,7 +829,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in=
t size,
} else {
/* Single stage lookup */
ret =3D get_physical_address(env, &pa, &prot, address, NULL,
- access_type, mmu_idx, true, false);
+ access_type, mmu_idx, true, false, fals=
e);
=20
qemu_log_mask(CPU_LOG_MMU,
"%s address=3D%" VADDR_PRIx " ret %d physical "
--=20
2.31.1