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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 15/42] hw/opentitan: Update the interrupt layout
Date: Tue, 11 May 2021 20:19:24 +1000
Message-Id: <20210511101951.165287-16-alistair.francis@wdc.com>
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Cc: alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
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Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistai=
r.francis@wdc.com
---
include/hw/riscv/opentitan.h | 16 ++++++++--------
hw/intc/ibex_plic.c | 20 ++++++++++----------
hw/riscv/opentitan.c | 8 ++++----
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index a5ea3a5e4e..aab9bc9245 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -82,14 +82,14 @@ enum {
};
=20
enum {
- IBEX_UART_RX_PARITY_ERR_IRQ =3D 0x28,
- IBEX_UART_RX_TIMEOUT_IRQ =3D 0x27,
- IBEX_UART_RX_BREAK_ERR_IRQ =3D 0x26,
- IBEX_UART_RX_FRAME_ERR_IRQ =3D 0x25,
- IBEX_UART_RX_OVERFLOW_IRQ =3D 0x24,
- IBEX_UART_TX_EMPTY_IRQ =3D 0x23,
- IBEX_UART_RX_WATERMARK_IRQ =3D 0x22,
- IBEX_UART_TX_WATERMARK_IRQ =3D 0x21,
+ IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8,
+ IBEX_UART0_RX_TIMEOUT_IRQ =3D 7,
+ IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6,
+ IBEX_UART0_RX_FRAME_ERR_IRQ =3D 5,
+ IBEX_UART0_RX_OVERFLOW_IRQ =3D 4,
+ IBEX_UART0_TX_EMPTY_IRQ =3D 3,
+ IBEX_UART0_RX_WATERMARK_IRQ =3D 2,
+ IBEX_UART0_TX_WATERMARK_IRQ =3D 1,
};
=20
#endif
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index c1b72fcab0..edf76e4f61 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int i=
rq, int level)
=20
static Property ibex_plic_properties[] =3D {
DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
- DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
+ DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
=20
DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
- DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
+ DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
=20
- DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
- DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
+ DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
+ DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
=20
- DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18=
),
- DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
+ DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30=
),
+ DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
=20
- DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
- DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
+ DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
+ DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
=20
- DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x=
20c),
+ DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x=
318),
=20
- DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
+ DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
DEFINE_PROP_END_OF_LIST(),
};
=20
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index dc9dea117e..557d73726b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -148,16 +148,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev=
_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].bas=
e);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_WATERMARK_IRQ));
+ IBEX_UART0_TX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
1, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_WATERMARK_IRQ));
+ IBEX_UART0_RX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
2, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_EMPTY_IRQ));
+ IBEX_UART0_TX_EMPTY_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
3, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_OVERFLOW_IRQ));
+ IBEX_UART0_RX_OVERFLOW_IRQ));
=20
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
--=20
2.31.1