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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Subject: [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an
enum
Date: Tue, 11 May 2021 20:19:18 +1000
Message-Id: <20210511101951.165287-10-alistair.francis@wdc.com>
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Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>,
Bin Meng <bmeng.cn@gmail.com>, Alistair Francis <alistair.francis@wdc.com>,
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistai=
r.francis@wdc.com
---
target/riscv/cpu_bits.h | 44 ++++++++++++++++++++-------------------
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 4 ++--
3 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b42dd4f8d8..8549d77b4f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -504,27 +504,29 @@
#define DEFAULT_RSTVEC 0x1000
=20
/* Exception causes */
-#define EXCP_NONE -1 /* sentinel value */
-#define RISCV_EXCP_INST_ADDR_MIS 0x0
-#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
-#define RISCV_EXCP_ILLEGAL_INST 0x2
-#define RISCV_EXCP_BREAKPOINT 0x3
-#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
-#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
-#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
-#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
-#define RISCV_EXCP_U_ECALL 0x8
-#define RISCV_EXCP_S_ECALL 0x9
-#define RISCV_EXCP_VS_ECALL 0xa
-#define RISCV_EXCP_M_ECALL 0xb
-#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0=
*/
-#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0=
*/
-#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0=
*/
-#define RISCV_EXCP_SEMIHOST 0x10
-#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
-#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
-#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
-#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
+typedef enum RISCVException {
+ RISCV_EXCP_NONE =3D -1, /* sentinel value */
+ RISCV_EXCP_INST_ADDR_MIS =3D 0x0,
+ RISCV_EXCP_INST_ACCESS_FAULT =3D 0x1,
+ RISCV_EXCP_ILLEGAL_INST =3D 0x2,
+ RISCV_EXCP_BREAKPOINT =3D 0x3,
+ RISCV_EXCP_LOAD_ADDR_MIS =3D 0x4,
+ RISCV_EXCP_LOAD_ACCESS_FAULT =3D 0x5,
+ RISCV_EXCP_STORE_AMO_ADDR_MIS =3D 0x6,
+ RISCV_EXCP_STORE_AMO_ACCESS_FAULT =3D 0x7,
+ RISCV_EXCP_U_ECALL =3D 0x8,
+ RISCV_EXCP_S_ECALL =3D 0x9,
+ RISCV_EXCP_VS_ECALL =3D 0xa,
+ RISCV_EXCP_M_ECALL =3D 0xb,
+ RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */
+ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */
+ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */
+ RISCV_EXCP_SEMIHOST =3D 0x10,
+ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14,
+ RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15,
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16,
+ RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT =3D 0x17,
+} RISCVException;
=20
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6842626c69..e530df9385 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->pc =3D env->resetvec;
env->two_stage_lookup =3D false;
#endif
- cs->exception_index =3D EXCP_NONE;
+ cs->exception_index =3D RISCV_EXCP_NONE;
env->load_res =3D -1;
set_default_nan_mode(1, &env->fp_status);
}
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 503c2559f8..99cc388db9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
- return EXCP_NONE; /* indicates no pending interrupt */
+ return RISCV_EXCP_NONE; /* indicates no pending interrupt */
}
}
#endif
@@ -1069,5 +1069,5 @@ void riscv_cpu_do_interrupt(CPUState *cs)
=20
env->two_stage_lookup =3D false;
#endif
- cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */
+ cs->exception_index =3D RISCV_EXCP_NONE; /* mark handled to qemu */
}
--=20
2.31.1