From nobody Mon Feb 9 18:19:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1620715558; cv=none; d=zohomail.com; s=zohoarc; b=lpNZx8XrIoCucOKL0lq2nlXHTOXAg1CBBugnbD4j2RIHe6gf9AMMhu2AyHS5TyqT2HllNjP+8gcQBJi40XdsrogX8UfPcsxKpyCcKr2SJfTh3KFD8T9iUpwvWeKswItVEIK15ajOLLbi8SXVvkryUcLzkIoYNNIFLAS/p28THlI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620715558; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ltT039/e6WW7MP4OIK211OSVzxRUJvx+Qsvseur6YBw=; b=jcJSrXNs0FFH7wubUemHa8K/D2V7rEzB0XnpWevqu6kjd3h2bR/eTAtfdExN0VYTqb18+ZAdo6sbC8k7p9ssK7GpDDeV8O2mWnZ2jfbuMl/hgfzv5diXeZmFJomGOSG9kX/GmuhcFuXbUSyxwyo/f/B+I581A9vbCdrKQvf8MkA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1620715558645835.0523670523601; Mon, 10 May 2021 23:45:58 -0700 (PDT) Received: from localhost ([::1]:44394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lgM9V-0008Py-GL for importer@patchew.org; Tue, 11 May 2021 02:45:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lgLsg-0006Wy-Ak for qemu-devel@nongnu.org; Tue, 11 May 2021 02:28:34 -0400 Received: from mga06.intel.com ([134.134.136.31]:46437) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lgLsc-0004hV-Bg for qemu-devel@nongnu.org; Tue, 11 May 2021 02:28:34 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 23:28:03 -0700 Received: from icx-2s.bj.intel.com ([10.240.192.119]) by orsmga003.jf.intel.com with ESMTP; 10 May 2021 23:28:02 -0700 IronPort-SDR: h8BONVQzKGOozf32Z7xvyfRavuFpUhyq83thgKl4TAAswcndMuKqdG/I6oCEioZVUvX5i+S3HA XB3DAMhz3KQA== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="260631556" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="260631556" IronPort-SDR: qIhtq5VnbvCC0sfmAE1d8JpWqJeGQHoim8jNn54gFw/venUp33YTo4RWfcZspmMtug/vumI3oN jUL/EsmxgCLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="391281265" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v2 18/32] hw/i386/pc: Account for SGX EPC sections when calculating device memory Date: Tue, 11 May 2021 14:20:37 +0800 Message-Id: <20210511062051.41948-19-yang.zhong@intel.com> X-Mailer: git-send-email 2.29.2.334.gfaefdd61ec In-Reply-To: <20210511062051.41948-1-yang.zhong@intel.com> References: <20210511062051.41948-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=yang.zhong@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, pbonzini@redhat.com, kai.huang@intel.com, seanjc@google.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Sean Christopherson Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX EPC above 4g ends. Use the helpers to adjust the device memory range if SGX EPC exists above 4g. For multiple virtual EPC sections, we just put them together physically contiguous for the simplicity because we don't support EPC NUMA affinity now. Once the SGX EPC NUMA support in the kernel SGX driver, we will support this in the future. Note that SGX EPC is currently hardcoded to reside above 4g. Signed-off-by: Sean Christopherson Signed-off-by: Yang Zhong --- hw/i386/pc.c | 11 ++++++++++- include/hw/i386/sgx-epc.h | 7 +++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8cfaf216e7..d727993dfe 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -926,8 +926,15 @@ void pc_memory_init(PCMachineState *pcms, exit(EXIT_FAILURE); } =20 + if (pcms->sgx_epc !=3D NULL) { + machine->device_memory->base =3D sgx_epc_above_4g_end(pcms->sg= x_epc); + } else { + machine->device_memory->base =3D + 0x100000000ULL + x86ms->above_4g_mem_size; + } + machine->device_memory->base =3D - ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); + ROUND_UP(machine->device_memory->base, 1 * GiB); =20 if (pcmc->enforce_aligned_dimm) { /* size device region assuming 1G page max alignment per slot = */ @@ -1012,6 +1019,8 @@ uint64_t pc_pci_hole64_start(void) if (!pcmc->broken_reserved_end) { hole64_start +=3D memory_region_size(&ms->device_memory->mr); } + } else if (pcms->sgx_epc !=3D NULL) { + hole64_start =3D sgx_epc_above_4g_end(pcms->sgx_epc); } else { hole64_start =3D 0x100000000ULL + x86ms->above_4g_mem_size; } diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h index 8d80b34fb7..743d0a943c 100644 --- a/include/hw/i386/sgx-epc.h +++ b/include/hw/i386/sgx-epc.h @@ -59,4 +59,11 @@ extern int sgx_epc_enabled; =20 int sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size); =20 +static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc) +{ + assert(sgx_epc !=3D NULL && sgx_epc->base >=3D 0x100000000ULL); + + return sgx_epc->base + sgx_epc->size; +} + #endif --=20 2.29.2.334.gfaefdd61ec