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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 13 +++++++++++++ accel/tcg/cputlb.c | 24 +++++++++++++++++------- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5a5f6d4c1a8..9a3dbb7ec08 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -276,6 +276,12 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, target_ulong len, uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, + target_ulong len, uint16_t idxmap, + unsigned bits); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -384,6 +390,13 @@ static inline void tlb_flush_range_by_mmuidx(CPUState = *cpu, target_ulong addr, unsigned bits) { } +static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits) +{ +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 16924ceb777..5314349ef9d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -870,16 +870,18 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, tar= get_ulong addr, tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); } =20 -void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, - target_ulong addr, - uint16_t idxmap, - unsigned bits) +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, + target_ulong addr, target_ulong le= n, + uint16_t idxmap, unsigned bits) { TLBFlushRangeData d; run_on_cpu_data runon; =20 - /* If all bits are significant, this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS) { + /* + * If all bits are significant, and len is small, + * this devolves to tlb_flush_page. + */ + if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap); return; } @@ -891,7 +893,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *s= rc_cpu, =20 /* This should already be page aligned */ d.addr =3D addr & TARGET_PAGE_MASK; - d.len =3D TARGET_PAGE_SIZE; + d.len =3D len; d.idxmap =3D idxmap; d.bits =3D bits; =20 @@ -914,6 +916,14 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *= src_cpu, tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d); } =20 +void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, + target_ulong addr, + uint16_t idxmap, unsigned bits) +{ + tlb_flush_range_by_mmuidx_all_cpus(src_cpu, addr, TARGET_PAGE_SIZE, + idxmap, bits); +} + void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, target_ulong addr, uint16_t idxmap, --=20 2.26.3