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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id j13sm18099051wrw.93.2021.05.09.08.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AOpOu7tS66FjHtPHNLuf/gpZjB/Q3PR0vAi0thAFl78=; b=VKKqMTjYJ/QP1ZoliCBPjA6kytDLigN8jwK4u6Fq+PaeuApWPtkJoQoqE7kM1vuwpP 4uh/FSJXutqo/s+6dg8lg/zkF1Civ2sUJ5vc9wJGTIs6d/RnzfsX33YuqNa+imPxhaQu tddiPQnC4OTNJepyPh6IVOh/g6Ot/QVItzUWMXIE5cOqR5OAJJnCfFDtHsp+7tf1Fzem EQXpIKkWjRvJNp0EeEoZJhQcEYxEUro2YjoEWhUwg6kXaeAlbMwOCdAU8UjTg7E2iAxL BlVZAq9lGA+kWSfPM+URf0pwtbXUQhF33LWaNIlxavP+zAFOkTWd6KQRRMr/LQsTsAXU gERw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AOpOu7tS66FjHtPHNLuf/gpZjB/Q3PR0vAi0thAFl78=; b=Sl1jAN9l38okUaxY0KB/cIFNo70g+VNQuNq+OFpHU++xNFs6Jp1uktav12c+vdNKgL b0COA2+vgRk+raEuiw8q7SScwHkUGbVLa0fpToZfBHLePoJzhfmdb5XOc030G8Om1LCM nK1hsJuX69LkTf2Xt2l6jbHZXzlzU8AkqNMhLD9X7aLOQASs8GdjidRGYKCmKuZVgpU4 Wde/E2kbe6MTXfPrDWPGUBfqtu2W/Vk0Sw/3O/v0/9taZkyW4uphbDjgrPIFEMvzMoCb xY8ep1o2/+El6wrpkTilTB0IG5vFMGTGSVlBz5+IwG9Z4vTsnXc+UCnpt6Mwc+hh7mIo FqIg== X-Gm-Message-State: AOAM5315BLJakcWN7+KfPJ+MJWBppoGLFzYnz5YNlqz9rWoq2g7eaNB7 A2+wIvfmdAw6KXrVRjmfeHQ= X-Google-Smtp-Source: ABdhPJxelpKDfXOn2f4TzC4xGcSTQBg75YosFXUM0RZFcNfJINQzesD145I5GGr22icN9lVY+RR+Ew== X-Received: by 2002:a5d:6383:: with SMTP id p3mr25377465wru.230.1620573427525; Sun, 09 May 2021 08:17:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ??? Date: Sun, 9 May 2021 17:16:18 +0200 Message-Id: <20210509151618.2331764-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Richard Henderson Now than ... /* we use range? FILL ME... */ ... we can remove the encode_pbm_to_runon() and flush_all_helper() calls. Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- XXX proper description, commit might be placed earlier in series. --- accel/tcg/cputlb.c | 86 +++++++++++----------------------------------- 1 file changed, 20 insertions(+), 66 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ad0e44bce63..2f7088614a7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -788,34 +788,6 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState= *cpu, } } =20 -static bool encode_pbm_to_runon(run_on_cpu_data *out, - TLBFlushRangeData d) -{ - /* We need 6 bits to hold to hold @bits up to 63. */ - if (d.idxmap <=3D MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) { - *out =3D RUN_ON_CPU_TARGET_PTR(d.addr | (d.idxmap << 6) | d.bits); - return true; - } - return false; -} - -static TLBFlushRangeData -decode_runon_to_pbm(run_on_cpu_data data) -{ - target_ulong addr_map_bits =3D (target_ulong) data.target_ptr; - return (TLBFlushRangeData){ - .addr =3D addr_map_bits & TARGET_PAGE_MASK, - .idxmap =3D (addr_map_bits & ~TARGET_PAGE_MASK) >> 6, - .bits =3D addr_map_bits & 0x3f - }; -} - -static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu, - run_on_cpu_data runon) -{ - tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon)); -} - static void tlb_flush_range_by_mmuidx_async_1(CPUState *cpu, run_on_cpu_data data) { @@ -829,7 +801,6 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ul= ong addr, unsigned bits) { TLBFlushRangeData d; - run_on_cpu_data runon; =20 /* * If all bits are significant, and len is small, @@ -853,8 +824,6 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ul= ong addr, =20 if (qemu_cpu_is_self(cpu)) { tlb_flush_range_by_mmuidx_async_0(cpu, d); - } else if (encode_pbm_to_runon(&runon, d)) { - async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon= ); } else { /* Otherwise allocate a structure, freed by the worker. */ TLBFlushRangeData *p =3D g_memdup(&d, sizeof(d)); @@ -874,7 +843,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_c= pu, uint16_t idxmap, unsigned bits) { TLBFlushRangeData d; - run_on_cpu_data runon; + CPUState *dst_cpu; =20 /* * If all bits are significant, and len is small, @@ -896,19 +865,13 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src= _cpu, d.idxmap =3D idxmap; d.bits =3D bits; =20 - if (encode_pbm_to_runon(&runon, d)) { - flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, r= unon); - } else { - CPUState *dst_cpu; - - /* Allocate a separate data block for each destination cpu. */ - CPU_FOREACH(dst_cpu) { - if (dst_cpu !=3D src_cpu) { - TLBFlushRangeData *p =3D g_memdup(&d, sizeof(d)); - async_run_on_cpu(dst_cpu, - tlb_flush_range_by_mmuidx_async_1, - RUN_ON_CPU_HOST_PTR(p)); - } + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu !=3D src_cpu) { + TLBFlushRangeData *p =3D g_memdup(&d, sizeof(d)); + async_run_on_cpu(dst_cpu, + tlb_flush_range_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); } } =20 @@ -929,8 +892,8 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, uint16_t idxmap, unsigned bits) { - TLBFlushRangeData d; - run_on_cpu_data runon; + TLBFlushRangeData d, *p; + CPUState *dst_cpu; =20 /* * If all bits are significant, and len is small, @@ -952,27 +915,18 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *src_cpu, d.idxmap =3D idxmap; d.bits =3D bits; =20 - if (encode_pbm_to_runon(&runon, d)) { - flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, r= unon); - async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async= _1, - runon); - } else { - CPUState *dst_cpu; - TLBFlushRangeData *p; - - /* Allocate a separate data block for each destination cpu. */ - CPU_FOREACH(dst_cpu) { - if (dst_cpu !=3D src_cpu) { - p =3D g_memdup(&d, sizeof(d)); - async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_= 1, - RUN_ON_CPU_HOST_PTR(p)); - } + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu !=3D src_cpu) { + p =3D g_memdup(&d, sizeof(d)); + async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); } - - p =3D g_memdup(&d, sizeof(d)); - async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1, - RUN_ON_CPU_HOST_PTR(p)); } + + p =3D g_memdup(&d, sizeof(d)); + async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); } =20 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, --=20 2.26.3