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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Clang has added some builtins for these operations; use them if available. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand --- include/qemu/host-utils.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index cdca2991d8..f1e52851e0 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -272,6 +272,9 @@ static inline int ctpop64(uint64_t val) */ static inline uint8_t revbit8(uint8_t x) { +#if __has_builtin(__builtin_bitreverse8) + return __builtin_bitreverse8(x); +#else /* Assign the correct nibble position. */ x =3D ((x & 0xf0) >> 4) | ((x & 0x0f) << 4); @@ -281,6 +284,7 @@ static inline uint8_t revbit8(uint8_t x) | ((x & 0x22) << 1) | ((x & 0x11) << 3); return x; +#endif } =20 /** @@ -289,6 +293,9 @@ static inline uint8_t revbit8(uint8_t x) */ static inline uint16_t revbit16(uint16_t x) { +#if __has_builtin(__builtin_bitreverse16) + return __builtin_bitreverse16(x); +#else /* Assign the correct byte position. */ x =3D bswap16(x); /* Assign the correct nibble position. */ @@ -300,6 +307,7 @@ static inline uint16_t revbit16(uint16_t x) | ((x & 0x2222) << 1) | ((x & 0x1111) << 3); return x; +#endif } =20 /** @@ -308,6 +316,9 @@ static inline uint16_t revbit16(uint16_t x) */ static inline uint32_t revbit32(uint32_t x) { +#if __has_builtin(__builtin_bitreverse32) + return __builtin_bitreverse32(x); +#else /* Assign the correct byte position. */ x =3D bswap32(x); /* Assign the correct nibble position. */ @@ -319,6 +330,7 @@ static inline uint32_t revbit32(uint32_t x) | ((x & 0x22222222u) << 1) | ((x & 0x11111111u) << 3); return x; +#endif } =20 /** @@ -327,6 +339,9 @@ static inline uint32_t revbit32(uint32_t x) */ static inline uint64_t revbit64(uint64_t x) { +#if __has_builtin(__builtin_bitreverse64) + return __builtin_bitreverse64(x); +#else /* Assign the correct byte position. */ x =3D bswap64(x); /* Assign the correct nibble position. */ @@ -338,6 +353,7 @@ static inline uint64_t revbit64(uint64_t x) | ((x & 0x2222222222222222ull) << 1) | ((x & 0x1111111111111111ull) << 3); return x; +#endif } =20 /* Host type specific sizes of these routines. */ --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620438622; cv=none; d=zohomail.com; s=zohoarc; b=PPOu8BmWu0HlxLimZ4jM84Po1Y/MNVhpwLA7Qziz1mBtzK5Moz27vpQEtq531xXbolpMJn3+gu+99wSkqTDSTiUuwnTGlZi/EVvlXWxMlpVyWEzeKLElpXnLWEVtj2gY/4t13P8V0/MAW5SiyxyeIxc1tV35Ea3mLhRH7ClIRXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620438622; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4FUAz053Q8O4lxDctUgjdKConowhJ6wTho8iZJwG5rg=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" These builtins came in with gcc 5 and clang 3.8, which are slightly newer than our supported minimum compiler versions. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/qemu/host-utils.h | 225 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index f1e52851e0..fd76f0cbd3 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -356,6 +356,231 @@ static inline uint64_t revbit64(uint64_t x) #endif } =20 +/** + * sadd32_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret =3D @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool sadd32_overflow(int32_t x, int32_t y, int32_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >=3D 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret =3D x + y; + return ((*ret ^ x) & ~(x ^ y)) < 0; +#endif +} + +/** + * sadd64_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret =3D @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool sadd64_overflow(int64_t x, int64_t y, int64_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >=3D 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret =3D x + y; + return ((*ret ^ x) & ~(x ^ y)) < 0; +#endif +} + +/** + * uadd32_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret =3D @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool uadd32_overflow(uint32_t x, uint32_t y, uint32_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >=3D 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret =3D x + y; + return *ret < x; +#endif +} + +/** + * uadd64_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret =3D @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool uadd64_overflow(uint64_t x, uint64_t y, uint64_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >=3D 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret =3D x + y; + return *ret < x; +#endif +} + +/** + * ssub32_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for difference + * + * Computes *@ret =3D @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool ssub32_overflow(int32_t x, int32_t y, int32_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >=3D 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret =3D x - y; + return ((*ret ^ x) & (x ^ y)) < 0; +#endif +} + +/** + * ssub64_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for sum + * + * Computes *@ret =3D @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool ssub64_overflow(int64_t x, int64_t y, int64_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >=3D 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret =3D x - y; + return ((*ret ^ x) & (x ^ y)) < 0; +#endif +} + +/** + * usub32_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for sum + * + * Computes *@ret =3D @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool usub32_overflow(uint32_t x, uint32_t y, uint32_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >=3D 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret =3D x - y; + return x < y; +#endif +} + +/** + * usub64_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for sum + * + * Computes *@ret =3D @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool usub64_overflow(uint64_t x, uint64_t y, uint64_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >=3D 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret =3D x - y; + return x < y; +#endif +} + +/** + * smul32_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret =3D @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool smul32_overflow(int32_t x, int32_t y, int32_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >=3D 5 + return __builtin_mul_overflow(x, y, ret); +#else + int64_t z =3D (int64_t)x * y; + *ret =3D z; + return *ret !=3D z; +#endif +} + +/** + * smul64_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret =3D @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool smul64_overflow(int64_t x, int64_t y, int64_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >=3D 5 + return __builtin_mul_overflow(x, y, ret); +#else + uint64_t hi, lo; + muls64(&lo, &hi, x, y); + *ret =3D lo; + return hi !=3D ((int64_t)lo >> 63); +#endif +} + +/** + * umul32_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret =3D @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool umul32_overflow(uint32_t x, uint32_t y, uint32_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >=3D 5 + return __builtin_mul_overflow(x, y, ret); +#else + uint64_t z =3D (uint64_t)x * y; + *ret =3D z; + return z > UINT32_MAX; +#endif +} + +/** + * smul64_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret =3D @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool umul64_overflow(uint64_t x, uint64_t y, uint64_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >=3D 5 + return __builtin_mul_overflow(x, y, ret); +#else + uint64_t hi; + mulu64(ret, &hi, x, y); + return hi !=3D 0; +#endif +} + /* Host type specific sizes of these routines. */ =20 #if ULONG_MAX =3D=3D UINT32_MAX --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620438623; cv=none; d=zohomail.com; s=zohoarc; b=IdsjEeAb5Wj5ov2DU+NjCC2PBo8xlY0qZzH8eijiwOAwUGAPLVChDFvvnnXkqIF6RmJ3/UvuuypZDWLB8jVr+S6hR7kiQJpBApAyaWhEmw9MMIkp9VRSxqSMWO7y/8uHKPiog00gsFdt1PXwxsVBwmCccGjQYgFGmJg5ZKp9j4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620438623; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" These builtins came in clang 3.8, but are not present in gcc through version 11. Even in clang the optimization is not ideal except for x86_64, but no worse than the hand-coding that we currently do. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/qemu/host-utils.h | 50 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index fd76f0cbd3..2ea8b3000b 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -26,6 +26,7 @@ #ifndef HOST_UTILS_H #define HOST_UTILS_H =20 +#include "qemu/compiler.h" #include "qemu/bswap.h" =20 #ifdef CONFIG_INT128 @@ -581,6 +582,55 @@ static inline bool umul64_overflow(uint64_t x, uint64_= t y, uint64_t *ret) #endif } =20 +/** + * uadd64_carry - addition with carry-in and carry-out + * @x, @y: addends + * @pcarry: in-out carry value + * + * Computes @x + @y + *@pcarry, placing the carry-out back + * into *@pcarry and returning the 64-bit sum. + */ +static inline uint64_t uadd64_carry(uint64_t x, uint64_t y, bool *pcarry) +{ +#if __has_builtin(__builtin_addcll) + unsigned long long c =3D *pcarry; + x =3D __builtin_addcll(x, y, c, &c); + *pcarry =3D c & 1; + return x; +#else + bool c =3D *pcarry; + /* This is clang's internal expansion of __builtin_addc. */ + c =3D uadd64_overflow(x, c, &x); + c |=3D uadd64_overflow(x, y, &x); + *pcarry =3D c; + return x; +#endif +} + +/** + * usub64_borrow - subtraction with borrow-in and borrow-out + * @x, @y: addends + * @pborrow: in-out borrow value + * + * Computes @x - @y - *@pborrow, placing the borrow-out back + * into *@pborrow and returning the 64-bit sum. + */ +static inline uint64_t usub64_borrow(uint64_t x, uint64_t y, bool *pborrow) +{ +#if __has_builtin(__builtin_subcll) + unsigned long long b =3D *pborrow; + x =3D __builtin_subcll(x, y, b, &b); + *pborrow =3D b & 1; + return x; +#else + bool b =3D *pborrow; + b =3D usub64_overflow(x, b, &x); + b |=3D usub64_overflow(x, y, &x); + *pborrow =3D b; + return x; +#endif +} + /* Host type specific sizes of these routines. */ =20 #if ULONG_MAX =3D=3D UINT32_MAX --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Obvious uses of the new functions. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-runtime-gvec.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 521da4a813..ac7d28c251 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -1073,9 +1073,8 @@ void HELPER(gvec_ssadd32)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { int32_t ai =3D *(int32_t *)(a + i); int32_t bi =3D *(int32_t *)(b + i); - int32_t di =3D ai + bi; - if (((di ^ ai) &~ (ai ^ bi)) < 0) { - /* Signed overflow. */ + int32_t di; + if (sadd32_overflow(ai, bi, &di)) { di =3D (di < 0 ? INT32_MAX : INT32_MIN); } *(int32_t *)(d + i) =3D di; @@ -1091,9 +1090,8 @@ void HELPER(gvec_ssadd64)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { int64_t ai =3D *(int64_t *)(a + i); int64_t bi =3D *(int64_t *)(b + i); - int64_t di =3D ai + bi; - if (((di ^ ai) &~ (ai ^ bi)) < 0) { - /* Signed overflow. */ + int64_t di; + if (sadd64_overflow(ai, bi, &di)) { di =3D (di < 0 ? INT64_MAX : INT64_MIN); } *(int64_t *)(d + i) =3D di; @@ -1143,9 +1141,8 @@ void HELPER(gvec_sssub32)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { int32_t ai =3D *(int32_t *)(a + i); int32_t bi =3D *(int32_t *)(b + i); - int32_t di =3D ai - bi; - if (((di ^ ai) & (ai ^ bi)) < 0) { - /* Signed overflow. */ + int32_t di; + if (ssub32_overflow(ai, bi, &di)) { di =3D (di < 0 ? INT32_MAX : INT32_MIN); } *(int32_t *)(d + i) =3D di; @@ -1161,9 +1158,8 @@ void HELPER(gvec_sssub64)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { int64_t ai =3D *(int64_t *)(a + i); int64_t bi =3D *(int64_t *)(b + i); - int64_t di =3D ai - bi; - if (((di ^ ai) & (ai ^ bi)) < 0) { - /* Signed overflow. */ + int64_t di; + if (ssub64_overflow(ai, bi, &di)) { di =3D (di < 0 ? INT64_MAX : INT64_MIN); } *(int64_t *)(d + i) =3D di; @@ -1209,8 +1205,8 @@ void HELPER(gvec_usadd32)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { uint32_t ai =3D *(uint32_t *)(a + i); uint32_t bi =3D *(uint32_t *)(b + i); - uint32_t di =3D ai + bi; - if (di < ai) { + uint32_t di; + if (uadd32_overflow(ai, bi, &di)) { di =3D UINT32_MAX; } *(uint32_t *)(d + i) =3D di; @@ -1226,8 +1222,8 @@ void HELPER(gvec_usadd64)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { uint64_t ai =3D *(uint64_t *)(a + i); uint64_t bi =3D *(uint64_t *)(b + i); - uint64_t di =3D ai + bi; - if (di < ai) { + uint64_t di; + if (uadd64_overflow(ai, bi, &di)) { di =3D UINT64_MAX; } *(uint64_t *)(d + i) =3D di; @@ -1273,8 +1269,8 @@ void HELPER(gvec_ussub32)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { uint32_t ai =3D *(uint32_t *)(a + i); uint32_t bi =3D *(uint32_t *)(b + i); - uint32_t di =3D ai - bi; - if (ai < bi) { + uint32_t di; + if (usub32_overflow(ai, bi, &di)) { di =3D 0; } *(uint32_t *)(d + i) =3D di; @@ -1290,8 +1286,8 @@ void HELPER(gvec_ussub64)(void *d, void *a, void *b, = uint32_t desc) for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { uint64_t ai =3D *(uint64_t *)(a + i); uint64_t bi =3D *(uint64_t *)(b + i); - uint64_t di =3D ai - bi; - if (ai < bi) { + uint64_t di; + if (usub64_overflow(ai, bi, &di)) { di =3D 0; } *(uint64_t *)(d + i) =3D di; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439020; cv=none; d=zohomail.com; s=zohoarc; b=LpQO1yANm4D8ChWaNxijLPLKHWuu4yxzYAT1FQIGNYAFkMcssid6Oarbln4ropRp/I3tg1QsEiPBsHfBi+WFjWygfD/864kXo5YK7qejrYmemUE+7CzewLx7lC6vsEtxPPPc05pNSl4cM9gcPOm3hRNiSqSLTCAqxCfL0ssMStw= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/72] tests/fp: add quad support to the benchmark utility Date: Fri, 7 May 2021 18:46:55 -0700 Message-Id: <20210508014802.892561-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e Currently this only support softfloat calculations because working out if the hardware supports 128 bit floats needs configure magic. The 3 op muladd operation is currently unimplemented so commented out for now. Signed-off-by: Alex Benn=C3=A9e Message-Id: <20201020163738.27700-8-alex.bennee@linaro.org> Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- tests/fp/fp-bench.c | 88 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 5 deletions(-) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 4ba5e1d2d4..d319993280 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -14,6 +14,7 @@ #include #include #include "qemu/timer.h" +#include "qemu/int128.h" #include "fpu/softfloat.h" =20 /* amortize the computation of random inputs */ @@ -50,8 +51,10 @@ static const char * const op_names[] =3D { enum precision { PREC_SINGLE, PREC_DOUBLE, + PREC_QUAD, PREC_FLOAT32, PREC_FLOAT64, + PREC_FLOAT128, PREC_MAX_NR, }; =20 @@ -89,6 +92,7 @@ union fp { double d; float32 f32; float64 f64; + float128 f128; uint64_t u64; }; =20 @@ -113,6 +117,10 @@ struct op_desc { static uint64_t random_ops[MAX_OPERANDS] =3D { SEED_A, SEED_B, SEED_C, }; + +static float128 random_quad_ops[MAX_OPERANDS] =3D { + {SEED_A, SEED_B}, {SEED_B, SEED_C}, {SEED_C, SEED_A}, +}; static float_status soft_status; static enum precision precision; static enum op operation; @@ -141,25 +149,45 @@ static void update_random_ops(int n_ops, enum precisi= on prec) int i; =20 for (i =3D 0; i < n_ops; i++) { - uint64_t r =3D random_ops[i]; =20 switch (prec) { case PREC_SINGLE: case PREC_FLOAT32: + { + uint64_t r =3D random_ops[i]; do { r =3D xorshift64star(r); } while (!float32_is_normal(r)); + random_ops[i] =3D r; break; + } case PREC_DOUBLE: case PREC_FLOAT64: + { + uint64_t r =3D random_ops[i]; do { r =3D xorshift64star(r); } while (!float64_is_normal(r)); + random_ops[i] =3D r; break; + } + case PREC_QUAD: + case PREC_FLOAT128: + { + float128 r =3D random_quad_ops[i]; + uint64_t hi =3D r.high; + uint64_t lo =3D r.low; + do { + hi =3D xorshift64star(hi); + lo =3D xorshift64star(lo); + r =3D make_float128(hi, lo); + } while (!float128_is_normal(r)); + random_quad_ops[i] =3D r; + break; + } default: g_assert_not_reached(); } - random_ops[i] =3D r; } } =20 @@ -184,6 +212,13 @@ static void fill_random(union fp *ops, int n_ops, enum= precision prec, ops[i].f64 =3D float64_chs(ops[i].f64); } break; + case PREC_QUAD: + case PREC_FLOAT128: + ops[i].f128 =3D random_quad_ops[i]; + if (no_neg && float128_is_neg(ops[i].f128)) { + ops[i].f128 =3D float128_chs(ops[i].f128); + } + break; default: g_assert_not_reached(); } @@ -345,6 +380,41 @@ static void bench(enum precision prec, enum op op, int= n_ops, bool no_neg) } } break; + case PREC_FLOAT128: + fill_random(ops, n_ops, prec, no_neg); + t0 =3D get_clock(); + for (i =3D 0; i < OPS_PER_ITER; i++) { + float128 a =3D ops[0].f128; + float128 b =3D ops[1].f128; + /* float128 c =3D ops[2].f128; */ + + switch (op) { + case OP_ADD: + res.f128 =3D float128_add(a, b, &soft_status); + break; + case OP_SUB: + res.f128 =3D float128_sub(a, b, &soft_status); + break; + case OP_MUL: + res.f128 =3D float128_mul(a, b, &soft_status); + break; + case OP_DIV: + res.f128 =3D float128_div(a, b, &soft_status); + break; + /* case OP_FMA: */ + /* res.f128 =3D float128_muladd(a, b, c, 0, &soft_stat= us); */ + /* break; */ + case OP_SQRT: + res.f128 =3D float128_sqrt(a, &soft_status); + break; + case OP_CMP: + res.u64 =3D float128_compare_quiet(a, b, &soft_status); + break; + default: + g_assert_not_reached(); + } + } + break; default: g_assert_not_reached(); } @@ -369,7 +439,8 @@ static void bench(enum precision prec, enum op op, int = n_ops, bool no_neg) GEN_BENCH(bench_ ## opname ## _float, float, PREC_SINGLE, op, n_ops) \ GEN_BENCH(bench_ ## opname ## _double, double, PREC_DOUBLE, op, n_ops)= \ GEN_BENCH(bench_ ## opname ## _float32, float32, PREC_FLOAT32, op, n_o= ps) \ - GEN_BENCH(bench_ ## opname ## _float64, float64, PREC_FLOAT64, op, n_o= ps) + GEN_BENCH(bench_ ## opname ## _float64, float64, PREC_FLOAT64, op, n_o= ps) \ + GEN_BENCH(bench_ ## opname ## _float128, float128, PREC_FLOAT128, op, = n_ops) =20 GEN_BENCH_ALL_TYPES(add, OP_ADD, 2) GEN_BENCH_ALL_TYPES(sub, OP_SUB, 2) @@ -383,7 +454,8 @@ GEN_BENCH_ALL_TYPES(cmp, OP_CMP, 2) GEN_BENCH_NO_NEG(bench_ ## name ## _float, float, PREC_SINGLE, op, n) \ GEN_BENCH_NO_NEG(bench_ ## name ## _double, double, PREC_DOUBLE, op, n= ) \ GEN_BENCH_NO_NEG(bench_ ## name ## _float32, float32, PREC_FLOAT32, op= , n) \ - GEN_BENCH_NO_NEG(bench_ ## name ## _float64, float64, PREC_FLOAT64, op= , n) + GEN_BENCH_NO_NEG(bench_ ## name ## _float64, float64, PREC_FLOAT64, op= , n) \ + GEN_BENCH_NO_NEG(bench_ ## name ## _float128, float128, PREC_FLOAT128,= op, n) =20 GEN_BENCH_ALL_TYPES_NO_NEG(sqrt, OP_SQRT, 1) #undef GEN_BENCH_ALL_TYPES_NO_NEG @@ -397,6 +469,7 @@ GEN_BENCH_ALL_TYPES_NO_NEG(sqrt, OP_SQRT, 1) [PREC_DOUBLE] =3D bench_ ## opname ## _double, \ [PREC_FLOAT32] =3D bench_ ## opname ## _float32, \ [PREC_FLOAT64] =3D bench_ ## opname ## _float64, \ + [PREC_FLOAT128] =3D bench_ ## opname ## _float128, \ } =20 static const bench_func_t bench_funcs[OP_MAX_NR][PREC_MAX_NR] =3D { @@ -445,7 +518,7 @@ static void usage_complete(int argc, char *argv[]) fprintf(stderr, " -h =3D show this help message.\n"); fprintf(stderr, " -o =3D floating point operation (%s). Default: %s\n", op_list, op_names[0]); - fprintf(stderr, " -p =3D floating point precision (single, double). " + fprintf(stderr, " -p =3D floating point precision (single, double, qua= d[soft only]). " "Default: single\n"); fprintf(stderr, " -r =3D rounding mode (even, zero, down, up, tieaway)= . " "Default: even\n"); @@ -565,6 +638,8 @@ static void parse_args(int argc, char *argv[]) precision =3D PREC_SINGLE; } else if (!strcmp(optarg, "double")) { precision =3D PREC_DOUBLE; + } else if (!strcmp(optarg, "quad")) { + precision =3D PREC_QUAD; } else { fprintf(stderr, "Unsupported precision '%s'\n", optarg); exit(EXIT_FAILURE); @@ -608,6 +683,9 @@ static void parse_args(int argc, char *argv[]) case PREC_DOUBLE: precision =3D PREC_FLOAT64; break; + case PREC_QUAD: + precision =3D PREC_FLOAT128; + break; default: g_assert_not_reached(); } --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439437; cv=none; d=zohomail.com; s=zohoarc; b=XXoX96oTmlyv/YzRZVZJr5ut+CAPBb/QuDRA+DzXhCmtzoCm81MQ/mfptFRDQFA/Qs2RNyeFMi31Rq+7c4OgkGPgIz3cugLSJXzSrdjsMAk4TRgM6Xv6ictxiikHSPBpw4yV4vOe+D53jwg9jXuibq/Ya3NWzOzGUN+zAws438E= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/72] softfloat: Move the binary point to the msb Date: Fri, 7 May 2021 18:46:56 -0700 Message-Id: <20210508014802.892561-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rather than point the binary point at msb-1, put it at the msb. Use uadd64_overflow to detect when addition overflows instead of DECOMPOSED_OVERFLOW_BIT. This reduces the number of special cases within the code, such as shifting an int64_t either left or right during conversion. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 169 +++++++++++++++++++----------------------------- 1 file changed, 66 insertions(+), 103 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 67cfa0fd82..cd777743f1 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -503,9 +503,8 @@ typedef struct { bool sign; } FloatParts; =20 -#define DECOMPOSED_BINARY_POINT (64 - 2) +#define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) -#define DECOMPOSED_OVERFLOW_BIT (DECOMPOSED_IMPLICIT_BIT << 1) =20 /* Structure holding all of the relevant parameters for a format. * exp_size: the size of the exponent field @@ -657,7 +656,7 @@ static FloatParts sf_canonicalize(FloatParts part, cons= t FloatFmt *parm, part.cls =3D float_class_zero; part.frac =3D 0; } else { - int shift =3D clz64(part.frac) - 1; + int shift =3D clz64(part.frac); part.cls =3D float_class_normal; part.exp =3D parm->frac_shift - parm->exp_bias - shift + 1; part.frac <<=3D shift; @@ -727,9 +726,8 @@ static FloatParts round_canonical(FloatParts p, float_s= tatus *s, if (likely(exp > 0)) { if (frac & round_mask) { flags |=3D float_flag_inexact; - frac +=3D inc; - if (frac & DECOMPOSED_OVERFLOW_BIT) { - frac >>=3D 1; + if (uadd64_overflow(frac, inc, &frac)) { + frac =3D (frac >> 1) | DECOMPOSED_IMPLICIT_BIT; exp++; } } @@ -758,9 +756,12 @@ static FloatParts round_canonical(FloatParts p, float_= status *s, p.cls =3D float_class_zero; goto do_zero; } else { - bool is_tiny =3D s->tininess_before_rounding - || (exp < 0) - || !((frac + inc) & DECOMPOSED_OVERFLOW_BIT); + bool is_tiny =3D s->tininess_before_rounding || (exp < 0); + + if (!is_tiny) { + uint64_t discard; + is_tiny =3D !uadd64_overflow(frac, inc, &discard); + } =20 shift64RightJamming(frac, 1 - exp, &frac); if (frac & round_mask) { @@ -985,7 +986,7 @@ static FloatParts addsub_floats(FloatParts a, FloatPart= s b, bool subtract, a.cls =3D float_class_zero; a.sign =3D s->float_rounding_mode =3D=3D float_round_down; } else { - int shift =3D clz64(a.frac) - 1; + int shift =3D clz64(a.frac); a.frac =3D a.frac << shift; a.exp =3D a.exp - shift; a.sign =3D a_sign; @@ -1022,9 +1023,10 @@ static FloatParts addsub_floats(FloatParts a, FloatP= arts b, bool subtract, shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); a.exp =3D b.exp; } - a.frac +=3D b.frac; - if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + + if (uadd64_overflow(a.frac, b.frac, &a.frac)) { shift64RightJamming(a.frac, 1, &a.frac); + a.frac |=3D DECOMPOSED_IMPLICIT_BIT; a.exp +=3D 1; } return a; @@ -1219,16 +1221,17 @@ static FloatParts mul_floats(FloatParts a, FloatPar= ts b, float_status *s) int exp =3D a.exp + b.exp; =20 mul64To128(a.frac, b.frac, &hi, &lo); - shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); - if (lo & DECOMPOSED_OVERFLOW_BIT) { - shift64RightJamming(lo, 1, &lo); + if (hi & DECOMPOSED_IMPLICIT_BIT) { exp +=3D 1; + } else { + hi <<=3D 1; } + hi |=3D (lo !=3D 0); =20 /* Re-use a */ a.exp =3D exp; a.sign =3D sign; - a.frac =3D lo; + a.frac =3D hi; return a; } /* handle all the NaN cases */ @@ -1411,56 +1414,41 @@ static FloatParts muladd_floats(FloatParts a, Float= Parts b, FloatParts c, =20 p_exp =3D a.exp + b.exp; =20 - /* Multiply of 2 62-bit numbers produces a (2*62) =3D=3D 124-bit - * result. - */ mul64To128(a.frac, b.frac, &hi, &lo); - /* binary point now at bit 124 */ =20 - /* check for overflow */ - if (hi & (1ULL << (DECOMPOSED_BINARY_POINT * 2 + 1 - 64))) { - shift128RightJamming(hi, lo, 1, &hi, &lo); + /* Renormalize to the msb. */ + if (hi & DECOMPOSED_IMPLICIT_BIT) { p_exp +=3D 1; + } else { + shortShift128Left(hi, lo, 1, &hi, &lo); } =20 /* + add/sub */ - if (c.cls =3D=3D float_class_zero) { - /* move binary point back to 62 */ - shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); - } else { + if (c.cls !=3D float_class_zero) { int exp_diff =3D p_exp - c.exp; if (p_sign =3D=3D c.sign) { /* Addition */ if (exp_diff <=3D 0) { - shift128RightJamming(hi, lo, - DECOMPOSED_BINARY_POINT - exp_diff, - &hi, &lo); - lo +=3D c.frac; + shift64RightJamming(hi, -exp_diff, &hi); p_exp =3D c.exp; + if (uadd64_overflow(hi, c.frac, &hi)) { + shift64RightJamming(hi, 1, &hi); + hi |=3D DECOMPOSED_IMPLICIT_BIT; + p_exp +=3D 1; + } } else { - uint64_t c_hi, c_lo; - /* shift c to the same binary point as the product (124) */ - c_hi =3D c.frac >> 2; - c_lo =3D 0; - shift128RightJamming(c_hi, c_lo, - exp_diff, - &c_hi, &c_lo); - add128(hi, lo, c_hi, c_lo, &hi, &lo); - /* move binary point back to 62 */ - shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi,= &lo); + uint64_t c_hi, c_lo, over; + shift128RightJamming(c.frac, 0, exp_diff, &c_hi, &c_lo); + add192(0, hi, lo, 0, c_hi, c_lo, &over, &hi, &lo); + if (over) { + shift64RightJamming(hi, 1, &hi); + hi |=3D DECOMPOSED_IMPLICIT_BIT; + p_exp +=3D 1; + } } - - if (lo & DECOMPOSED_OVERFLOW_BIT) { - shift64RightJamming(lo, 1, &lo); - p_exp +=3D 1; - } - } else { /* Subtraction */ - uint64_t c_hi, c_lo; - /* make C binary point match product at bit 124 */ - c_hi =3D c.frac >> 2; - c_lo =3D 0; + uint64_t c_hi =3D c.frac, c_lo =3D 0; =20 if (exp_diff <=3D 0) { shift128RightJamming(hi, lo, -exp_diff, &hi, &lo); @@ -1495,20 +1483,15 @@ static FloatParts muladd_floats(FloatParts a, Float= Parts b, FloatParts c, /* Normalizing to a binary point of 124 is the correct adjust for the exponent. However since we're shifting, we might as well put the binary point back - at 62 where we really want it. Therefore shift as + at 63 where we really want it. Therefore shift as if we're leaving 1 bit at the top of the word, but adjust the exponent as if we're leaving 3 bits. */ - shift -=3D 1; - if (shift >=3D 64) { - lo =3D lo << (shift - 64); - } else { - hi =3D (hi << shift) | (lo >> (64 - shift)); - lo =3D hi | ((lo << shift) !=3D 0); - } - p_exp -=3D shift - 2; + shift128Left(hi, lo, shift, &hi, &lo); + p_exp -=3D shift; } } } + hi |=3D (lo !=3D 0); =20 if (flags & float_muladd_halve_result) { p_exp -=3D 1; @@ -1518,7 +1501,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, a.cls =3D float_class_normal; a.sign =3D p_sign ^ sign_flip; a.exp =3D p_exp; - a.frac =3D lo; + a.frac =3D hi; =20 return a; } @@ -1742,25 +1725,17 @@ static FloatParts div_floats(FloatParts a, FloatPar= ts b, float_status *s) * exponent to match. * * The udiv_qrnnd algorithm that we're using requires normalizatio= n, - * i.e. the msb of the denominator must be set. Since we know that - * DECOMPOSED_BINARY_POINT is msb-1, the inputs must be shifted le= ft - * by one (more), and the remainder must be shifted right by one. + * i.e. the msb of the denominator must be set, which is already t= rue. */ if (a.frac < b.frac) { exp -=3D 1; - shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 2, &n1, &n0); - } else { shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, &n1, &n0); + } else { + shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, &n1, &n0); } - q =3D udiv_qrnnd(&r, n1, n0, b.frac << 1); + q =3D udiv_qrnnd(&r, n1, n0, b.frac); =20 - /* - * Set lsb if there is a remainder, to set inexact. - * As mentioned above, to find the actual value of the remainder we - * would need to shift right, but (1) we are only concerned about - * non-zero-ness, and (2) the remainder will always be even because - * both inputs to the division primitive are even. - */ + /* Set lsb if there is a remainder, to set inexact. */ a.frac =3D q | (r !=3D 0); a.sign =3D sign; a.exp =3D exp; @@ -2135,12 +2110,12 @@ static FloatParts round_to_int(FloatParts a, FloatR= oundMode rmode, =20 if (a.frac & rnd_mask) { s->float_exception_flags |=3D float_flag_inexact; - a.frac +=3D inc; - a.frac &=3D ~rnd_mask; - if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + if (uadd64_overflow(a.frac, inc, &a.frac)) { a.frac >>=3D 1; + a.frac |=3D DECOMPOSED_IMPLICIT_BIT; a.exp++; } + a.frac &=3D ~rnd_mask; } } break; @@ -2213,10 +2188,8 @@ static int64_t round_to_int_and_pack(FloatParts in, = FloatRoundMode rmode, case float_class_zero: return 0; case float_class_normal: - if (p.exp < DECOMPOSED_BINARY_POINT) { + if (p.exp <=3D DECOMPOSED_BINARY_POINT) { r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - } else if (p.exp - DECOMPOSED_BINARY_POINT < 2) { - r =3D p.frac << (p.exp - DECOMPOSED_BINARY_POINT); } else { r =3D UINT64_MAX; } @@ -2498,10 +2471,8 @@ static uint64_t round_to_uint_and_pack(FloatParts in= , FloatRoundMode rmode, return 0; } =20 - if (p.exp < DECOMPOSED_BINARY_POINT) { + if (p.exp <=3D DECOMPOSED_BINARY_POINT) { r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - } else if (p.exp - DECOMPOSED_BINARY_POINT < 2) { - r =3D p.frac << (p.exp - DECOMPOSED_BINARY_POINT); } else { s->float_exception_flags =3D orig_flags | float_flag_invalid; return max; @@ -2765,11 +2736,11 @@ static FloatParts int_to_float(int64_t a, int scale= , float_status *status) f =3D -f; r.sign =3D true; } - shift =3D clz64(f) - 1; + shift =3D clz64(f); scale =3D MIN(MAX(scale, -0x10000), 0x10000); =20 r.exp =3D DECOMPOSED_BINARY_POINT - shift + scale; - r.frac =3D (shift < 0 ? DECOMPOSED_IMPLICIT_BIT : f << shift); + r.frac =3D f << shift; } =20 return r; @@ -2920,21 +2891,16 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status = *status) static FloatParts uint_to_float(uint64_t a, int scale, float_status *statu= s) { FloatParts r =3D { .sign =3D false }; + int shift; =20 if (a =3D=3D 0) { r.cls =3D float_class_zero; } else { scale =3D MIN(MAX(scale, -0x10000), 0x10000); + shift =3D clz64(a); r.cls =3D float_class_normal; - if ((int64_t)a < 0) { - r.exp =3D DECOMPOSED_BINARY_POINT + 1 + scale; - shift64RightJamming(a, 1, &a); - r.frac =3D a; - } else { - int shift =3D clz64(a) - 1; - r.exp =3D DECOMPOSED_BINARY_POINT - shift + scale; - r.frac =3D a << shift; - } + r.exp =3D DECOMPOSED_BINARY_POINT - shift + scale; + r.frac =3D a << shift; } =20 return r; @@ -3475,12 +3441,9 @@ static FloatParts sqrt_float(FloatParts a, float_sta= tus *s, const FloatFmt *p) /* We need two overflow bits at the top. Adding room for that is a * right shift. If the exponent is odd, we can discard the low bit * by multiplying the fraction by 2; that's a left shift. Combine - * those and we shift right if the exponent is even. + * those and we shift right by 1 if the exponent is odd, otherwise 2. */ - a_frac =3D a.frac; - if (!(a.exp & 1)) { - a_frac >>=3D 1; - } + a_frac =3D a.frac >> (2 - (a.exp & 1)); a.exp >>=3D 1; =20 /* Bit-by-bit computation of sqrt. */ @@ -3488,10 +3451,10 @@ static FloatParts sqrt_float(FloatParts a, float_st= atus *s, const FloatFmt *p) s_frac =3D 0; =20 /* Iterate from implicit bit down to the 3 extra bits to compute a - * properly rounded result. Remember we've inserted one more bit - * at the top, so these positions are one less. + * properly rounded result. Remember we've inserted two more bits + * at the top, so these positions are two less. */ - bit =3D DECOMPOSED_BINARY_POINT - 1; + bit =3D DECOMPOSED_BINARY_POINT - 2; last_bit =3D MAX(p->frac_shift - 4, 0); do { uint64_t q =3D 1ULL << bit; @@ -3507,7 +3470,7 @@ static FloatParts sqrt_float(FloatParts a, float_stat= us *s, const FloatFmt *p) /* Undo the right shift done above. If there is any remaining * fraction, the result is inexact. Set the sticky bit. */ - a.frac =3D (r_frac << 1) + (a_frac !=3D 0); + a.frac =3D (r_frac << 2) + (a_frac !=3D 0); =20 return a; } --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439196; cv=none; d=zohomail.com; s=zohoarc; b=IaBfGvp+1uutm55bfzjhyUpujweLf2rjJ9SsbddhWrdJqHX2HFzC8tM+e8id9ZlKMMyxztjX06LWPY2Djh7SvkN2Oi5UkqdxXnzyYwumXo40iU1EFiOTXGqHztic4hc4YkPB+5FKxg3tIgC6uG7Hg6Rgh/FVULOp2woZk0OktKo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620439196; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/fpu/softfloat.h | 5 ++++- fpu/softfloat-specialize.c.inc | 12 ------------ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 78ad5ca738..019c2ec66d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -100,7 +100,10 @@ typedef enum { | Routine to raise any or all of the software IEC/IEEE floating-point | exception flags. *-------------------------------------------------------------------------= ---*/ -void float_raise(uint8_t flags, float_status *status); +static inline void float_raise(uint8_t flags, float_status *status) +{ + status->float_exception_flags |=3D flags; +} =20 /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9ea318f3e2..487b29155c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -228,18 +228,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity =3D make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); =20 -/*------------------------------------------------------------------------= ---- -| Raises the exceptions specified by `flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply `float_exception_flags |=3D flags;'. -*-------------------------------------------------------------------------= ---*/ - -void float_raise(uint8_t flags, float_status *status) -{ - status->float_exception_flags |=3D flags; -} - /*------------------------------------------------------------------------= ---- | Internal canonical NaN format. *-------------------------------------------------------------------------= ---*/ --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620438808; cv=none; d=zohomail.com; s=zohoarc; b=UYoEGHRy4soknOoeIza+Yc6kPkHwZOLNPG/DZUDZgBwIYETrTYjud1eiURyTLq9+p+2PrsHn2glrjmzHwQK+C/D7lveP1iuxinD7v3dyLN9q9LssneDrXaZKryHrSYyXG1YhaVkq5YGV/ytw1nEiHTZvgPBf0U1vNK74d/fTl5M= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/72] softfloat: Use float_raise in more places Date: Fri, 7 May 2021 18:46:58 -0700 Message-Id: <20210508014802.892561-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We have been somewhat inconsistent about when to use float_raise and when to or in the bit by hand. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- fpu/softfloat.c | 87 +++++++++++++++++++++++++------------------------ 1 file changed, 44 insertions(+), 43 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cd777743f1..93fe785809 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -132,7 +132,7 @@ this code that are retained. if (unlikely(soft_t ## _is_denormal(*a))) { \ *a =3D soft_t ## _set_sign(soft_t ## _zero, \ soft_t ## _is_neg(*a)); \ - s->float_exception_flags |=3D float_flag_input_denormal; \ + float_raise(float_flag_input_denormal, s); \ } \ } =20 @@ -360,7 +360,7 @@ float32_gen2(float32 xa, float32 xb, float_status *s, =20 ur.h =3D hard(ua.h, ub.h); if (unlikely(f32_is_inf(ur))) { - s->float_exception_flags |=3D float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabsf(ur.h) <=3D FLT_MIN) && post(ua, ub)) { goto soft; } @@ -391,7 +391,7 @@ float64_gen2(float64 xa, float64 xb, float_status *s, =20 ur.h =3D hard(ua.h, ub.h); if (unlikely(f64_is_inf(ur))) { - s->float_exception_flags |=3D float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabs(ur.h) <=3D DBL_MIN) && post(ua, ub)) { goto soft; } @@ -880,7 +880,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) { switch (a.cls) { case float_class_snan: - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); a =3D parts_silence_nan(a, s); /* fall through */ case float_class_qnan: @@ -898,7 +898,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); } =20 if (s->default_nan_mode) { @@ -922,7 +922,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, int which; =20 if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); } =20 which =3D pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); @@ -1241,7 +1241,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts= b, float_status *s) /* Inf * Zero =3D=3D NaN */ if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } /* Multiply by 0 or Inf */ @@ -1356,6 +1356,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, } =20 if (inf_zero) { + float_raise(float_flag_invalid, s); s->float_exception_flags |=3D float_flag_invalid; return parts_default_nan(s); } @@ -1380,7 +1381,7 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, =20 if (c.cls =3D=3D float_class_inf) { if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } else { a.cls =3D float_class_inf; @@ -1598,7 +1599,7 @@ float32_muladd(float32 xa, float32 xb, float32 xc, in= t flags, float_status *s) ur.h =3D fmaf(ua.h, ub.h, uc.h); =20 if (unlikely(f32_is_inf(ur))) { - s->float_exception_flags |=3D float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabsf(ur.h) <=3D FLT_MIN)) { ua =3D ua_orig; uc =3D uc_orig; @@ -1669,7 +1670,7 @@ float64_muladd(float64 xa, float64 xb, float64 xc, in= t flags, float_status *s) ur.h =3D fma(ua.h, ub.h, uc.h); =20 if (unlikely(f64_is_inf(ur))) { - s->float_exception_flags |=3D float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabs(ur.h) <=3D FLT_MIN)) { ua =3D ua_orig; uc =3D uc_orig; @@ -1749,7 +1750,7 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) if (a.cls =3D=3D b.cls && (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } /* Inf / x or 0 / x */ @@ -1759,7 +1760,7 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) } /* Div 0 =3D> Inf */ if (b.cls =3D=3D float_class_zero) { - s->float_exception_flags |=3D float_flag_divbyzero; + float_raise(float_flag_divbyzero, s); a.cls =3D float_class_inf; a.sign =3D sign; return a; @@ -1895,7 +1896,7 @@ static FloatParts float_to_float(FloatParts a, const = FloatFmt *dstf, /* There is no NaN in the destination format. Raise Invalid * and return a zero with the sign of the input NaN. */ - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); a.cls =3D float_class_zero; a.frac =3D 0; a.exp =3D 0; @@ -1905,7 +1906,7 @@ static FloatParts float_to_float(FloatParts a, const = FloatFmt *dstf, /* There is no Inf in the destination format. Raise Invalid * and return the maximum normal with the correct sign. */ - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); a.cls =3D float_class_normal; a.exp =3D dstf->exp_max; a.frac =3D ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; @@ -1916,7 +1917,7 @@ static FloatParts float_to_float(FloatParts a, const = FloatFmt *dstf, } } else if (is_nan(a.cls)) { if (is_snan(a.cls)) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); a =3D parts_silence_nan(a, s); } if (s->default_nan_mode) { @@ -2048,7 +2049,7 @@ static FloatParts round_to_int(FloatParts a, FloatRou= ndMode rmode, if (a.exp < 0) { bool one; /* all fractional */ - s->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, s); switch (rmode) { case float_round_nearest_even: one =3D a.exp =3D=3D -1 && a.frac > DECOMPOSED_IMPLICIT_BI= T; @@ -2109,7 +2110,7 @@ static FloatParts round_to_int(FloatParts a, FloatRou= ndMode rmode, } =20 if (a.frac & rnd_mask) { - s->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, s); if (uadd64_overflow(a.frac, inc, &a.frac)) { a.frac >>=3D 1; a.frac |=3D DECOMPOSED_IMPLICIT_BIT; @@ -3188,7 +3189,7 @@ static FloatRelation compare_floats(FloatParts a, Flo= atParts b, bool is_quiet, if (!is_quiet || a.cls =3D=3D float_class_snan || b.cls =3D=3D float_class_snan) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); } return float_relation_unordered; } @@ -3429,7 +3430,7 @@ static FloatParts sqrt_float(FloatParts a, float_stat= us *s, const FloatFmt *p) return a; /* sqrt(+-0) =3D +-0 */ } if (a.sign) { - s->float_exception_flags |=3D float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } if (a.cls =3D=3D float_class_inf) { @@ -3760,7 +3761,7 @@ static int32_t roundAndPackInt32(bool zSign, uint64_t= absZ, return zSign ? INT32_MIN : INT32_MAX; } if (roundBits) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; =20 @@ -3822,7 +3823,7 @@ static int64_t roundAndPackInt64(bool zSign, uint64_t= absZ0, uint64_t absZ1, return zSign ? INT64_MIN : INT64_MAX; } if (absZ1) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; =20 @@ -3883,7 +3884,7 @@ static int64_t roundAndPackUint64(bool zSign, uint64_= t absZ0, } =20 if (absZ1) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return absZ0; } @@ -3994,7 +3995,7 @@ static float32 roundAndPackFloat32(bool zSign, int zE= xp, uint32_t zSig, } } if (roundBits) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig =3D ( zSig + roundIncrement )>>7; if (!(roundBits ^ 0x40) && roundNearestEven) { @@ -4150,7 +4151,7 @@ static float64 roundAndPackFloat64(bool zSign, int zE= xp, uint64_t zSig, } } if (roundBits) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig =3D ( zSig + roundIncrement )>>10; if (!(roundBits ^ 0x200) && roundNearestEven) { @@ -4284,7 +4285,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, bool zSign, float_raise(float_flag_underflow, status); } if (roundBits) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig0 +=3D roundIncrement; if ( (int64_t) zSig0 < 0 ) zExp =3D 1; @@ -4297,7 +4298,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, bool zSign, } } if (roundBits) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig0 +=3D roundIncrement; if ( zSig0 < roundIncrement ) { @@ -4360,7 +4361,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, bool zSign, float_raise(float_flag_underflow, status); } if (zSig1) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } switch (roundingMode) { case float_round_nearest_even: @@ -4390,7 +4391,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, bool zSign, } } if (zSig1) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } if ( increment ) { ++zSig0; @@ -4667,7 +4668,7 @@ static float128 roundAndPackFloat128(bool zSign, int3= 2_t zExp, } } if (zSig2) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } if ( increment ) { add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 ); @@ -5405,7 +5406,7 @@ int32_t floatx80_to_int32_round_to_zero(floatx80 a, f= loat_status *status) } else if ( aExp < 0x3FFF ) { if (aExp || aSig) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } @@ -5420,7 +5421,7 @@ int32_t floatx80_to_int32_round_to_zero(floatx80 a, f= loat_status *status) return aSign ? (int32_t) 0x80000000 : 0x7FFFFFFF; } if ( ( aSig<float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; =20 @@ -5504,13 +5505,13 @@ int64_t floatx80_to_int64_round_to_zero(floatx80 a,= float_status *status) } else if ( aExp < 0x3FFF ) { if (aExp | aSig) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } z =3D aSig>>( - shiftCount ); if ( (uint64_t) ( aSig<<( shiftCount & 63 ) ) ) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } if ( aSign ) z =3D - z; return z; @@ -5661,7 +5662,7 @@ floatx80 floatx80_round_to_int(floatx80 a, float_stat= us *status) && ( (uint64_t) ( extractFloatx80Frac( a ) ) =3D=3D 0 ) ) { return a; } - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); aSign =3D extractFloatx80Sign( a ); switch (status->float_rounding_mode) { case float_round_nearest_even: @@ -5728,7 +5729,7 @@ floatx80 floatx80_round_to_int(floatx80 a, float_stat= us *status) z.low =3D UINT64_C(0x8000000000000000); } if (z.low !=3D a.low) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; =20 @@ -6364,7 +6365,7 @@ int32_t float128_to_int32_round_to_zero(float128 a, f= loat_status *status) } else if ( aExp < 0x3FFF ) { if (aExp || aSig0) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } @@ -6380,7 +6381,7 @@ int32_t float128_to_int32_round_to_zero(float128 a, f= loat_status *status) return aSign ? INT32_MIN : INT32_MAX; } if ( ( aSig0<float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; =20 @@ -6458,7 +6459,7 @@ int64_t float128_to_int64_round_to_zero(float128 a, f= loat_status *status) if ( ( a.high =3D=3D UINT64_C(0xC03E000000000000) ) && ( aSig1 < UINT64_C(0x0002000000000000) ) ) { if (aSig1) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } } else { @@ -6471,20 +6472,20 @@ int64_t float128_to_int64_round_to_zero(float128 a,= float_status *status) } z =3D ( aSig0<>( ( - shiftCount ) & 63 ) ); if ( (uint64_t) ( aSig1<float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } } else { if ( aExp < 0x3FFF ) { if ( aExp | aSig0 | aSig1 ) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } z =3D aSig0>>( - shiftCount ); if ( aSig1 || ( shiftCount && (uint64_t) ( aSig0<<( shiftCount & 63 ) ) = ) ) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } } if ( aSign ) z =3D - z; @@ -6793,7 +6794,7 @@ float128 float128_round_to_int(float128 a, float_stat= us *status) else { if ( aExp < 0x3FFF ) { if ( ( ( (uint64_t) ( a.high<<1 ) ) | a.low ) =3D=3D 0 ) retur= n a; - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); aSign =3D extractFloat128Sign( a ); switch (status->float_rounding_mode) { case float_round_nearest_even: @@ -6867,7 +6868,7 @@ float128 float128_round_to_int(float128 a, float_stat= us *status) z.high &=3D ~ roundBitsMask; } if ( ( z.low !=3D a.low ) || ( z.high !=3D a.high ) ) { - status->float_exception_flags |=3D float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; =20 --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/72] softfloat: Tidy a * b + inf return Date: Fri, 7 May 2021 18:46:59 -0700 Message-Id: <20210508014802.892561-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) No reason to set values in 'a', when we already have float_class_inf in 'c', and can flip that sign. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- fpu/softfloat.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 93fe785809..ee4b5073b6 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1384,9 +1384,8 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, float_raise(float_flag_invalid, s); return parts_default_nan(s); } else { - a.cls =3D float_class_inf; - a.sign =3D c.sign ^ sign_flip; - return a; + c.sign ^=3D sign_flip; + return c; } } =20 --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Fri, 07 May 2021 18:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/72] softfloat: Add float_cmask and constants Date: Fri, 7 May 2021 18:47:00 -0700 Message-Id: <20210508014802.892561-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Testing more than one class at a time is better done with masks. This reduces the static branch count. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- fpu/softfloat.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ee4b5073b6..64edb23793 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -469,6 +469,20 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; =20 +#define float_cmask(bit) (1u << (bit)) + +enum { + float_cmask_zero =3D float_cmask(float_class_zero), + float_cmask_normal =3D float_cmask(float_class_normal), + float_cmask_inf =3D float_cmask(float_class_inf), + float_cmask_qnan =3D float_cmask(float_class_qnan), + float_cmask_snan =3D float_cmask(float_class_snan), + + float_cmask_infzero =3D float_cmask_zero | float_cmask_inf, + float_cmask_anynan =3D float_cmask_qnan | float_cmask_snan, +}; + + /* Simple helpers for checking if, or what kind of, NaN we have */ static inline __attribute__((unused)) bool is_nan(FloatClass c) { @@ -1338,26 +1352,28 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bflo= at16 b, float_status *status) static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, int flags, float_status *s) { - bool inf_zero =3D ((1 << a.cls) | (1 << b.cls)) =3D=3D - ((1 << float_class_inf) | (1 << float_class_zero)); - bool p_sign; + bool inf_zero, p_sign; bool sign_flip =3D flags & float_muladd_negate_result; FloatClass p_class; uint64_t hi, lo; int p_exp; + int ab_mask, abc_mask; + + ab_mask =3D float_cmask(a.cls) | float_cmask(b.cls); + abc_mask =3D float_cmask(c.cls) | ab_mask; + inf_zero =3D ab_mask =3D=3D float_cmask_infzero; =20 /* It is implementation-defined whether the cases of (0,inf,qnan) * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN * they return if they do), so we have to hand this information * off to the target-specific pick-a-NaN routine. */ - if (is_nan(a.cls) || is_nan(b.cls) || is_nan(c.cls)) { + if (unlikely(abc_mask & float_cmask_anynan)) { return pick_nan_muladd(a, b, c, inf_zero, s); } =20 if (inf_zero) { float_raise(float_flag_invalid, s); - s->float_exception_flags |=3D float_flag_invalid; return parts_default_nan(s); } =20 @@ -1371,9 +1387,9 @@ static FloatParts muladd_floats(FloatParts a, FloatPa= rts b, FloatParts c, p_sign ^=3D 1; } =20 - if (a.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_inf) { + if (ab_mask & float_cmask_inf) { p_class =3D float_class_inf; - } else if (a.cls =3D=3D float_class_zero || b.cls =3D=3D float_class_z= ero) { + } else if (ab_mask & float_cmask_zero) { p_class =3D float_class_zero; } else { p_class =3D float_class_normal; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439197; cv=none; d=zohomail.com; s=zohoarc; b=ZQ4AuW7DkkKCklc6mRZaX6+WEsYRbnIm5kUcPbUQ6yg/AgSs/CnksFpGOtI92LyBOW0hgf9AFEoWtBc/ebaRFJFjaEHuMimdbYjEzygjOWDeLoRsbJ2V5uYH32D8J6vaxCRxaZHeeSjno61B2cnBZHIex3FqXEQHrhtz5WQyego= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620439197; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand --- fpu/softfloat.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 64edb23793..b694e38522 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1931,13 +1931,7 @@ static FloatParts float_to_float(FloatParts a, const= FloatFmt *dstf, break; } } else if (is_nan(a.cls)) { - if (is_snan(a.cls)) { - float_raise(float_flag_invalid, s); - a =3D parts_silence_nan(a, s); - } - if (s->default_nan_mode) { - return parts_default_nan(s); - } + return return_nan(a, s); } return a; } --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439433; cv=none; d=zohomail.com; s=zohoarc; b=JQYoREYREXDzLIcI/YdWa8L8OBhOtj370sNwunSRAGNqKdXarF9Y+/XwC1Pyogrls8JrfLywINrO/xnj4vEapgvzNj1cLwIKnjhA3WTxAE9Wwwjz57q/jrOsOQboNITd8tfv7gLrCZKJCChFvgmYW1/gsJrgfsraASTfeSLoeGw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620439433; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Do not call parts_silence_nan when default_nan_mode is in effect. This will avoid an assert in a later patch. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand --- fpu/softfloat.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b694e38522..6589f00b23 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -892,21 +892,16 @@ static float64 float64_round_pack_canonical(FloatPart= s p, float_status *s) =20 static FloatParts return_nan(FloatParts a, float_status *s) { - switch (a.cls) { - case float_class_snan: + g_assert(is_nan(a.cls)); + if (is_snan(a.cls)) { float_raise(float_flag_invalid, s); - a =3D parts_silence_nan(a, s); - /* fall through */ - case float_class_qnan: - if (s->default_nan_mode) { - return parts_default_nan(s); + if (!s->default_nan_mode) { + return parts_silence_nan(a, s); } - break; - - default: - g_assert_not_reached(); + } else if (!s->default_nan_mode) { + return a; } - return a; + return parts_default_nan(s); } =20 static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MiCAsnwsyr5jz7kk+vBhCEvkm3DwoUGr8DX9RFGFP2o=; b=oHsDHD4SbrDPc8JMf61MZoFfL0Nyp+Z6PVZH3SgaoVPip7/47kTfA4f7ggyd8ZDolE Nz9f5/92WHR2VL5VGZLdLxplxbwxqCNG12VQtJ2ZasD9zXTv7TUzXI1si64GRscN1CU6 QMzoxWDwmCOtXg0/UGyEGdk3BO/pakQbZ360QVTXUBITxgqe+0CuXUVwCB7Dnv2690LO 0/PByqoODEDhrpGZxQqzCQbYPOj/aD/p7wD43wTcvuRiX9IQ9e0Xb7UItzPTURWisSjJ 4kRPr42B9zFF1kK7aF7FJh4jvsc40KDFJv49flEVdlwJI1KgAzHXgXjH/I0C8zLeIrLl Zq8g== X-Gm-Message-State: AOAM530HTz7OYsAa4CT+4ggyzkpgQ/DF/eetmAvP0YeoT8ujrqXtbHoN coqQSS+/C1epnOU9KJcECWqRohADkHbJ2g== X-Google-Smtp-Source: ABdhPJwNbEjHPmYyqqfXf1i7xm3Lp0cr+GzZFUVvjOyoVJnc9HTmuFrbVd17QYl0n38igeEbkJnOCw== X-Received: by 2002:a63:d710:: with SMTP id d16mr13190101pgg.214.1620438492139; Fri, 07 May 2021 18:48:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/72] target/mips: Set set_default_nan_mode with set_snan_bit_is_one Date: Fri, 7 May 2021 18:47:03 -0700 Message-Id: <20210508014802.892561-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This behavior is currently hard-coded in parts_silence_nan, but setting this bit properly will allow this to be cleaned up. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand --- target/mips/fpu_helper.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 1c2d6d35a7..ad1116e8c1 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -27,8 +27,14 @@ static inline void restore_flush_mode(CPUMIPSState *env) =20 static inline void restore_snan_bit_mode(CPUMIPSState *env) { - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) =3D= =3D 0, - &env->active_fpu.fp_status); + bool nan2008 =3D env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + + /* + * With nan2008, SNaNs are silenced in the usual way. + * Before that, SNaNs are not silenced; default nans are produced. + */ + set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); + set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); } =20 static inline void restore_fp_status(CPUMIPSState *env) --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Require default_nan_mode to be set instead. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand --- fpu/softfloat-specialize.c.inc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 487b29155c..5988830c16 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -180,16 +180,15 @@ static FloatParts parts_default_nan(float_status *sta= tus) static FloatParts parts_silence_nan(FloatParts a, float_status *status) { g_assert(!no_signaling_nans(status)); -#if defined(TARGET_HPPA) - a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); - a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); -#else + g_assert(!status->default_nan_mode); + + /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ if (snan_bit_is_one(status)) { - return parts_default_nan(status); + a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); } else { a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); } -#endif a.cls =3D float_class_qnan; return a; } --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439606; cv=none; d=zohomail.com; s=zohoarc; b=MduaJuIrnMfpWXrxT0JiAu5zS/GKF95rJNBPt2Sw9zJs9gLrECQgNRNO7AFx1Z7AFsNs6E8buJuALIftILsB9QJtYfsgC/XikFSvyfPMxi0hxoU7sJD+0lComcYR9ObxFP6EwJEBuxqoy5SpAfrVT9dr4NyykJ9SVg7EAI1+sVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620439606; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CTft5gBrUD6MnXZkZyjYyUchTRH6b2xyA6TvzbAPqzc=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- fpu/softfloat.c | 362 ++++++++++++++++----------------- fpu/softfloat-specialize.c.inc | 6 +- 2 files changed, 184 insertions(+), 184 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6589f00b23..27b51659c9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -515,7 +515,7 @@ typedef struct { int32_t exp; FloatClass cls; bool sign; -} FloatParts; +} FloatParts64; =20 #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) @@ -580,11 +580,11 @@ static const FloatFmt float64_params =3D { }; =20 /* Unpack a float to parts, but do not canonicalize. */ -static inline FloatParts unpack_raw(FloatFmt fmt, uint64_t raw) +static inline FloatParts64 unpack_raw(FloatFmt fmt, uint64_t raw) { const int sign_pos =3D fmt.frac_size + fmt.exp_size; =20 - return (FloatParts) { + return (FloatParts64) { .cls =3D float_class_unclassified, .sign =3D extract64(raw, sign_pos, 1), .exp =3D extract64(raw, fmt.frac_size, fmt.exp_size), @@ -592,50 +592,50 @@ static inline FloatParts unpack_raw(FloatFmt fmt, uin= t64_t raw) }; } =20 -static inline FloatParts float16_unpack_raw(float16 f) +static inline FloatParts64 float16_unpack_raw(float16 f) { return unpack_raw(float16_params, f); } =20 -static inline FloatParts bfloat16_unpack_raw(bfloat16 f) +static inline FloatParts64 bfloat16_unpack_raw(bfloat16 f) { return unpack_raw(bfloat16_params, f); } =20 -static inline FloatParts float32_unpack_raw(float32 f) +static inline FloatParts64 float32_unpack_raw(float32 f) { return unpack_raw(float32_params, f); } =20 -static inline FloatParts float64_unpack_raw(float64 f) +static inline FloatParts64 float64_unpack_raw(float64 f) { return unpack_raw(float64_params, f); } =20 /* Pack a float from parts, but do not canonicalize. */ -static inline uint64_t pack_raw(FloatFmt fmt, FloatParts p) +static inline uint64_t pack_raw(FloatFmt fmt, FloatParts64 p) { const int sign_pos =3D fmt.frac_size + fmt.exp_size; uint64_t ret =3D deposit64(p.frac, fmt.frac_size, fmt.exp_size, p.exp); return deposit64(ret, sign_pos, 1, p.sign); } =20 -static inline float16 float16_pack_raw(FloatParts p) +static inline float16 float16_pack_raw(FloatParts64 p) { return make_float16(pack_raw(float16_params, p)); } =20 -static inline bfloat16 bfloat16_pack_raw(FloatParts p) +static inline bfloat16 bfloat16_pack_raw(FloatParts64 p) { return pack_raw(bfloat16_params, p); } =20 -static inline float32 float32_pack_raw(FloatParts p) +static inline float32 float32_pack_raw(FloatParts64 p) { return make_float32(pack_raw(float32_params, p)); } =20 -static inline float64 float64_pack_raw(FloatParts p) +static inline float64 float64_pack_raw(FloatParts64 p) { return make_float64(pack_raw(float64_params, p)); } @@ -651,7 +651,7 @@ static inline float64 float64_pack_raw(FloatParts p) #include "softfloat-specialize.c.inc" =20 /* Canonicalize EXP and FRAC, setting CLS. */ -static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, +static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *par= m, float_status *status) { if (part.exp =3D=3D parm->exp_max && !parm->arm_althp) { @@ -689,7 +689,7 @@ static FloatParts sf_canonicalize(FloatParts part, cons= t FloatFmt *parm, * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. */ =20 -static FloatParts round_canonical(FloatParts p, float_status *s, +static FloatParts64 round_canonical(FloatParts64 p, float_status *s, const FloatFmt *parm) { const uint64_t frac_lsb =3D parm->frac_lsb; @@ -838,59 +838,59 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, } =20 /* Explicit FloatFmt version */ -static FloatParts float16a_unpack_canonical(float16 f, float_status *s, +static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, const FloatFmt *params) { return sf_canonicalize(float16_unpack_raw(f), params, s); } =20 -static FloatParts float16_unpack_canonical(float16 f, float_status *s) +static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) { return float16a_unpack_canonical(f, s, &float16_params); } =20 -static FloatParts bfloat16_unpack_canonical(bfloat16 f, float_status *s) +static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) { return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); } =20 -static float16 float16a_round_pack_canonical(FloatParts p, float_status *s, +static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, const FloatFmt *params) { return float16_pack_raw(round_canonical(p, s, params)); } =20 -static float16 float16_round_pack_canonical(FloatParts p, float_status *s) +static float16 float16_round_pack_canonical(FloatParts64 p, float_status *= s) { return float16a_round_pack_canonical(p, s, &float16_params); } =20 -static bfloat16 bfloat16_round_pack_canonical(FloatParts p, float_status *= s) +static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status= *s) { return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); } =20 -static FloatParts float32_unpack_canonical(float32 f, float_status *s) +static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) { return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); } =20 -static float32 float32_round_pack_canonical(FloatParts p, float_status *s) +static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) { return float32_pack_raw(round_canonical(p, s, &float32_params)); } =20 -static FloatParts float64_unpack_canonical(float64 f, float_status *s) +static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) { return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); } =20 -static float64 float64_round_pack_canonical(FloatParts p, float_status *s) +static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) { return float64_pack_raw(round_canonical(p, s, &float64_params)); } =20 -static FloatParts return_nan(FloatParts a, float_status *s) +static FloatParts64 return_nan(FloatParts64 a, float_status *s) { g_assert(is_nan(a.cls)); if (is_snan(a.cls)) { @@ -904,7 +904,7 @@ static FloatParts return_nan(FloatParts a, float_status= *s) return parts_default_nan(s); } =20 -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status = *s) { if (is_snan(a.cls) || is_snan(b.cls)) { float_raise(float_flag_invalid, s); @@ -925,7 +925,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, = float_status *s) return a; } =20 -static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, +static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatP= arts64 c, bool inf_zero, float_status *s) { int which; @@ -971,7 +971,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, * Arithmetic. */ =20 -static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, +static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool sub= tract, float_status *s) { bool a_sign =3D a.sign; @@ -1062,18 +1062,18 @@ static FloatParts addsub_floats(FloatParts a, Float= Parts b, bool subtract, =20 float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *statu= s) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pb =3D float16_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, false, status); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pb =3D float16_unpack_canonical(b, status); + FloatParts64 pr =3D addsub_floats(pa, pb, false, status); =20 return float16_round_pack_canonical(pr, status); } =20 float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *statu= s) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pb =3D float16_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, true, status); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pb =3D float16_unpack_canonical(b, status); + FloatParts64 pr =3D addsub_floats(pa, pb, true, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1081,9 +1081,9 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 b= , float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pb =3D float32_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, subtract, status); + FloatParts64 pa =3D float32_unpack_canonical(a, status); + FloatParts64 pb =3D float32_unpack_canonical(b, status); + FloatParts64 pr =3D addsub_floats(pa, pb, subtract, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1101,9 +1101,9 @@ static inline float32 soft_f32_sub(float32 a, float32= b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pb =3D float64_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, subtract, status); + FloatParts64 pa =3D float64_unpack_canonical(a, status); + FloatParts64 pb =3D float64_unpack_canonical(b, status); + FloatParts64 pr =3D addsub_floats(pa, pb, subtract, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1199,18 +1199,18 @@ float64_sub(float64 a, float64 b, float_status *s) */ bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *s= tatus) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pb =3D bfloat16_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, false, status); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); + FloatParts64 pr =3D addsub_floats(pa, pb, false, status); =20 return bfloat16_round_pack_canonical(pr, status); } =20 bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *s= tatus) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pb =3D bfloat16_unpack_canonical(b, status); - FloatParts pr =3D addsub_floats(pa, pb, true, status); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); + FloatParts64 pr =3D addsub_floats(pa, pb, true, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1221,7 +1221,7 @@ bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat= 16 b, float_status *status) * for Binary Floating-Point Arithmetic. */ =20 -static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) +static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_statu= s *s) { bool sign =3D a.sign ^ b.sign; =20 @@ -1267,9 +1267,9 @@ static FloatParts mul_floats(FloatParts a, FloatParts= b, float_status *s) =20 float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *statu= s) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pb =3D float16_unpack_canonical(b, status); - FloatParts pr =3D mul_floats(pa, pb, status); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pb =3D float16_unpack_canonical(b, status); + FloatParts64 pr =3D mul_floats(pa, pb, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1277,9 +1277,9 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b= , float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_mul(float32 a, float32 b, float_status *status) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pb =3D float32_unpack_canonical(b, status); - FloatParts pr =3D mul_floats(pa, pb, status); + FloatParts64 pa =3D float32_unpack_canonical(a, status); + FloatParts64 pb =3D float32_unpack_canonical(b, status); + FloatParts64 pr =3D mul_floats(pa, pb, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1287,9 +1287,9 @@ soft_f32_mul(float32 a, float32 b, float_status *stat= us) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_mul(float64 a, float64 b, float_status *status) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pb =3D float64_unpack_canonical(b, status); - FloatParts pr =3D mul_floats(pa, pb, status); + FloatParts64 pa =3D float64_unpack_canonical(a, status); + FloatParts64 pb =3D float64_unpack_canonical(b, status); + FloatParts64 pr =3D mul_floats(pa, pb, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1325,9 +1325,9 @@ float64_mul(float64 a, float64 b, float_status *s) =20 bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *s= tatus) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pb =3D bfloat16_unpack_canonical(b, status); - FloatParts pr =3D mul_floats(pa, pb, status); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); + FloatParts64 pr =3D mul_floats(pa, pb, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1344,7 +1344,7 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat= 16 b, float_status *status) * NaNs.) */ =20 -static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, +static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatPar= ts64 c, int flags, float_status *s) { bool inf_zero, p_sign; @@ -1520,10 +1520,10 @@ static FloatParts muladd_floats(FloatParts a, Float= Parts b, FloatParts c, float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, int flags, float_status *s= tatus) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pb =3D float16_unpack_canonical(b, status); - FloatParts pc =3D float16_unpack_canonical(c, status); - FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pb =3D float16_unpack_canonical(b, status); + FloatParts64 pc =3D float16_unpack_canonical(c, status); + FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1532,10 +1532,10 @@ static float32 QEMU_SOFTFLOAT_ATTR soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float_status *status) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pb =3D float32_unpack_canonical(b, status); - FloatParts pc =3D float32_unpack_canonical(c, status); - FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa =3D float32_unpack_canonical(a, status); + FloatParts64 pb =3D float32_unpack_canonical(b, status); + FloatParts64 pc =3D float32_unpack_canonical(c, status); + FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1544,10 +1544,10 @@ static float64 QEMU_SOFTFLOAT_ATTR soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float_status *status) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pb =3D float64_unpack_canonical(b, status); - FloatParts pc =3D float64_unpack_canonical(c, status); - FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa =3D float64_unpack_canonical(a, status); + FloatParts64 pb =3D float64_unpack_canonical(b, status); + FloatParts64 pc =3D float64_unpack_canonical(c, status); + FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1705,10 +1705,10 @@ float64_muladd(float64 xa, float64 xb, float64 xc, = int flags, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pb =3D bfloat16_unpack_canonical(b, status); - FloatParts pc =3D bfloat16_unpack_canonical(c, status); - FloatParts pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); + FloatParts64 pc =3D bfloat16_unpack_canonical(c, status); + FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1719,7 +1719,7 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfl= oat16 b, bfloat16 c, * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ =20 -static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) +static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_statu= s *s) { bool sign =3D a.sign ^ b.sign; =20 @@ -1786,9 +1786,9 @@ static FloatParts div_floats(FloatParts a, FloatParts= b, float_status *s) =20 float16 float16_div(float16 a, float16 b, float_status *status) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pb =3D float16_unpack_canonical(b, status); - FloatParts pr =3D div_floats(pa, pb, status); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pb =3D float16_unpack_canonical(b, status); + FloatParts64 pr =3D div_floats(pa, pb, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1796,9 +1796,9 @@ float16 float16_div(float16 a, float16 b, float_statu= s *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_div(float32 a, float32 b, float_status *status) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pb =3D float32_unpack_canonical(b, status); - FloatParts pr =3D div_floats(pa, pb, status); + FloatParts64 pa =3D float32_unpack_canonical(a, status); + FloatParts64 pb =3D float32_unpack_canonical(b, status); + FloatParts64 pr =3D div_floats(pa, pb, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1806,9 +1806,9 @@ soft_f32_div(float32 a, float32 b, float_status *stat= us) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_div(float64 a, float64 b, float_status *status) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pb =3D float64_unpack_canonical(b, status); - FloatParts pr =3D div_floats(pa, pb, status); + FloatParts64 pa =3D float64_unpack_canonical(a, status); + FloatParts64 pb =3D float64_unpack_canonical(b, status); + FloatParts64 pr =3D div_floats(pa, pb, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1878,9 +1878,9 @@ float64_div(float64 a, float64 b, float_status *s) =20 bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pb =3D bfloat16_unpack_canonical(b, status); - FloatParts pr =3D div_floats(pa, pb, status); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); + FloatParts64 pr =3D div_floats(pa, pb, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1896,7 +1896,7 @@ bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_s= tatus *status) * invalid exceptions and handling the conversion on NaNs. */ =20 -static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, +static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, float_status *s) { if (dstf->arm_althp) { @@ -1934,32 +1934,32 @@ static FloatParts float_to_float(FloatParts a, cons= t FloatFmt *dstf, float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts p =3D float16a_unpack_canonical(a, s, fmt16); - FloatParts pr =3D float_to_float(p, &float32_params, s); + FloatParts64 p =3D float16a_unpack_canonical(a, s, fmt16); + FloatParts64 pr =3D float_to_float(p, &float32_params, s); return float32_round_pack_canonical(pr, s); } =20 float64 float16_to_float64(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts p =3D float16a_unpack_canonical(a, s, fmt16); - FloatParts pr =3D float_to_float(p, &float64_params, s); + FloatParts64 p =3D float16a_unpack_canonical(a, s, fmt16); + FloatParts64 pr =3D float_to_float(p, &float64_params, s); return float64_round_pack_canonical(pr, s); } =20 float16 float32_to_float16(float32 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts p =3D float32_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, fmt16, s); + FloatParts64 p =3D float32_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_float32_to_float64(float32 a, float_status *s) { - FloatParts p =3D float32_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, &float64_params, s); + FloatParts64 p =3D float32_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, &float64_params, s); return float64_round_pack_canonical(pr, s); } =20 @@ -1982,43 +1982,43 @@ float64 float32_to_float64(float32 a, float_status = *s) float16 float64_to_float16(float64 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts p =3D float64_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, fmt16, s); + FloatParts64 p =3D float64_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } =20 float32 float64_to_float32(float64 a, float_status *s) { - FloatParts p =3D float64_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, &float32_params, s); + FloatParts64 p =3D float64_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, &float32_params, s); return float32_round_pack_canonical(pr, s); } =20 float32 bfloat16_to_float32(bfloat16 a, float_status *s) { - FloatParts p =3D bfloat16_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, &float32_params, s); + FloatParts64 p =3D bfloat16_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, &float32_params, s); return float32_round_pack_canonical(pr, s); } =20 float64 bfloat16_to_float64(bfloat16 a, float_status *s) { - FloatParts p =3D bfloat16_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, &float64_params, s); + FloatParts64 p =3D bfloat16_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, &float64_params, s); return float64_round_pack_canonical(pr, s); } =20 bfloat16 float32_to_bfloat16(float32 a, float_status *s) { - FloatParts p =3D float32_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, &bfloat16_params, s); + FloatParts64 p =3D float32_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } =20 bfloat16 float64_to_bfloat16(float64 a, float_status *s) { - FloatParts p =3D float64_unpack_canonical(a, s); - FloatParts pr =3D float_to_float(p, &bfloat16_params, s); + FloatParts64 p =3D float64_unpack_canonical(a, s); + FloatParts64 pr =3D float_to_float(p, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } =20 @@ -2029,7 +2029,7 @@ bfloat16 float64_to_bfloat16(float64 a, float_status = *s) * Arithmetic. */ =20 -static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode, +static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, int scale, float_status *s) { switch (a.cls) { @@ -2132,22 +2132,22 @@ static FloatParts round_to_int(FloatParts a, FloatR= oundMode rmode, =20 float16 float16_round_to_int(float16 a, float_status *s) { - FloatParts pa =3D float16_unpack_canonical(a, s); - FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa =3D float16_unpack_canonical(a, s); + FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return float16_round_pack_canonical(pr, s); } =20 float32 float32_round_to_int(float32 a, float_status *s) { - FloatParts pa =3D float32_unpack_canonical(a, s); - FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa =3D float32_unpack_canonical(a, s); + FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return float32_round_pack_canonical(pr, s); } =20 float64 float64_round_to_int(float64 a, float_status *s) { - FloatParts pa =3D float64_unpack_canonical(a, s); - FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa =3D float64_unpack_canonical(a, s); + FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return float64_round_pack_canonical(pr, s); } =20 @@ -2158,8 +2158,8 @@ float64 float64_round_to_int(float64 a, float_status = *s) =20 bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) { - FloatParts pa =3D bfloat16_unpack_canonical(a, s); - FloatParts pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, s); + FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return bfloat16_round_pack_canonical(pr, s); } =20 @@ -2174,13 +2174,13 @@ bfloat16 bfloat16_round_to_int(bfloat16 a, float_st= atus *s) * is returned. */ =20 -static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode, +static int64_t round_to_int_and_pack(FloatParts64 in, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) { uint64_t r; int orig_flags =3D get_float_exception_flags(s); - FloatParts p =3D round_to_int(in, rmode, scale, s); + FloatParts64 p =3D round_to_int(in, rmode, scale, s); =20 switch (p.cls) { case float_class_snan: @@ -2452,12 +2452,12 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a,= float_status *s) * flag. */ =20 -static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode, +static uint64_t round_to_uint_and_pack(FloatParts64 in, FloatRoundMode rmo= de, int scale, uint64_t max, float_status *s) { int orig_flags =3D get_float_exception_flags(s); - FloatParts p =3D round_to_int(in, rmode, scale, s); + FloatParts64 p =3D round_to_int(in, rmode, scale, s); uint64_t r; =20 switch (p.cls) { @@ -2726,9 +2726,9 @@ uint64_t bfloat16_to_uint64_round_to_zero(bfloat16 a,= float_status *s) * to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ =20 -static FloatParts int_to_float(int64_t a, int scale, float_status *status) +static FloatParts64 int_to_float(int64_t a, int scale, float_status *statu= s) { - FloatParts r =3D { .sign =3D false }; + FloatParts64 r =3D { .sign =3D false }; =20 if (a =3D=3D 0) { r.cls =3D float_class_zero; @@ -2753,7 +2753,7 @@ static FloatParts int_to_float(int64_t a, int scale, = float_status *status) =20 float16 int64_to_float16_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa =3D int_to_float(a, scale, status); + FloatParts64 pa =3D int_to_float(a, scale, status); return float16_round_pack_canonical(pa, status); } =20 @@ -2789,7 +2789,7 @@ float16 int8_to_float16(int8_t a, float_status *statu= s) =20 float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa =3D int_to_float(a, scale, status); + FloatParts64 pa =3D int_to_float(a, scale, status); return float32_round_pack_canonical(pa, status); } =20 @@ -2820,7 +2820,7 @@ float32 int16_to_float32(int16_t a, float_status *sta= tus) =20 float64 int64_to_float64_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa =3D int_to_float(a, scale, status); + FloatParts64 pa =3D int_to_float(a, scale, status); return float64_round_pack_canonical(pa, status); } =20 @@ -2856,7 +2856,7 @@ float64 int16_to_float64(int16_t a, float_status *sta= tus) =20 bfloat16 int64_to_bfloat16_scalbn(int64_t a, int scale, float_status *stat= us) { - FloatParts pa =3D int_to_float(a, scale, status); + FloatParts64 pa =3D int_to_float(a, scale, status); return bfloat16_round_pack_canonical(pa, status); } =20 @@ -2893,9 +2893,9 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status *s= tatus) * IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ =20 -static FloatParts uint_to_float(uint64_t a, int scale, float_status *statu= s) +static FloatParts64 uint_to_float(uint64_t a, int scale, float_status *sta= tus) { - FloatParts r =3D { .sign =3D false }; + FloatParts64 r =3D { .sign =3D false }; int shift; =20 if (a =3D=3D 0) { @@ -2913,7 +2913,7 @@ static FloatParts uint_to_float(uint64_t a, int scale= , float_status *status) =20 float16 uint64_to_float16_scalbn(uint64_t a, int scale, float_status *stat= us) { - FloatParts pa =3D uint_to_float(a, scale, status); + FloatParts64 pa =3D uint_to_float(a, scale, status); return float16_round_pack_canonical(pa, status); } =20 @@ -2949,7 +2949,7 @@ float16 uint8_to_float16(uint8_t a, float_status *sta= tus) =20 float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *stat= us) { - FloatParts pa =3D uint_to_float(a, scale, status); + FloatParts64 pa =3D uint_to_float(a, scale, status); return float32_round_pack_canonical(pa, status); } =20 @@ -2980,7 +2980,7 @@ float32 uint16_to_float32(uint16_t a, float_status *s= tatus) =20 float64 uint64_to_float64_scalbn(uint64_t a, int scale, float_status *stat= us) { - FloatParts pa =3D uint_to_float(a, scale, status); + FloatParts64 pa =3D uint_to_float(a, scale, status); return float64_round_pack_canonical(pa, status); } =20 @@ -3016,7 +3016,7 @@ float64 uint16_to_float64(uint16_t a, float_status *s= tatus) =20 bfloat16 uint64_to_bfloat16_scalbn(uint64_t a, int scale, float_status *st= atus) { - FloatParts pa =3D uint_to_float(a, scale, status); + FloatParts64 pa =3D uint_to_float(a, scale, status); return bfloat16_round_pack_canonical(pa, status); } =20 @@ -3061,7 +3061,7 @@ bfloat16 uint16_to_bfloat16(uint16_t a, float_status = *status) * minnummag() and maxnummag() functions correspond to minNumMag() * and minNumMag() from the IEEE-754 2008. */ -static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, +static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ism= in, bool ieee, bool ismag, float_status *s) { if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { @@ -3136,9 +3136,9 @@ static FloatParts minmax_floats(FloatParts a, FloatPa= rts b, bool ismin, float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ - FloatParts pa =3D float ## sz ## _unpack_canonical(a, s); \ - FloatParts pb =3D float ## sz ## _unpack_canonical(b, s); \ - FloatParts pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts64 pa =3D float ## sz ## _unpack_canonical(a, s); = \ + FloatParts64 pb =3D float ## sz ## _unpack_canonical(b, s); = \ + FloatParts64 pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); = \ \ return float ## sz ## _round_pack_canonical(pr, s); \ } @@ -3169,9 +3169,9 @@ MINMAX(64, maxnummag, false, true, true) #define BF16_MINMAX(name, ismin, isiee, ismag) \ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ { \ - FloatParts pa =3D bfloat16_unpack_canonical(a, s); \ - FloatParts pb =3D bfloat16_unpack_canonical(b, s); \ - FloatParts pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts64 pa =3D bfloat16_unpack_canonical(a, s); = \ + FloatParts64 pb =3D bfloat16_unpack_canonical(b, s); = \ + FloatParts64 pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); = \ \ return bfloat16_round_pack_canonical(pr, s); \ } @@ -3186,7 +3186,7 @@ BF16_MINMAX(maxnummag, false, true, true) #undef BF16_MINMAX =20 /* Floating point compare */ -static FloatRelation compare_floats(FloatParts a, FloatParts b, bool is_qu= iet, +static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool i= s_quiet, float_status *s) { if (is_nan(a.cls) || is_nan(b.cls)) { @@ -3247,8 +3247,8 @@ static FloatRelation compare_floats(FloatParts a, Flo= atParts b, bool is_quiet, static int attr \ name(float ## sz a, float ## sz b, bool is_quiet, float_status *s) \ { \ - FloatParts pa =3D float ## sz ## _unpack_canonical(a, s); \ - FloatParts pb =3D float ## sz ## _unpack_canonical(b, s); \ + FloatParts64 pa =3D float ## sz ## _unpack_canonical(a, s); = \ + FloatParts64 pb =3D float ## sz ## _unpack_canonical(b, s); = \ return compare_floats(pa, pb, is_quiet, s); \ } =20 @@ -3349,8 +3349,8 @@ FloatRelation float64_compare_quiet(float64 a, float6= 4 b, float_status *s) static FloatRelation QEMU_FLATTEN soft_bf16_compare(bfloat16 a, bfloat16 b, bool is_quiet, float_status *s) { - FloatParts pa =3D bfloat16_unpack_canonical(a, s); - FloatParts pb =3D bfloat16_unpack_canonical(b, s); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, s); + FloatParts64 pb =3D bfloat16_unpack_canonical(b, s); return compare_floats(pa, pb, is_quiet, s); } =20 @@ -3365,16 +3365,16 @@ FloatRelation bfloat16_compare_quiet(bfloat16 a, bf= loat16 b, float_status *s) } =20 /* Multiply A by 2 raised to the power N. */ -static FloatParts scalbn_decomposed(FloatParts a, int n, float_status *s) +static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status = *s) { if (unlikely(is_nan(a.cls))) { return return_nan(a, s); } if (a.cls =3D=3D float_class_normal) { - /* The largest float type (even though not supported by FloatParts) + /* The largest float type (even though not supported by FloatParts= 64) * is float128, which has a 15 bit exponent. Bounding N to 16 bits * still allows rounding to infinity, without allowing overflow - * within the int32_t that backs FloatParts.exp. + * within the int32_t that backs FloatParts64.exp. */ n =3D MIN(MAX(n, -0x10000), 0x10000); a.exp +=3D n; @@ -3384,29 +3384,29 @@ static FloatParts scalbn_decomposed(FloatParts a, i= nt n, float_status *s) =20 float16 float16_scalbn(float16 a, int n, float_status *status) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pr =3D scalbn_decomposed(pa, n, status); return float16_round_pack_canonical(pr, status); } =20 float32 float32_scalbn(float32 a, int n, float_status *status) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa =3D float32_unpack_canonical(a, status); + FloatParts64 pr =3D scalbn_decomposed(pa, n, status); return float32_round_pack_canonical(pr, status); } =20 float64 float64_scalbn(float64 a, int n, float_status *status) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa =3D float64_unpack_canonical(a, status); + FloatParts64 pr =3D scalbn_decomposed(pa, n, status); return float64_round_pack_canonical(pr, status); } =20 bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pr =3D scalbn_decomposed(pa, n, status); return bfloat16_round_pack_canonical(pr, status); } =20 @@ -3422,7 +3422,7 @@ bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_sta= tus *status) * especially for 64 bit floats. */ =20 -static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt= *p) +static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const Floa= tFmt *p) { uint64_t a_frac, r_frac, s_frac; int bit, last_bit; @@ -3482,24 +3482,24 @@ static FloatParts sqrt_float(FloatParts a, float_st= atus *s, const FloatFmt *p) =20 float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) { - FloatParts pa =3D float16_unpack_canonical(a, status); - FloatParts pr =3D sqrt_float(pa, status, &float16_params); + FloatParts64 pa =3D float16_unpack_canonical(a, status); + FloatParts64 pr =3D sqrt_float(pa, status, &float16_params); return float16_round_pack_canonical(pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR soft_f32_sqrt(float32 a, float_status *status) { - FloatParts pa =3D float32_unpack_canonical(a, status); - FloatParts pr =3D sqrt_float(pa, status, &float32_params); + FloatParts64 pa =3D float32_unpack_canonical(a, status); + FloatParts64 pr =3D sqrt_float(pa, status, &float32_params); return float32_round_pack_canonical(pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_f64_sqrt(float64 a, float_status *status) { - FloatParts pa =3D float64_unpack_canonical(a, status); - FloatParts pr =3D sqrt_float(pa, status, &float64_params); + FloatParts64 pa =3D float64_unpack_canonical(a, status); + FloatParts64 pr =3D sqrt_float(pa, status, &float64_params); return float64_round_pack_canonical(pr, status); } =20 @@ -3559,8 +3559,8 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_s= tatus *s) =20 bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { - FloatParts pa =3D bfloat16_unpack_canonical(a, status); - FloatParts pr =3D sqrt_float(pa, status, &bfloat16_params); + FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); + FloatParts64 pr =3D sqrt_float(pa, status, &bfloat16_params); return bfloat16_round_pack_canonical(pr, status); } =20 @@ -3570,28 +3570,28 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, flo= at_status *status) =20 float16 float16_default_nan(float_status *status) { - FloatParts p =3D parts_default_nan(status); + FloatParts64 p =3D parts_default_nan(status); p.frac >>=3D float16_params.frac_shift; return float16_pack_raw(p); } =20 float32 float32_default_nan(float_status *status) { - FloatParts p =3D parts_default_nan(status); + FloatParts64 p =3D parts_default_nan(status); p.frac >>=3D float32_params.frac_shift; return float32_pack_raw(p); } =20 float64 float64_default_nan(float_status *status) { - FloatParts p =3D parts_default_nan(status); + FloatParts64 p =3D parts_default_nan(status); p.frac >>=3D float64_params.frac_shift; return float64_pack_raw(p); } =20 float128 float128_default_nan(float_status *status) { - FloatParts p =3D parts_default_nan(status); + FloatParts64 p =3D parts_default_nan(status); float128 r; =20 /* Extrapolate from the choices made by parts_default_nan to fill @@ -3608,7 +3608,7 @@ float128 float128_default_nan(float_status *status) =20 bfloat16 bfloat16_default_nan(float_status *status) { - FloatParts p =3D parts_default_nan(status); + FloatParts64 p =3D parts_default_nan(status); p.frac >>=3D bfloat16_params.frac_shift; return bfloat16_pack_raw(p); } @@ -3619,7 +3619,7 @@ bfloat16 bfloat16_default_nan(float_status *status) =20 float16 float16_silence_nan(float16 a, float_status *status) { - FloatParts p =3D float16_unpack_raw(a); + FloatParts64 p =3D float16_unpack_raw(a); p.frac <<=3D float16_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float16_params.frac_shift; @@ -3628,7 +3628,7 @@ float16 float16_silence_nan(float16 a, float_status *= status) =20 float32 float32_silence_nan(float32 a, float_status *status) { - FloatParts p =3D float32_unpack_raw(a); + FloatParts64 p =3D float32_unpack_raw(a); p.frac <<=3D float32_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float32_params.frac_shift; @@ -3637,7 +3637,7 @@ float32 float32_silence_nan(float32 a, float_status *= status) =20 float64 float64_silence_nan(float64 a, float_status *status) { - FloatParts p =3D float64_unpack_raw(a); + FloatParts64 p =3D float64_unpack_raw(a); p.frac <<=3D float64_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float64_params.frac_shift; @@ -3646,7 +3646,7 @@ float64 float64_silence_nan(float64 a, float_status *= status) =20 bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) { - FloatParts p =3D bfloat16_unpack_raw(a); + FloatParts64 p =3D bfloat16_unpack_raw(a); p.frac <<=3D bfloat16_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D bfloat16_params.frac_shift; @@ -3658,7 +3658,7 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_statu= s *status) | input-denormal exception and return zero. Otherwise just return the valu= e. *-------------------------------------------------------------------------= ---*/ =20 -static bool parts_squash_denormal(FloatParts p, float_status *status) +static bool parts_squash_denormal(FloatParts64 p, float_status *status) { if (p.exp =3D=3D 0 && p.frac !=3D 0) { float_raise(float_flag_input_denormal, status); @@ -3671,7 +3671,7 @@ static bool parts_squash_denormal(FloatParts p, float= _status *status) float16 float16_squash_input_denormal(float16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p =3D float16_unpack_raw(a); + FloatParts64 p =3D float16_unpack_raw(a); if (parts_squash_denormal(p, status)) { return float16_set_sign(float16_zero, p.sign); } @@ -3682,7 +3682,7 @@ float16 float16_squash_input_denormal(float16 a, floa= t_status *status) float32 float32_squash_input_denormal(float32 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p =3D float32_unpack_raw(a); + FloatParts64 p =3D float32_unpack_raw(a); if (parts_squash_denormal(p, status)) { return float32_set_sign(float32_zero, p.sign); } @@ -3693,7 +3693,7 @@ float32 float32_squash_input_denormal(float32 a, floa= t_status *status) float64 float64_squash_input_denormal(float64 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p =3D float64_unpack_raw(a); + FloatParts64 p =3D float64_unpack_raw(a); if (parts_squash_denormal(p, status)) { return float64_set_sign(float64_zero, p.sign); } @@ -3704,7 +3704,7 @@ float64 float64_squash_input_denormal(float64 a, floa= t_status *status) bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p =3D bfloat16_unpack_raw(a); + FloatParts64 p =3D bfloat16_unpack_raw(a); if (parts_squash_denormal(p, status)) { return bfloat16_set_sign(bfloat16_zero, p.sign); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5988830c16..52fc76d800 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -129,7 +129,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_sta= tus *status) | The pattern for a default generated deconstructed floating-point NaN. *-------------------------------------------------------------------------= ---*/ =20 -static FloatParts parts_default_nan(float_status *status) +static FloatParts64 parts_default_nan(float_status *status) { bool sign =3D 0; uint64_t frac; @@ -164,7 +164,7 @@ static FloatParts parts_default_nan(float_status *statu= s) } #endif =20 - return (FloatParts) { + return (FloatParts64) { .cls =3D float_class_qnan, .sign =3D sign, .exp =3D INT_MAX, @@ -177,7 +177,7 @@ static FloatParts parts_default_nan(float_status *statu= s) | floating-point parts. *-------------------------------------------------------------------------= ---*/ =20 -static FloatParts parts_silence_nan(FloatParts a, float_status *status) +static FloatParts64 parts_silence_nan(FloatParts64 a, float_status *status) { g_assert(!no_signaling_nans(status)); g_assert(!status->default_nan_mode); --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Fri, 07 May 2021 18:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/72] softfloat: Move type-specific pack/unpack routines Date: Fri, 7 May 2021 18:47:06 -0700 Message-Id: <20210508014802.892561-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In preparation from moving sf_canonicalize. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- fpu/softfloat.c | 109 +++++++++++++++++++++++++----------------------- 1 file changed, 56 insertions(+), 53 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 27b51659c9..398a068b58 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -837,59 +837,6 @@ static FloatParts64 round_canonical(FloatParts64 p, fl= oat_status *s, return p; } =20 -/* Explicit FloatFmt version */ -static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, - const FloatFmt *params) -{ - return sf_canonicalize(float16_unpack_raw(f), params, s); -} - -static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) -{ - return float16a_unpack_canonical(f, s, &float16_params); -} - -static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) -{ - return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); -} - -static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, - const FloatFmt *params) -{ - return float16_pack_raw(round_canonical(p, s, params)); -} - -static float16 float16_round_pack_canonical(FloatParts64 p, float_status *= s) -{ - return float16a_round_pack_canonical(p, s, &float16_params); -} - -static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status= *s) -{ - return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); -} - -static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) -{ - return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); -} - -static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) -{ - return float32_pack_raw(round_canonical(p, s, &float32_params)); -} - -static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) -{ - return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); -} - -static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) -{ - return float64_pack_raw(round_canonical(p, s, &float64_params)); -} - static FloatParts64 return_nan(FloatParts64 a, float_status *s) { g_assert(is_nan(a.cls)); @@ -964,6 +911,62 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, Fl= oatParts64 b, FloatParts64 return a; } =20 +/* + * Pack/unpack routines with a specific FloatFmt. + */ + +static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, + const FloatFmt *params) +{ + return sf_canonicalize(float16_unpack_raw(f), params, s); +} + +static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) +{ + return float16a_unpack_canonical(f, s, &float16_params); +} + +static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) +{ + return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); +} + +static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, + const FloatFmt *params) +{ + return float16_pack_raw(round_canonical(p, s, params)); +} + +static float16 float16_round_pack_canonical(FloatParts64 p, float_status *= s) +{ + return float16a_round_pack_canonical(p, s, &float16_params); +} + +static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status= *s) +{ + return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); +} + +static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) +{ + return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); +} + +static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) +{ + return float32_pack_raw(round_canonical(p, s, &float32_params)); +} + +static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) +{ + return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); +} + +static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) +{ + return float64_pack_raw(round_canonical(p, s, &float64_params)); +} + /* * Returns the result of adding or subtracting the values of the * floating-point values `a' and `b'. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, rename to parts64_default_nan and define a macro for parts_default_nan using QEMU_GENERIC. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- fpu/softfloat.c | 47 +++++++++++++++++++++++----------- fpu/softfloat-specialize.c.inc | 4 +-- 2 files changed, 34 insertions(+), 17 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 398a068b58..c7f95961cf 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -650,6 +650,8 @@ static inline float64 float64_pack_raw(FloatParts64 p) *-------------------------------------------------------------------------= ---*/ #include "softfloat-specialize.c.inc" =20 +#define parts_default_nan parts64_default_nan + /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *par= m, float_status *status) @@ -848,7 +850,8 @@ static FloatParts64 return_nan(FloatParts64 a, float_st= atus *s) } else if (!s->default_nan_mode) { return a; } - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } =20 static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status = *s) @@ -858,7 +861,7 @@ static FloatParts64 pick_nan(FloatParts64 a, FloatParts= 64 b, float_status *s) } =20 if (s->default_nan_mode) { - return parts_default_nan(s); + parts_default_nan(&a, s); } else { if (pickNaN(a.cls, b.cls, a.frac > b.frac || @@ -900,7 +903,8 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, Flo= atParts64 b, FloatParts64 a =3D c; break; case 3: - return parts_default_nan(s); + parts_default_nan(&a, s); + break; default: g_assert_not_reached(); } @@ -1011,7 +1015,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, Flo= atParts64 b, bool subtract, if (a.cls =3D=3D float_class_inf) { if (b.cls =3D=3D float_class_inf) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); } return a; } @@ -1254,7 +1258,8 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatP= arts64 b, float_status *s) if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } /* Multiply by 0 or Inf */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -1372,7 +1377,8 @@ static FloatParts64 muladd_floats(FloatParts64 a, Flo= atParts64 b, FloatParts64 c =20 if (inf_zero) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } =20 if (flags & float_muladd_negate_c) { @@ -1396,11 +1402,11 @@ static FloatParts64 muladd_floats(FloatParts64 a, F= loatParts64 b, FloatParts64 c if (c.cls =3D=3D float_class_inf) { if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&c, s); } else { c.sign ^=3D sign_flip; - return c; } + return c; } =20 if (p_class =3D=3D float_class_inf) { @@ -1764,7 +1770,8 @@ static FloatParts64 div_floats(FloatParts64 a, FloatP= arts64 b, float_status *s) && (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } /* Inf / x or 0 / x */ if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { @@ -3438,7 +3445,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_= status *s, const FloatFmt * } if (a.sign) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } if (a.cls =3D=3D float_class_inf) { return a; /* sqrt(+inf) =3D +inf */ @@ -3573,30 +3581,37 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, flo= at_status *status) =20 float16 float16_default_nan(float_status *status) { - FloatParts64 p =3D parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>=3D float16_params.frac_shift; return float16_pack_raw(p); } =20 float32 float32_default_nan(float_status *status) { - FloatParts64 p =3D parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>=3D float32_params.frac_shift; return float32_pack_raw(p); } =20 float64 float64_default_nan(float_status *status) { - FloatParts64 p =3D parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>=3D float64_params.frac_shift; return float64_pack_raw(p); } =20 float128 float128_default_nan(float_status *status) { - FloatParts64 p =3D parts_default_nan(status); + FloatParts64 p; float128 r; =20 + parts_default_nan(&p, status); /* Extrapolate from the choices made by parts_default_nan to fill * in the quad-floating format. If the low bit is set, assume we * want to set all non-snan bits. @@ -3611,7 +3626,9 @@ float128 float128_default_nan(float_status *status) =20 bfloat16 bfloat16_default_nan(float_status *status) { - FloatParts64 p =3D parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>=3D bfloat16_params.frac_shift; return bfloat16_pack_raw(p); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 52fc76d800..085ddea62b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -129,7 +129,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_sta= tus *status) | The pattern for a default generated deconstructed floating-point NaN. *-------------------------------------------------------------------------= ---*/ =20 -static FloatParts64 parts_default_nan(float_status *status) +static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign =3D 0; uint64_t frac; @@ -164,7 +164,7 @@ static FloatParts64 parts_default_nan(float_status *sta= tus) } #endif =20 - return (FloatParts64) { + *p =3D (FloatParts64) { .cls =3D float_class_qnan, .sign =3D sign, .exp =3D INT_MAX, --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, rename to unpack_raw64. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- fpu/softfloat.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c7f95961cf..5ff9368012 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,36 +580,45 @@ static const FloatFmt float64_params =3D { }; =20 /* Unpack a float to parts, but do not canonicalize. */ -static inline FloatParts64 unpack_raw(FloatFmt fmt, uint64_t raw) +static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t ra= w) { - const int sign_pos =3D fmt.frac_size + fmt.exp_size; + const int f_size =3D fmt->frac_size; + const int e_size =3D fmt->exp_size; =20 - return (FloatParts64) { + *r =3D (FloatParts64) { .cls =3D float_class_unclassified, - .sign =3D extract64(raw, sign_pos, 1), - .exp =3D extract64(raw, fmt.frac_size, fmt.exp_size), - .frac =3D extract64(raw, 0, fmt.frac_size), + .sign =3D extract64(raw, f_size + e_size, 1), + .exp =3D extract64(raw, f_size, e_size), + .frac =3D extract64(raw, 0, f_size) }; } =20 static inline FloatParts64 float16_unpack_raw(float16 f) { - return unpack_raw(float16_params, f); + FloatParts64 p; + unpack_raw64(&p, &float16_params, f); + return p; } =20 static inline FloatParts64 bfloat16_unpack_raw(bfloat16 f) { - return unpack_raw(bfloat16_params, f); + FloatParts64 p; + unpack_raw64(&p, &bfloat16_params, f); + return p; } =20 static inline FloatParts64 float32_unpack_raw(float32 f) { - return unpack_raw(float32_params, f); + FloatParts64 p; + unpack_raw64(&p, &float32_params, f); + return p; } =20 static inline FloatParts64 float64_unpack_raw(float64 f) { - return unpack_raw(float64_params, f); + FloatParts64 p; + unpack_raw64(&p, &float64_params, f); + return p; } =20 /* Pack a float from parts, but do not canonicalize. */ --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:48:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/72] softfloat: Use pointers with ftype_unpack_raw Date: Fri, 7 May 2021 18:47:09 -0700 Message-Id: <20210508014802.892561-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 76 +++++++++++++++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 28 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5ff9368012..5a736a46cf 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -593,32 +593,24 @@ static void unpack_raw64(FloatParts64 *r, const Float= Fmt *fmt, uint64_t raw) }; } =20 -static inline FloatParts64 float16_unpack_raw(float16 f) +static inline void float16_unpack_raw(FloatParts64 *p, float16 f) { - FloatParts64 p; - unpack_raw64(&p, &float16_params, f); - return p; + unpack_raw64(p, &float16_params, f); } =20 -static inline FloatParts64 bfloat16_unpack_raw(bfloat16 f) +static inline void bfloat16_unpack_raw(FloatParts64 *p, bfloat16 f) { - FloatParts64 p; - unpack_raw64(&p, &bfloat16_params, f); - return p; + unpack_raw64(p, &bfloat16_params, f); } =20 -static inline FloatParts64 float32_unpack_raw(float32 f) +static inline void float32_unpack_raw(FloatParts64 *p, float32 f) { - FloatParts64 p; - unpack_raw64(&p, &float32_params, f); - return p; + unpack_raw64(p, &float32_params, f); } =20 -static inline FloatParts64 float64_unpack_raw(float64 f) +static inline void float64_unpack_raw(FloatParts64 *p, float64 f) { - FloatParts64 p; - unpack_raw64(&p, &float64_params, f); - return p; + unpack_raw64(p, &float64_params, f); } =20 /* Pack a float from parts, but do not canonicalize. */ @@ -931,7 +923,10 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, Fl= oatParts64 b, FloatParts64 static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, const FloatFmt *params) { - return sf_canonicalize(float16_unpack_raw(f), params, s); + FloatParts64 p; + + float16_unpack_raw(&p, f); + return sf_canonicalize(p, params, s); } =20 static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) @@ -941,7 +936,10 @@ static FloatParts64 float16_unpack_canonical(float16 f= , float_status *s) =20 static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) { - return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); + FloatParts64 p; + + bfloat16_unpack_raw(&p, f); + return sf_canonicalize(p, &bfloat16_params, s); } =20 static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, @@ -962,7 +960,10 @@ static bfloat16 bfloat16_round_pack_canonical(FloatPar= ts64 p, float_status *s) =20 static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) { - return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); + FloatParts64 p; + + float32_unpack_raw(&p, f); + return sf_canonicalize(p, &float32_params, s); } =20 static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) @@ -972,7 +973,10 @@ static float32 float32_round_pack_canonical(FloatParts= 64 p, float_status *s) =20 static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) { - return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); + FloatParts64 p; + + float64_unpack_raw(&p, f); + return sf_canonicalize(p, &float64_params, s); } =20 static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) @@ -3648,7 +3652,9 @@ bfloat16 bfloat16_default_nan(float_status *status) =20 float16 float16_silence_nan(float16 a, float_status *status) { - FloatParts64 p =3D float16_unpack_raw(a); + FloatParts64 p; + + float16_unpack_raw(&p, a); p.frac <<=3D float16_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float16_params.frac_shift; @@ -3657,7 +3663,9 @@ float16 float16_silence_nan(float16 a, float_status *= status) =20 float32 float32_silence_nan(float32 a, float_status *status) { - FloatParts64 p =3D float32_unpack_raw(a); + FloatParts64 p; + + float32_unpack_raw(&p, a); p.frac <<=3D float32_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float32_params.frac_shift; @@ -3666,7 +3674,9 @@ float32 float32_silence_nan(float32 a, float_status *= status) =20 float64 float64_silence_nan(float64 a, float_status *status) { - FloatParts64 p =3D float64_unpack_raw(a); + FloatParts64 p; + + float64_unpack_raw(&p, a); p.frac <<=3D float64_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float64_params.frac_shift; @@ -3675,7 +3685,9 @@ float64 float64_silence_nan(float64 a, float_status *= status) =20 bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) { - FloatParts64 p =3D bfloat16_unpack_raw(a); + FloatParts64 p; + + bfloat16_unpack_raw(&p, a); p.frac <<=3D bfloat16_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D bfloat16_params.frac_shift; @@ -3700,7 +3712,9 @@ static bool parts_squash_denormal(FloatParts64 p, flo= at_status *status) float16 float16_squash_input_denormal(float16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p =3D float16_unpack_raw(a); + FloatParts64 p; + + float16_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return float16_set_sign(float16_zero, p.sign); } @@ -3711,7 +3725,9 @@ float16 float16_squash_input_denormal(float16 a, floa= t_status *status) float32 float32_squash_input_denormal(float32 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p =3D float32_unpack_raw(a); + FloatParts64 p; + + float32_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return float32_set_sign(float32_zero, p.sign); } @@ -3722,7 +3738,9 @@ float32 float32_squash_input_denormal(float32 a, floa= t_status *status) float64 float64_squash_input_denormal(float64 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p =3D float64_unpack_raw(a); + FloatParts64 p; + + float64_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return float64_set_sign(float64_zero, p.sign); } @@ -3733,7 +3751,9 @@ float64 float64_squash_input_denormal(float64 a, floa= t_status *status) bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p =3D bfloat16_unpack_raw(a); + FloatParts64 p; + + bfloat16_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return bfloat16_set_sign(bfloat16_zero, p.sign); } --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439778; cv=none; d=zohomail.com; s=zohoarc; b=J7ISMOM01bIhQQfK1mcMUhtWhzvsGrIW59FgTXBI0cH5E3zJ/4IIO44RETswv1xGBnxJ+j+GqNu0aFh6J1ayhQzd7Sqa8ljPHdcllRiW+S93Icjn/rj8x9uV+MfTPy4HIUZ99fqB7aJRJ4TdmgRNahlXRfHVilQbUX2PrXJ5cew= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 20/72] softfloat: Use pointers with pack_raw Date: Fri, 7 May 2021 18:47:10 -0700 Message-Id: <20210508014802.892561-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, rename to pack_raw64. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5a736a46cf..b59b777bca 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -614,31 +614,36 @@ static inline void float64_unpack_raw(FloatParts64 *p= , float64 f) } =20 /* Pack a float from parts, but do not canonicalize. */ -static inline uint64_t pack_raw(FloatFmt fmt, FloatParts64 p) +static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt) { - const int sign_pos =3D fmt.frac_size + fmt.exp_size; - uint64_t ret =3D deposit64(p.frac, fmt.frac_size, fmt.exp_size, p.exp); - return deposit64(ret, sign_pos, 1, p.sign); + const int f_size =3D fmt->frac_size; + const int e_size =3D fmt->exp_size; + uint64_t ret; + + ret =3D (uint64_t)p->sign << (f_size + e_size); + ret =3D deposit64(ret, f_size, e_size, p->exp); + ret =3D deposit64(ret, 0, f_size, p->frac); + return ret; } =20 static inline float16 float16_pack_raw(FloatParts64 p) { - return make_float16(pack_raw(float16_params, p)); + return make_float16(pack_raw64(&p, &float16_params)); } =20 static inline bfloat16 bfloat16_pack_raw(FloatParts64 p) { - return pack_raw(bfloat16_params, p); + return pack_raw64(&p, &bfloat16_params); } =20 static inline float32 float32_pack_raw(FloatParts64 p) { - return make_float32(pack_raw(float32_params, p)); + return make_float32(pack_raw64(&p, &float32_params)); } =20 static inline float64 float64_pack_raw(FloatParts64 p) { - return make_float64(pack_raw(float64_params, p)); + return make_float64(pack_raw64(&p, &float64_params)); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/72] softfloat: Use pointers with ftype_pack_raw Date: Fri, 7 May 2021 18:47:11 -0700 Message-Id: <20210508014802.892561-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b59b777bca..e02cbafaf9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -626,24 +626,24 @@ static uint64_t pack_raw64(const FloatParts64 *p, con= st FloatFmt *fmt) return ret; } =20 -static inline float16 float16_pack_raw(FloatParts64 p) +static inline float16 float16_pack_raw(const FloatParts64 *p) { - return make_float16(pack_raw64(&p, &float16_params)); + return make_float16(pack_raw64(p, &float16_params)); } =20 -static inline bfloat16 bfloat16_pack_raw(FloatParts64 p) +static inline bfloat16 bfloat16_pack_raw(const FloatParts64 *p) { - return pack_raw64(&p, &bfloat16_params); + return pack_raw64(p, &bfloat16_params); } =20 -static inline float32 float32_pack_raw(FloatParts64 p) +static inline float32 float32_pack_raw(const FloatParts64 *p) { - return make_float32(pack_raw64(&p, &float32_params)); + return make_float32(pack_raw64(p, &float32_params)); } =20 -static inline float64 float64_pack_raw(FloatParts64 p) +static inline float64 float64_pack_raw(const FloatParts64 *p) { - return make_float64(pack_raw64(&p, &float64_params)); + return make_float64(pack_raw64(p, &float64_params)); } =20 /*------------------------------------------------------------------------= ---- @@ -950,7 +950,8 @@ static FloatParts64 bfloat16_unpack_canonical(bfloat16 = f, float_status *s) static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, const FloatFmt *params) { - return float16_pack_raw(round_canonical(p, s, params)); + p =3D round_canonical(p, s, params); + return float16_pack_raw(&p); } =20 static float16 float16_round_pack_canonical(FloatParts64 p, float_status *= s) @@ -960,7 +961,8 @@ static float16 float16_round_pack_canonical(FloatParts6= 4 p, float_status *s) =20 static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status= *s) { - return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); + p =3D round_canonical(p, s, &bfloat16_params); + return bfloat16_pack_raw(&p); } =20 static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) @@ -973,7 +975,8 @@ static FloatParts64 float32_unpack_canonical(float32 f,= float_status *s) =20 static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) { - return float32_pack_raw(round_canonical(p, s, &float32_params)); + p =3D round_canonical(p, s, &float32_params); + return float32_pack_raw(&p); } =20 static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) @@ -986,7 +989,8 @@ static FloatParts64 float64_unpack_canonical(float64 f,= float_status *s) =20 static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) { - return float64_pack_raw(round_canonical(p, s, &float64_params)); + p =3D round_canonical(p, s, &float64_params); + return float64_pack_raw(&p); } =20 /* @@ -3603,7 +3607,7 @@ float16 float16_default_nan(float_status *status) =20 parts_default_nan(&p, status); p.frac >>=3D float16_params.frac_shift; - return float16_pack_raw(p); + return float16_pack_raw(&p); } =20 float32 float32_default_nan(float_status *status) @@ -3612,7 +3616,7 @@ float32 float32_default_nan(float_status *status) =20 parts_default_nan(&p, status); p.frac >>=3D float32_params.frac_shift; - return float32_pack_raw(p); + return float32_pack_raw(&p); } =20 float64 float64_default_nan(float_status *status) @@ -3621,7 +3625,7 @@ float64 float64_default_nan(float_status *status) =20 parts_default_nan(&p, status); p.frac >>=3D float64_params.frac_shift; - return float64_pack_raw(p); + return float64_pack_raw(&p); } =20 float128 float128_default_nan(float_status *status) @@ -3648,7 +3652,7 @@ bfloat16 bfloat16_default_nan(float_status *status) =20 parts_default_nan(&p, status); p.frac >>=3D bfloat16_params.frac_shift; - return bfloat16_pack_raw(p); + return bfloat16_pack_raw(&p); } =20 /*------------------------------------------------------------------------= ---- @@ -3663,7 +3667,7 @@ float16 float16_silence_nan(float16 a, float_status *= status) p.frac <<=3D float16_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float16_params.frac_shift; - return float16_pack_raw(p); + return float16_pack_raw(&p); } =20 float32 float32_silence_nan(float32 a, float_status *status) @@ -3674,7 +3678,7 @@ float32 float32_silence_nan(float32 a, float_status *= status) p.frac <<=3D float32_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float32_params.frac_shift; - return float32_pack_raw(p); + return float32_pack_raw(&p); } =20 float64 float64_silence_nan(float64 a, float_status *status) @@ -3685,7 +3689,7 @@ float64 float64_silence_nan(float64 a, float_status *= status) p.frac <<=3D float64_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D float64_params.frac_shift; - return float64_pack_raw(p); + return float64_pack_raw(&p); } =20 bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) @@ -3696,7 +3700,7 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_statu= s *status) p.frac <<=3D bfloat16_params.frac_shift; p =3D parts_silence_nan(p, status); p.frac >>=3D bfloat16_params.frac_shift; - return bfloat16_pack_raw(p); + return bfloat16_pack_raw(&p); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439101; cv=none; d=zohomail.com; s=zohoarc; b=aH9ecCBz3SAocuZm5M+fCHiAoV28TRshZNNEkvp/zObYCZRj4vioKD7iw+meSlGdNjbRNxdkGe7RRWKxrdaCz4BucI8cgr5i4RL0XClD5CZYdScQDDIbh0sVcp/NBhZOImNvPhiKA8sKT1OAZgXITP22WBWQVrWUT9gWSq2ISxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620439101; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 509 ++++++++++++++++++++++++++++++------------------ 1 file changed, 320 insertions(+), 189 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e02cbafaf9..e53d4a138f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -925,26 +925,24 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, F= loatParts64 b, FloatParts64 * Pack/unpack routines with a specific FloatFmt. */ =20 -static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, - const FloatFmt *params) +static void float16a_unpack_canonical(FloatParts64 *p, float16 f, + float_status *s, const FloatFmt *par= ams) { - FloatParts64 p; - - float16_unpack_raw(&p, f); - return sf_canonicalize(p, params, s); + float16_unpack_raw(p, f); + *p =3D sf_canonicalize(*p, params, s); } =20 -static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) +static void float16_unpack_canonical(FloatParts64 *p, float16 f, + float_status *s) { - return float16a_unpack_canonical(f, s, &float16_params); + float16a_unpack_canonical(p, f, s, &float16_params); } =20 -static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) +static void bfloat16_unpack_canonical(FloatParts64 *p, bfloat16 f, + float_status *s) { - FloatParts64 p; - - bfloat16_unpack_raw(&p, f); - return sf_canonicalize(p, &bfloat16_params, s); + bfloat16_unpack_raw(p, f); + *p =3D sf_canonicalize(*p, &bfloat16_params, s); } =20 static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, @@ -965,12 +963,11 @@ static bfloat16 bfloat16_round_pack_canonical(FloatPa= rts64 p, float_status *s) return bfloat16_pack_raw(&p); } =20 -static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) +static void float32_unpack_canonical(FloatParts64 *p, float32 f, + float_status *s) { - FloatParts64 p; - - float32_unpack_raw(&p, f); - return sf_canonicalize(p, &float32_params, s); + float32_unpack_raw(p, f); + *p =3D sf_canonicalize(*p, &float32_params, s); } =20 static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) @@ -979,12 +976,11 @@ static float32 float32_round_pack_canonical(FloatPart= s64 p, float_status *s) return float32_pack_raw(&p); } =20 -static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) +static void float64_unpack_canonical(FloatParts64 *p, float64 f, + float_status *s) { - FloatParts64 p; - - float64_unpack_raw(&p, f); - return sf_canonicalize(p, &float64_params, s); + float64_unpack_raw(p, f); + *p =3D sf_canonicalize(*p, &float64_params, s); } =20 static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) @@ -1091,18 +1087,22 @@ static FloatParts64 addsub_floats(FloatParts64 a, F= loatParts64 b, bool subtract, =20 float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *statu= s) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pb =3D float16_unpack_canonical(b, status); - FloatParts64 pr =3D addsub_floats(pa, pb, false, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr =3D addsub_floats(pa, pb, false, status); =20 return float16_round_pack_canonical(pr, status); } =20 float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *statu= s) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pb =3D float16_unpack_canonical(b, status); - FloatParts64 pr =3D addsub_floats(pa, pb, true, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr =3D addsub_floats(pa, pb, true, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1110,9 +1110,11 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 = b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) { - FloatParts64 pa =3D float32_unpack_canonical(a, status); - FloatParts64 pb =3D float32_unpack_canonical(b, status); - FloatParts64 pr =3D addsub_floats(pa, pb, subtract, status); + FloatParts64 pa, pb, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr =3D addsub_floats(pa, pb, subtract, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1130,9 +1132,11 @@ static inline float32 soft_f32_sub(float32 a, float3= 2 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) { - FloatParts64 pa =3D float64_unpack_canonical(a, status); - FloatParts64 pb =3D float64_unpack_canonical(b, status); - FloatParts64 pr =3D addsub_floats(pa, pb, subtract, status); + FloatParts64 pa, pb, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr =3D addsub_floats(pa, pb, subtract, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1228,18 +1232,22 @@ float64_sub(float64 a, float64 b, float_status *s) */ bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *s= tatus) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); - FloatParts64 pr =3D addsub_floats(pa, pb, false, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr =3D addsub_floats(pa, pb, false, status); =20 return bfloat16_round_pack_canonical(pr, status); } =20 bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *s= tatus) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); - FloatParts64 pr =3D addsub_floats(pa, pb, true, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr =3D addsub_floats(pa, pb, true, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1297,9 +1305,11 @@ static FloatParts64 mul_floats(FloatParts64 a, Float= Parts64 b, float_status *s) =20 float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *statu= s) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pb =3D float16_unpack_canonical(b, status); - FloatParts64 pr =3D mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr =3D mul_floats(pa, pb, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1307,9 +1317,11 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 = b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_mul(float32 a, float32 b, float_status *status) { - FloatParts64 pa =3D float32_unpack_canonical(a, status); - FloatParts64 pb =3D float32_unpack_canonical(b, status); - FloatParts64 pr =3D mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr =3D mul_floats(pa, pb, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1317,9 +1329,11 @@ soft_f32_mul(float32 a, float32 b, float_status *sta= tus) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_mul(float64 a, float64 b, float_status *status) { - FloatParts64 pa =3D float64_unpack_canonical(a, status); - FloatParts64 pb =3D float64_unpack_canonical(b, status); - FloatParts64 pr =3D mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr =3D mul_floats(pa, pb, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1355,9 +1369,11 @@ float64_mul(float64 a, float64 b, float_status *s) =20 bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *s= tatus) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); - FloatParts64 pr =3D mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr =3D mul_floats(pa, pb, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1551,10 +1567,12 @@ static FloatParts64 muladd_floats(FloatParts64 a, F= loatParts64 b, FloatParts64 c float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, int flags, float_status *s= tatus) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pb =3D float16_unpack_canonical(b, status); - FloatParts64 pc =3D float16_unpack_canonical(c, status); - FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + float16_unpack_canonical(&pc, c, status); + pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1563,10 +1581,12 @@ static float32 QEMU_SOFTFLOAT_ATTR soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float_status *status) { - FloatParts64 pa =3D float32_unpack_canonical(a, status); - FloatParts64 pb =3D float32_unpack_canonical(b, status); - FloatParts64 pc =3D float32_unpack_canonical(c, status); - FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + float32_unpack_canonical(&pc, c, status); + pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1575,10 +1595,12 @@ static float64 QEMU_SOFTFLOAT_ATTR soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float_status *status) { - FloatParts64 pa =3D float64_unpack_canonical(a, status); - FloatParts64 pb =3D float64_unpack_canonical(b, status); - FloatParts64 pc =3D float64_unpack_canonical(c, status); - FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + float64_unpack_canonical(&pc, c, status); + pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1736,10 +1758,12 @@ float64_muladd(float64 xa, float64 xb, float64 xc, = int flags, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); - FloatParts64 pc =3D bfloat16_unpack_canonical(c, status); - FloatParts64 pr =3D muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + bfloat16_unpack_canonical(&pc, c, status); + pr =3D muladd_floats(pa, pb, pc, flags, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1818,9 +1842,11 @@ static FloatParts64 div_floats(FloatParts64 a, Float= Parts64 b, float_status *s) =20 float16 float16_div(float16 a, float16 b, float_status *status) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pb =3D float16_unpack_canonical(b, status); - FloatParts64 pr =3D div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr =3D div_floats(pa, pb, status); =20 return float16_round_pack_canonical(pr, status); } @@ -1828,9 +1854,11 @@ float16 float16_div(float16 a, float16 b, float_stat= us *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_div(float32 a, float32 b, float_status *status) { - FloatParts64 pa =3D float32_unpack_canonical(a, status); - FloatParts64 pb =3D float32_unpack_canonical(b, status); - FloatParts64 pr =3D div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr =3D div_floats(pa, pb, status); =20 return float32_round_pack_canonical(pr, status); } @@ -1838,9 +1866,11 @@ soft_f32_div(float32 a, float32 b, float_status *sta= tus) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_div(float64 a, float64 b, float_status *status) { - FloatParts64 pa =3D float64_unpack_canonical(a, status); - FloatParts64 pb =3D float64_unpack_canonical(b, status); - FloatParts64 pr =3D div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr =3D div_floats(pa, pb, status); =20 return float64_round_pack_canonical(pr, status); } @@ -1910,9 +1940,11 @@ float64_div(float64 a, float64 b, float_status *s) =20 bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); - FloatParts64 pr =3D div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr =3D div_floats(pa, pb, status); =20 return bfloat16_round_pack_canonical(pr, status); } @@ -1966,32 +1998,40 @@ static FloatParts64 float_to_float(FloatParts64 a, = const FloatFmt *dstf, float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p =3D float16a_unpack_canonical(a, s, fmt16); - FloatParts64 pr =3D float_to_float(p, &float32_params, s); + FloatParts64 pa, pr; + + float16a_unpack_canonical(&pa, a, s, fmt16); + pr =3D float_to_float(pa, &float32_params, s); return float32_round_pack_canonical(pr, s); } =20 float64 float16_to_float64(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p =3D float16a_unpack_canonical(a, s, fmt16); - FloatParts64 pr =3D float_to_float(p, &float64_params, s); + FloatParts64 pa, pr; + + float16a_unpack_canonical(&pa, a, s, fmt16); + pr =3D float_to_float(pa, &float64_params, s); return float64_round_pack_canonical(pr, s); } =20 float16 float32_to_float16(float32 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p =3D float32_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, fmt16, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_float32_to_float64(float32 a, float_status *s) { - FloatParts64 p =3D float32_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, &float64_params, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, &float64_params, s); return float64_round_pack_canonical(pr, s); } =20 @@ -2014,43 +2054,55 @@ float64 float32_to_float64(float32 a, float_status = *s) float16 float64_to_float16(float64 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p =3D float64_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, fmt16, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } =20 float32 float64_to_float32(float64 a, float_status *s) { - FloatParts64 p =3D float64_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, &float32_params, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, &float32_params, s); return float32_round_pack_canonical(pr, s); } =20 float32 bfloat16_to_float32(bfloat16 a, float_status *s) { - FloatParts64 p =3D bfloat16_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, &float32_params, s); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, &float32_params, s); return float32_round_pack_canonical(pr, s); } =20 float64 bfloat16_to_float64(bfloat16 a, float_status *s) { - FloatParts64 p =3D bfloat16_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, &float64_params, s); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, &float64_params, s); return float64_round_pack_canonical(pr, s); } =20 bfloat16 float32_to_bfloat16(float32 a, float_status *s) { - FloatParts64 p =3D float32_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, &bfloat16_params, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } =20 bfloat16 float64_to_bfloat16(float64 a, float_status *s) { - FloatParts64 p =3D float64_unpack_canonical(a, s); - FloatParts64 pr =3D float_to_float(p, &bfloat16_params, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr =3D float_to_float(pa, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } =20 @@ -2164,22 +2216,28 @@ static FloatParts64 round_to_int(FloatParts64 a, Fl= oatRoundMode rmode, =20 float16 float16_round_to_int(float16 a, float_status *s) { - FloatParts64 pa =3D float16_unpack_canonical(a, s); - FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + float16_unpack_canonical(&pa, a, s); + pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return float16_round_pack_canonical(pr, s); } =20 float32 float32_round_to_int(float32 a, float_status *s) { - FloatParts64 pa =3D float32_unpack_canonical(a, s); - FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return float32_round_pack_canonical(pr, s); } =20 float64 float64_round_to_int(float64 a, float_status *s) { - FloatParts64 pa =3D float64_unpack_canonical(a, s); - FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return float64_round_pack_canonical(pr, s); } =20 @@ -2190,8 +2248,10 @@ float64 float64_round_to_int(float64 a, float_status= *s) =20 bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, s); - FloatParts64 pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, s); + pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); return bfloat16_round_pack_canonical(pr, s); } =20 @@ -2253,71 +2313,91 @@ static int64_t round_to_int_and_pack(FloatParts64 i= n, FloatRoundMode rmode, int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT8_MIN, INT8_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT8_MIN, INT8_MAX, s); } =20 int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float32_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float32_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float32_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float64_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float64_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float64_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int8_t float16_to_int8(float16 a, float_status *s) @@ -2423,22 +2503,28 @@ int64_t float64_to_int64_round_to_zero(float64 a, f= loat_status *s) int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_int_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_int_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_int_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int16_t bfloat16_to_int16(bfloat16 a, float_status *s) @@ -2532,71 +2618,91 @@ static uint64_t round_to_uint_and_pack(FloatParts64= in, FloatRoundMode rmode, uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT8_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT8_MAX, s); } =20 uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } =20 uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } =20 uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } =20 uint16_t float32_to_uint16_scalbn(float32 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float32_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } =20 uint32_t float32_to_uint32_scalbn(float32 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float32_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } =20 uint64_t float32_to_uint64_scalbn(float32 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float32_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } =20 uint16_t float64_to_uint16_scalbn(float64 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float64_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } =20 uint32_t float64_to_uint32_scalbn(float64 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float64_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } =20 uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int sca= le, float_status *s) { - return round_to_uint_and_pack(float64_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } =20 uint8_t float16_to_uint8(float16 a, float_status *s) @@ -2702,22 +2808,28 @@ uint64_t float64_to_uint64_round_to_zero(float64 a,= float_status *s) uint16_t bfloat16_to_uint16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } =20 uint32_t bfloat16_to_uint32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } =20 uint64_t bfloat16_to_uint64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } =20 uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s) @@ -3168,10 +3280,10 @@ static FloatParts64 minmax_floats(FloatParts64 a, F= loatParts64 b, bool ismin, float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ - FloatParts64 pa =3D float ## sz ## _unpack_canonical(a, s); = \ - FloatParts64 pb =3D float ## sz ## _unpack_canonical(b, s); = \ - FloatParts64 pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); = \ - \ + FloatParts64 pa, pb, pr; \ + float ## sz ## _unpack_canonical(&pa, a, s); \ + float ## sz ## _unpack_canonical(&pb, b, s); \ + pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ return float ## sz ## _round_pack_canonical(pr, s); \ } =20 @@ -3201,10 +3313,10 @@ MINMAX(64, maxnummag, false, true, true) #define BF16_MINMAX(name, ismin, isiee, ismag) \ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ { \ - FloatParts64 pa =3D bfloat16_unpack_canonical(a, s); = \ - FloatParts64 pb =3D bfloat16_unpack_canonical(b, s); = \ - FloatParts64 pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); = \ - \ + FloatParts64 pa, pb, pr; \ + bfloat16_unpack_canonical(&pa, a, s); \ + bfloat16_unpack_canonical(&pb, b, s); \ + pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ return bfloat16_round_pack_canonical(pr, s); \ } =20 @@ -3279,8 +3391,9 @@ static FloatRelation compare_floats(FloatParts64 a, F= loatParts64 b, bool is_quie static int attr \ name(float ## sz a, float ## sz b, bool is_quiet, float_status *s) \ { \ - FloatParts64 pa =3D float ## sz ## _unpack_canonical(a, s); = \ - FloatParts64 pb =3D float ## sz ## _unpack_canonical(b, s); = \ + FloatParts64 pa, pb; \ + float ## sz ## _unpack_canonical(&pa, a, s); \ + float ## sz ## _unpack_canonical(&pb, b, s); \ return compare_floats(pa, pb, is_quiet, s); \ } =20 @@ -3381,8 +3494,10 @@ FloatRelation float64_compare_quiet(float64 a, float= 64 b, float_status *s) static FloatRelation QEMU_FLATTEN soft_bf16_compare(bfloat16 a, bfloat16 b, bool is_quiet, float_status *s) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, s); - FloatParts64 pb =3D bfloat16_unpack_canonical(b, s); + FloatParts64 pa, pb; + + bfloat16_unpack_canonical(&pa, a, s); + bfloat16_unpack_canonical(&pb, b, s); return compare_floats(pa, pb, is_quiet, s); } =20 @@ -3416,29 +3531,37 @@ static FloatParts64 scalbn_decomposed(FloatParts64 = a, int n, float_status *s) =20 float16 float16_scalbn(float16 a, int n, float_status *status) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + float16_unpack_canonical(&pa, a, status); + pr =3D scalbn_decomposed(pa, n, status); return float16_round_pack_canonical(pr, status); } =20 float32 float32_scalbn(float32 a, int n, float_status *status) { - FloatParts64 pa =3D float32_unpack_canonical(a, status); - FloatParts64 pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, status); + pr =3D scalbn_decomposed(pa, n, status); return float32_round_pack_canonical(pr, status); } =20 float64 float64_scalbn(float64 a, int n, float_status *status) { - FloatParts64 pa =3D float64_unpack_canonical(a, status); - FloatParts64 pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, status); + pr =3D scalbn_decomposed(pa, n, status); return float64_round_pack_canonical(pr, status); } =20 bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pr =3D scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, status); + pr =3D scalbn_decomposed(pa, n, status); return bfloat16_round_pack_canonical(pr, status); } =20 @@ -3515,24 +3638,30 @@ static FloatParts64 sqrt_float(FloatParts64 a, floa= t_status *s, const FloatFmt * =20 float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) { - FloatParts64 pa =3D float16_unpack_canonical(a, status); - FloatParts64 pr =3D sqrt_float(pa, status, &float16_params); + FloatParts64 pa, pr; + + float16_unpack_canonical(&pa, a, status); + pr =3D sqrt_float(pa, status, &float16_params); return float16_round_pack_canonical(pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR soft_f32_sqrt(float32 a, float_status *status) { - FloatParts64 pa =3D float32_unpack_canonical(a, status); - FloatParts64 pr =3D sqrt_float(pa, status, &float32_params); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, status); + pr =3D sqrt_float(pa, status, &float32_params); return float32_round_pack_canonical(pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_f64_sqrt(float64 a, float_status *status) { - FloatParts64 pa =3D float64_unpack_canonical(a, status); - FloatParts64 pr =3D sqrt_float(pa, status, &float64_params); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, status); + pr =3D sqrt_float(pa, status, &float64_params); return float64_round_pack_canonical(pr, status); } =20 @@ -3592,8 +3721,10 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_= status *s) =20 bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { - FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); - FloatParts64 pr =3D sqrt_float(pa, status, &bfloat16_params); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, status); + pr =3D sqrt_float(pa, status, &bfloat16_params); return bfloat16_round_pack_canonical(pr, status); } =20 --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Fri, 07 May 2021 18:48:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 23/72] softfloat: Use pointers with ftype_round_pack_canonical Date: Fri, 7 May 2021 18:47:13 -0700 Message-Id: <20210508014802.892561-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 131 +++++++++++++++++++++++++----------------------- 1 file changed, 68 insertions(+), 63 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e53d4a138f..b0cbd5941c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -945,22 +945,25 @@ static void bfloat16_unpack_canonical(FloatParts64 *p= , bfloat16 f, *p =3D sf_canonicalize(*p, &bfloat16_params, s); } =20 -static float16 float16a_round_pack_canonical(FloatParts64 p, float_status = *s, +static float16 float16a_round_pack_canonical(FloatParts64 *p, + float_status *s, const FloatFmt *params) { - p =3D round_canonical(p, s, params); - return float16_pack_raw(&p); + *p =3D round_canonical(*p, s, params); + return float16_pack_raw(p); } =20 -static float16 float16_round_pack_canonical(FloatParts64 p, float_status *= s) +static float16 float16_round_pack_canonical(FloatParts64 *p, + float_status *s) { return float16a_round_pack_canonical(p, s, &float16_params); } =20 -static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status= *s) +static bfloat16 bfloat16_round_pack_canonical(FloatParts64 *p, + float_status *s) { - p =3D round_canonical(p, s, &bfloat16_params); - return bfloat16_pack_raw(&p); + *p =3D round_canonical(*p, s, &bfloat16_params); + return bfloat16_pack_raw(p); } =20 static void float32_unpack_canonical(FloatParts64 *p, float32 f, @@ -970,10 +973,11 @@ static void float32_unpack_canonical(FloatParts64 *p,= float32 f, *p =3D sf_canonicalize(*p, &float32_params, s); } =20 -static float32 float32_round_pack_canonical(FloatParts64 p, float_status *= s) +static float32 float32_round_pack_canonical(FloatParts64 *p, + float_status *s) { - p =3D round_canonical(p, s, &float32_params); - return float32_pack_raw(&p); + *p =3D round_canonical(*p, s, &float32_params); + return float32_pack_raw(p); } =20 static void float64_unpack_canonical(FloatParts64 *p, float64 f, @@ -983,10 +987,11 @@ static void float64_unpack_canonical(FloatParts64 *p,= float64 f, *p =3D sf_canonicalize(*p, &float64_params, s); } =20 -static float64 float64_round_pack_canonical(FloatParts64 p, float_status *= s) +static float64 float64_round_pack_canonical(FloatParts64 *p, + float_status *s) { - p =3D round_canonical(p, s, &float64_params); - return float64_pack_raw(&p); + *p =3D round_canonical(*p, s, &float64_params); + return float64_pack_raw(p); } =20 /* @@ -1093,7 +1098,7 @@ float16 QEMU_FLATTEN float16_add(float16 a, float16 b= , float_status *status) float16_unpack_canonical(&pb, b, status); pr =3D addsub_floats(pa, pb, false, status); =20 - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *statu= s) @@ -1104,7 +1109,7 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 b= , float_status *status) float16_unpack_canonical(&pb, b, status); pr =3D addsub_floats(pa, pb, true, status); =20 - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR @@ -1116,7 +1121,7 @@ soft_f32_addsub(float32 a, float32 b, bool subtract, = float_status *status) float32_unpack_canonical(&pb, b, status); pr =3D addsub_floats(pa, pb, subtract, status); =20 - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } =20 static inline float32 soft_f32_add(float32 a, float32 b, float_status *sta= tus) @@ -1138,7 +1143,7 @@ soft_f64_addsub(float64 a, float64 b, bool subtract, = float_status *status) float64_unpack_canonical(&pb, b, status); pr =3D addsub_floats(pa, pb, subtract, status); =20 - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } =20 static inline float64 soft_f64_add(float64 a, float64 b, float_status *sta= tus) @@ -1238,7 +1243,7 @@ bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat= 16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr =3D addsub_floats(pa, pb, false, status); =20 - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *s= tatus) @@ -1249,7 +1254,7 @@ bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat= 16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr =3D addsub_floats(pa, pb, true, status); =20 - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 /* @@ -1311,7 +1316,7 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b= , float_status *status) float16_unpack_canonical(&pb, b, status); pr =3D mul_floats(pa, pb, status); =20 - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR @@ -1323,7 +1328,7 @@ soft_f32_mul(float32 a, float32 b, float_status *stat= us) float32_unpack_canonical(&pb, b, status); pr =3D mul_floats(pa, pb, status); =20 - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR @@ -1335,7 +1340,7 @@ soft_f64_mul(float64 a, float64 b, float_status *stat= us) float64_unpack_canonical(&pb, b, status); pr =3D mul_floats(pa, pb, status); =20 - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } =20 static float hard_f32_mul(float a, float b) @@ -1375,7 +1380,7 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat= 16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr =3D mul_floats(pa, pb, status); =20 - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 /* @@ -1574,7 +1579,7 @@ float16 QEMU_FLATTEN float16_muladd(float16 a, float1= 6 b, float16 c, float16_unpack_canonical(&pc, c, status); pr =3D muladd_floats(pa, pb, pc, flags, status); =20 - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR @@ -1588,7 +1593,7 @@ soft_f32_muladd(float32 a, float32 b, float32 c, int = flags, float32_unpack_canonical(&pc, c, status); pr =3D muladd_floats(pa, pb, pc, flags, status); =20 - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR @@ -1602,7 +1607,7 @@ soft_f64_muladd(float64 a, float64 b, float64 c, int = flags, float64_unpack_canonical(&pc, c, status); pr =3D muladd_floats(pa, pb, pc, flags, status); =20 - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } =20 static bool force_soft_fma; @@ -1765,7 +1770,7 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfl= oat16 b, bfloat16 c, bfloat16_unpack_canonical(&pc, c, status); pr =3D muladd_floats(pa, pb, pc, flags, status); =20 - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 /* @@ -1848,7 +1853,7 @@ float16 float16_div(float16 a, float16 b, float_statu= s *status) float16_unpack_canonical(&pb, b, status); pr =3D div_floats(pa, pb, status); =20 - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR @@ -1860,7 +1865,7 @@ soft_f32_div(float32 a, float32 b, float_status *stat= us) float32_unpack_canonical(&pb, b, status); pr =3D div_floats(pa, pb, status); =20 - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR @@ -1872,7 +1877,7 @@ soft_f64_div(float64 a, float64 b, float_status *stat= us) float64_unpack_canonical(&pb, b, status); pr =3D div_floats(pa, pb, status); =20 - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } =20 static float hard_f32_div(float a, float b) @@ -1946,7 +1951,7 @@ bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_s= tatus *status) bfloat16_unpack_canonical(&pb, b, status); pr =3D div_floats(pa, pb, status); =20 - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 /* @@ -2002,7 +2007,7 @@ float32 float16_to_float32(float16 a, bool ieee, floa= t_status *s) =20 float16a_unpack_canonical(&pa, a, s, fmt16); pr =3D float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } =20 float64 float16_to_float64(float16 a, bool ieee, float_status *s) @@ -2012,7 +2017,7 @@ float64 float16_to_float64(float16 a, bool ieee, floa= t_status *s) =20 float16a_unpack_canonical(&pa, a, s, fmt16); pr =3D float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } =20 float16 float32_to_float16(float32 a, bool ieee, float_status *s) @@ -2022,7 +2027,7 @@ float16 float32_to_float16(float32 a, bool ieee, floa= t_status *s) =20 float32_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(pr, s, fmt16); + return float16a_round_pack_canonical(&pr, s, fmt16); } =20 static float64 QEMU_SOFTFLOAT_ATTR @@ -2032,7 +2037,7 @@ soft_float32_to_float64(float32 a, float_status *s) =20 float32_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } =20 float64 float32_to_float64(float32 a, float_status *s) @@ -2058,7 +2063,7 @@ float16 float64_to_float16(float64 a, bool ieee, floa= t_status *s) =20 float64_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(pr, s, fmt16); + return float16a_round_pack_canonical(&pr, s, fmt16); } =20 float32 float64_to_float32(float64 a, float_status *s) @@ -2067,7 +2072,7 @@ float32 float64_to_float32(float64 a, float_status *s) =20 float64_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } =20 float32 bfloat16_to_float32(bfloat16 a, float_status *s) @@ -2076,7 +2081,7 @@ float32 bfloat16_to_float32(bfloat16 a, float_status = *s) =20 bfloat16_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } =20 float64 bfloat16_to_float64(bfloat16 a, float_status *s) @@ -2085,7 +2090,7 @@ float64 bfloat16_to_float64(bfloat16 a, float_status = *s) =20 bfloat16_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } =20 bfloat16 float32_to_bfloat16(float32 a, float_status *s) @@ -2094,7 +2099,7 @@ bfloat16 float32_to_bfloat16(float32 a, float_status = *s) =20 float32_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(pr, s); + return bfloat16_round_pack_canonical(&pr, s); } =20 bfloat16 float64_to_bfloat16(float64 a, float_status *s) @@ -2103,7 +2108,7 @@ bfloat16 float64_to_bfloat16(float64 a, float_status = *s) =20 float64_unpack_canonical(&pa, a, s); pr =3D float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(pr, s); + return bfloat16_round_pack_canonical(&pr, s); } =20 /* @@ -2220,7 +2225,7 @@ float16 float16_round_to_int(float16 a, float_status = *s) =20 float16_unpack_canonical(&pa, a, s); pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return float16_round_pack_canonical(pr, s); + return float16_round_pack_canonical(&pr, s); } =20 float32 float32_round_to_int(float32 a, float_status *s) @@ -2229,7 +2234,7 @@ float32 float32_round_to_int(float32 a, float_status = *s) =20 float32_unpack_canonical(&pa, a, s); pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } =20 float64 float64_round_to_int(float64 a, float_status *s) @@ -2238,7 +2243,7 @@ float64 float64_round_to_int(float64 a, float_status = *s) =20 float64_unpack_canonical(&pa, a, s); pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } =20 /* @@ -2252,7 +2257,7 @@ bfloat16 bfloat16_round_to_int(bfloat16 a, float_stat= us *s) =20 bfloat16_unpack_canonical(&pa, a, s); pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return bfloat16_round_pack_canonical(pr, s); + return bfloat16_round_pack_canonical(&pr, s); } =20 /* @@ -2898,7 +2903,7 @@ static FloatParts64 int_to_float(int64_t a, int scale= , float_status *status) float16 int64_to_float16_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa =3D int_to_float(a, scale, status); - return float16_round_pack_canonical(pa, status); + return float16_round_pack_canonical(&pa, status); } =20 float16 int32_to_float16_scalbn(int32_t a, int scale, float_status *status) @@ -2934,7 +2939,7 @@ float16 int8_to_float16(int8_t a, float_status *statu= s) float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa =3D int_to_float(a, scale, status); - return float32_round_pack_canonical(pa, status); + return float32_round_pack_canonical(&pa, status); } =20 float32 int32_to_float32_scalbn(int32_t a, int scale, float_status *status) @@ -2965,7 +2970,7 @@ float32 int16_to_float32(int16_t a, float_status *sta= tus) float64 int64_to_float64_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa =3D int_to_float(a, scale, status); - return float64_round_pack_canonical(pa, status); + return float64_round_pack_canonical(&pa, status); } =20 float64 int32_to_float64_scalbn(int32_t a, int scale, float_status *status) @@ -3001,7 +3006,7 @@ float64 int16_to_float64(int16_t a, float_status *sta= tus) bfloat16 int64_to_bfloat16_scalbn(int64_t a, int scale, float_status *stat= us) { FloatParts64 pa =3D int_to_float(a, scale, status); - return bfloat16_round_pack_canonical(pa, status); + return bfloat16_round_pack_canonical(&pa, status); } =20 bfloat16 int32_to_bfloat16_scalbn(int32_t a, int scale, float_status *stat= us) @@ -3058,7 +3063,7 @@ static FloatParts64 uint_to_float(uint64_t a, int sca= le, float_status *status) float16 uint64_to_float16_scalbn(uint64_t a, int scale, float_status *stat= us) { FloatParts64 pa =3D uint_to_float(a, scale, status); - return float16_round_pack_canonical(pa, status); + return float16_round_pack_canonical(&pa, status); } =20 float16 uint32_to_float16_scalbn(uint32_t a, int scale, float_status *stat= us) @@ -3094,7 +3099,7 @@ float16 uint8_to_float16(uint8_t a, float_status *sta= tus) float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *stat= us) { FloatParts64 pa =3D uint_to_float(a, scale, status); - return float32_round_pack_canonical(pa, status); + return float32_round_pack_canonical(&pa, status); } =20 float32 uint32_to_float32_scalbn(uint32_t a, int scale, float_status *stat= us) @@ -3125,7 +3130,7 @@ float32 uint16_to_float32(uint16_t a, float_status *s= tatus) float64 uint64_to_float64_scalbn(uint64_t a, int scale, float_status *stat= us) { FloatParts64 pa =3D uint_to_float(a, scale, status); - return float64_round_pack_canonical(pa, status); + return float64_round_pack_canonical(&pa, status); } =20 float64 uint32_to_float64_scalbn(uint32_t a, int scale, float_status *stat= us) @@ -3161,7 +3166,7 @@ float64 uint16_to_float64(uint16_t a, float_status *s= tatus) bfloat16 uint64_to_bfloat16_scalbn(uint64_t a, int scale, float_status *st= atus) { FloatParts64 pa =3D uint_to_float(a, scale, status); - return bfloat16_round_pack_canonical(pa, status); + return bfloat16_round_pack_canonical(&pa, status); } =20 bfloat16 uint32_to_bfloat16_scalbn(uint32_t a, int scale, float_status *st= atus) @@ -3284,7 +3289,7 @@ float ## sz float ## sz ## _ ## name(float ## sz a, f= loat ## sz b, \ float ## sz ## _unpack_canonical(&pa, a, s); \ float ## sz ## _unpack_canonical(&pb, b, s); \ pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return float ## sz ## _round_pack_canonical(pr, s); \ + return float ## sz ## _round_pack_canonical(&pr, s); \ } =20 MINMAX(16, min, true, false, false) @@ -3317,7 +3322,7 @@ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, fl= oat_status *s) \ bfloat16_unpack_canonical(&pa, a, s); \ bfloat16_unpack_canonical(&pb, b, s); \ pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return bfloat16_round_pack_canonical(pr, s); \ + return bfloat16_round_pack_canonical(&pr, s); \ } =20 BF16_MINMAX(min, true, false, false) @@ -3535,7 +3540,7 @@ float16 float16_scalbn(float16 a, int n, float_status= *status) =20 float16_unpack_canonical(&pa, a, status); pr =3D scalbn_decomposed(pa, n, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 float32 float32_scalbn(float32 a, int n, float_status *status) @@ -3544,7 +3549,7 @@ float32 float32_scalbn(float32 a, int n, float_status= *status) =20 float32_unpack_canonical(&pa, a, status); pr =3D scalbn_decomposed(pa, n, status); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } =20 float64 float64_scalbn(float64 a, int n, float_status *status) @@ -3553,7 +3558,7 @@ float64 float64_scalbn(float64 a, int n, float_status= *status) =20 float64_unpack_canonical(&pa, a, status); pr =3D scalbn_decomposed(pa, n, status); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } =20 bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) @@ -3562,7 +3567,7 @@ bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_sta= tus *status) =20 bfloat16_unpack_canonical(&pa, a, status); pr =3D scalbn_decomposed(pa, n, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 /* @@ -3642,7 +3647,7 @@ float16 QEMU_FLATTEN float16_sqrt(float16 a, float_st= atus *status) =20 float16_unpack_canonical(&pa, a, status); pr =3D sqrt_float(pa, status, &float16_params); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR @@ -3652,7 +3657,7 @@ soft_f32_sqrt(float32 a, float_status *status) =20 float32_unpack_canonical(&pa, a, status); pr =3D sqrt_float(pa, status, &float32_params); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR @@ -3662,7 +3667,7 @@ soft_f64_sqrt(float64 a, float_status *status) =20 float64_unpack_canonical(&pa, a, status); pr =3D sqrt_float(pa, status, &float64_params); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } =20 float32 QEMU_FLATTEN float32_sqrt(float32 xa, float_status *s) @@ -3725,7 +3730,7 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float= _status *status) =20 bfloat16_unpack_canonical(&pa, a, status); pr =3D sqrt_float(pa, status, &bfloat16_params); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439784; cv=none; d=zohomail.com; s=zohoarc; b=Iw4aoTTPC2H9BMkfIznLRgzLIjVODZ6j3dWpqz9dhOLPncohF5LbQWSQlpYt3wl0OPHIWq117R+4NvoqViGlbBqsrQGPEo8yCBVH68rLBwKxJYOOB2gFVJCcldmlrNSk3SpLB+LtPBsQXsvS+HWoiEoQF7Uu5F9Rn0dKdtJxxhQ= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 24/72] softfloat: Use pointers with parts_silence_nan Date: Fri, 7 May 2021 18:47:14 -0700 Message-Id: <20210508014802.892561-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, rename to parts64_silence_nan, split out parts_silence_nan_frac, and define a macro for parts_silence_nan. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 16 +++++++++------- fpu/softfloat-specialize.c.inc | 17 +++++++++++------ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b0cbd5941c..2123453d40 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -657,6 +657,7 @@ static inline float64 float64_pack_raw(const FloatParts= 64 *p) #include "softfloat-specialize.c.inc" =20 #define parts_default_nan parts64_default_nan +#define parts_silence_nan parts64_silence_nan =20 /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *par= m, @@ -851,7 +852,8 @@ static FloatParts64 return_nan(FloatParts64 a, float_st= atus *s) if (is_snan(a.cls)) { float_raise(float_flag_invalid, s); if (!s->default_nan_mode) { - return parts_silence_nan(a, s); + parts_silence_nan(&a, s); + return a; } } else if (!s->default_nan_mode) { return a; @@ -875,7 +877,7 @@ static FloatParts64 pick_nan(FloatParts64 a, FloatParts= 64 b, float_status *s) a =3D b; } if (is_snan(a.cls)) { - return parts_silence_nan(a, s); + parts_silence_nan(&a, s); } } return a; @@ -916,7 +918,7 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, Flo= atParts64 b, FloatParts64 } =20 if (is_snan(a.cls)) { - return parts_silence_nan(a, s); + parts_silence_nan(&a, s); } return a; } @@ -3801,7 +3803,7 @@ float16 float16_silence_nan(float16 a, float_status *= status) =20 float16_unpack_raw(&p, a); p.frac <<=3D float16_params.frac_shift; - p =3D parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>=3D float16_params.frac_shift; return float16_pack_raw(&p); } @@ -3812,7 +3814,7 @@ float32 float32_silence_nan(float32 a, float_status *= status) =20 float32_unpack_raw(&p, a); p.frac <<=3D float32_params.frac_shift; - p =3D parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>=3D float32_params.frac_shift; return float32_pack_raw(&p); } @@ -3823,7 +3825,7 @@ float64 float64_silence_nan(float64 a, float_status *= status) =20 float64_unpack_raw(&p, a); p.frac <<=3D float64_params.frac_shift; - p =3D parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>=3D float64_params.frac_shift; return float64_pack_raw(&p); } @@ -3834,7 +3836,7 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_statu= s *status) =20 bfloat16_unpack_raw(&p, a); p.frac <<=3D bfloat16_params.frac_shift; - p =3D parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>=3D bfloat16_params.frac_shift; return bfloat16_pack_raw(&p); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 085ddea62b..2a1bc66633 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -177,20 +177,25 @@ static void parts64_default_nan(FloatParts64 *p, floa= t_status *status) | floating-point parts. *-------------------------------------------------------------------------= ---*/ =20 -static FloatParts64 parts_silence_nan(FloatParts64 a, float_status *status) +static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) { g_assert(!no_signaling_nans(status)); g_assert(!status->default_nan_mode); =20 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ if (snan_bit_is_one(status)) { - a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); - a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); + frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); } else { - a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); + frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 1); } - a.cls =3D float_class_qnan; - return a; + return frac; +} + +static void parts64_silence_nan(FloatParts64 *p, float_status *status) +{ + p->frac =3D parts_silence_nan_frac(p->frac, status); + p->cls =3D float_class_qnan; } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:48:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/72] softfloat: Rearrange FloatParts64 Date: Fri, 7 May 2021 18:47:15 -0700 Message-Id: <20210508014802.892561-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Shuffle the fraction to the end, otherwise sort by size. Add frac_hi and frac_lo members to alias frac. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2123453d40..2d6f61ee7a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -511,10 +511,19 @@ static inline __attribute__((unused)) bool is_qnan(Fl= oatClass c) */ =20 typedef struct { - uint64_t frac; - int32_t exp; FloatClass cls; bool sign; + int32_t exp; + union { + /* Routines that know the structure may reference the singular nam= e. */ + uint64_t frac; + /* + * Routines expanded with multiple structures reference "hi" and "= lo". + * In this structure, the one word is both highest and lowest. + */ + uint64_t frac_hi; + uint64_t frac_lo; + }; } FloatParts64; =20 #define DECOMPOSED_BINARY_POINT 63 --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:48:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/72] softfloat: Convert float128_silence_nan to parts Date: Fri, 7 May 2021 18:47:16 -0700 Message-Id: <20210508014802.892561-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This is the minimal change that also introduces float128_params, float128_unpack_raw, and float128_pack_raw without running into unused symbol Werrors. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 96 +++++++++++++++++++++++++++++----- fpu/softfloat-specialize.c.inc | 25 +++------ 2 files changed, 89 insertions(+), 32 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2d6f61ee7a..073b80d502 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -500,14 +500,12 @@ static inline __attribute__((unused)) bool is_qnan(Fl= oatClass c) } =20 /* - * Structure holding all of the decomposed parts of a float. The - * exponent is unbiased and the fraction is normalized. All - * calculations are done with a 64 bit fraction and then rounded as - * appropriate for the final format. + * Structure holding all of the decomposed parts of a float. + * The exponent is unbiased and the fraction is normalized. * - * Thanks to the packed FloatClass a decent compiler should be able to - * fit the whole structure into registers and avoid using the stack - * for parameter passing. + * The fraction words are stored in big-endian word ordering, + * so that truncation from a larger format to a smaller format + * can be done simply by ignoring subsequent elements. */ =20 typedef struct { @@ -526,6 +524,15 @@ typedef struct { }; } FloatParts64; =20 +typedef struct { + FloatClass cls; + bool sign; + int32_t exp; + uint64_t frac_hi; + uint64_t frac_lo; +} FloatParts128; + +/* These apply to the most significant word of each FloatPartsN. */ #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) =20 @@ -561,11 +568,11 @@ typedef struct { .exp_bias =3D ((1 << E) - 1) >> 1, \ .exp_max =3D (1 << E) - 1, \ .frac_size =3D F, \ - .frac_shift =3D DECOMPOSED_BINARY_POINT - F, \ - .frac_lsb =3D 1ull << (DECOMPOSED_BINARY_POINT - F), \ - .frac_lsbm1 =3D 1ull << ((DECOMPOSED_BINARY_POINT - F) - 1), \ - .round_mask =3D (1ull << (DECOMPOSED_BINARY_POINT - F)) - 1, \ - .roundeven_mask =3D (2ull << (DECOMPOSED_BINARY_POINT - F)) - 1 + .frac_shift =3D (-F - 1) & 63, \ + .frac_lsb =3D 1ull << ((-F - 1) & 63), \ + .frac_lsbm1 =3D 1ull << ((-F - 2) & 63), \ + .round_mask =3D (1ull << ((-F - 1) & 63)) - 1, \ + .roundeven_mask =3D (2ull << ((-F - 1) & 63)) - 1 =20 static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) @@ -588,6 +595,10 @@ static const FloatFmt float64_params =3D { FLOAT_PARAMS(11, 52) }; =20 +static const FloatFmt float128_params =3D { + FLOAT_PARAMS(15, 112) +}; + /* Unpack a float to parts, but do not canonicalize. */ static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t ra= w) { @@ -622,6 +633,20 @@ static inline void float64_unpack_raw(FloatParts64 *p,= float64 f) unpack_raw64(p, &float64_params, f); } =20 +static void float128_unpack_raw(FloatParts128 *p, float128 f) +{ + const int f_size =3D float128_params.frac_size - 64; + const int e_size =3D float128_params.exp_size; + + *p =3D (FloatParts128) { + .cls =3D float_class_unclassified, + .sign =3D extract64(f.high, f_size + e_size, 1), + .exp =3D extract64(f.high, f_size, e_size), + .frac_hi =3D extract64(f.high, 0, f_size), + .frac_lo =3D f.low, + }; +} + /* Pack a float from parts, but do not canonicalize. */ static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt) { @@ -655,6 +680,18 @@ static inline float64 float64_pack_raw(const FloatPart= s64 *p) return make_float64(pack_raw64(p, &float64_params)); } =20 +static float128 float128_pack_raw(const FloatParts128 *p) +{ + const int f_size =3D float128_params.frac_size - 64; + const int e_size =3D float128_params.exp_size; + uint64_t hi; + + hi =3D (uint64_t)p->sign << (f_size + e_size); + hi =3D deposit64(hi, f_size, e_size, p->exp); + hi =3D deposit64(hi, 0, f_size, p->frac_hi); + return make_float128(hi, p->frac_lo); +} + /*------------------------------------------------------------------------= ---- | Functions and definitions to determine: (1) whether tininess for underf= low | is detected before or after rounding by default, (2) what (if anything) @@ -665,8 +702,30 @@ static inline float64 float64_pack_raw(const FloatPart= s64 *p) *-------------------------------------------------------------------------= ---*/ #include "softfloat-specialize.c.inc" =20 +#define PARTS_GENERIC_64_128(NAME, P) \ + QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) + #define parts_default_nan parts64_default_nan -#define parts_silence_nan parts64_silence_nan +#define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P,= S) + + +/* + * Helper functions for softfloat-parts.c.inc, per-size operations. + */ + +static void frac128_shl(FloatParts128 *a, int c) +{ + shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shl(A, C) frac128_shl(A, C) + +static void frac128_shr(FloatParts128 *a, int c) +{ + shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shr(A, C) frac128_shr(A, C) =20 /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *par= m, @@ -3850,6 +3909,17 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_stat= us *status) return bfloat16_pack_raw(&p); } =20 +float128 float128_silence_nan(float128 a, float_status *status) +{ + FloatParts128 p; + + float128_unpack_raw(&p, a); + frac_shl(&p, float128_params.frac_shift); + parts_silence_nan(&p, status); + frac_shr(&p, float128_params.frac_shift); + return float128_pack_raw(&p); +} + /*------------------------------------------------------------------------= ---- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the valu= e. diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2a1bc66633..d892016f0f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -198,6 +198,12 @@ static void parts64_silence_nan(FloatParts64 *p, float= _status *status) p->cls =3D float_class_qnan; } =20 +static void parts128_silence_nan(FloatParts128 *p, float_status *status) +{ + p->frac_hi =3D parts_silence_nan_frac(p->frac_hi, status); + p->cls =3D float_class_qnan; +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated extended double-precision NaN. *-------------------------------------------------------------------------= ---*/ @@ -1057,25 +1063,6 @@ bool float128_is_signaling_nan(float128 a, float_sta= tus *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Returns a quiet NaN from a signalling NaN for the quadruple-precision -| floating point value `a'. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_silence_nan(float128 a, float_status *status) -{ - if (no_signaling_nans(status)) { - g_assert_not_reached(); - } else { - if (snan_bit_is_one(status)) { - return float128_default_nan(status); - } else { - a.high |=3D UINT64_C(0x0000800000000000); - return a; - } - } -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point = NaN | `a' to the canonical NaN format. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 17 ++++------------- fpu/softfloat-specialize.c.inc | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 073b80d502..6d5392aeab 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -705,7 +705,7 @@ static float128 float128_pack_raw(const FloatParts128 *= p) #define PARTS_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) =20 -#define parts_default_nan parts64_default_nan +#define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P,= S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P,= S) =20 =20 @@ -3836,20 +3836,11 @@ float64 float64_default_nan(float_status *status) =20 float128 float128_default_nan(float_status *status) { - FloatParts64 p; - float128 r; + FloatParts128 p; =20 parts_default_nan(&p, status); - /* Extrapolate from the choices made by parts_default_nan to fill - * in the quad-floating format. If the low bit is set, assume we - * want to set all non-snan bits. - */ - r.low =3D -(p.frac & 1); - r.high =3D p.frac >> (DECOMPOSED_BINARY_POINT - 48); - r.high |=3D UINT64_C(0x7FFF000000000000); - r.high |=3D (uint64_t)p.sign << 63; - - return r; + frac_shr(&p, float128_params.frac_shift); + return float128_pack_raw(&p); } =20 bfloat16 bfloat16_default_nan(float_status *status) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d892016f0f..a0cf016b4f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -172,6 +172,25 @@ static void parts64_default_nan(FloatParts64 *p, float= _status *status) }; } =20 +static void parts128_default_nan(FloatParts128 *p, float_status *status) +{ + /* + * Extrapolate from the choices made by parts64_default_nan to fill + * in the quad-floating format. If the low bit is set, assume we + * want to set all non-snan bits. + */ + FloatParts64 p64; + parts64_default_nan(&p64, status); + + *p =3D (FloatParts128) { + .cls =3D float_class_qnan, + .sign =3D p64.sign, + .exp =3D INT_MAX, + .frac_hi =3D p64.frac, + .frac_lo =3D -(p64.frac & 1) + }; +} + /*------------------------------------------------------------------------= ---- | Returns a quiet NaN from a signalling NaN for the deconstructed | floating-point parts. --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440156; cv=none; d=zohomail.com; s=zohoarc; b=DNy2hWswLdOYuwSP3vbCkW3ScAC81L4LXo9cv4fzu+drZD8AtStCyqJNl64MHmJYIyd3DM6N81tu2FT7KLmsCP/lssbOGz3zTcrUzMtjeU1u29D61k7ww0XQQ8rKTFuSvQLbwkedibgQ4QvLxj1UQTCEAU4ub2kJPbaJQve6KLk= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/72] softfloat: Move return_nan to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:18 -0700 Message-Id: <20210508014802.892561-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, convert to pointers, rename to return_nan$N and define a macro for return_nan using QEMU_GENERIC. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- fpu/softfloat.c | 45 ++++++++++++++++++++++----------------- fpu/softfloat-parts.c.inc | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 20 deletions(-) create mode 100644 fpu/softfloat-parts.c.inc diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6d5392aeab..5b26696078 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -708,6 +708,10 @@ static float128 float128_pack_raw(const FloatParts128 = *p) #define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P,= S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P,= S) =20 +static void parts64_return_nan(FloatParts64 *a, float_status *s); +static void parts128_return_nan(FloatParts128 *a, float_status *s); + +#define parts_return_nan(P, S) PARTS_GENERIC_64_128(return_nan, P)(P, = S) =20 /* * Helper functions for softfloat-parts.c.inc, per-size operations. @@ -914,22 +918,6 @@ static FloatParts64 round_canonical(FloatParts64 p, fl= oat_status *s, return p; } =20 -static FloatParts64 return_nan(FloatParts64 a, float_status *s) -{ - g_assert(is_nan(a.cls)); - if (is_snan(a.cls)) { - float_raise(float_flag_invalid, s); - if (!s->default_nan_mode) { - parts_silence_nan(&a, s); - return a; - } - } else if (!s->default_nan_mode) { - return a; - } - parts_default_nan(&a, s); - return a; -} - static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status = *s) { if (is_snan(a.cls) || is_snan(b.cls)) { @@ -991,6 +979,21 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, Fl= oatParts64 b, FloatParts64 return a; } =20 +#define partsN(NAME) parts64_##NAME +#define FloatPartsN FloatParts64 + +#include "softfloat-parts.c.inc" + +#undef partsN +#undef FloatPartsN +#define partsN(NAME) parts128_##NAME +#define FloatPartsN FloatParts128 + +#include "softfloat-parts.c.inc" + +#undef partsN +#undef FloatPartsN + /* * Pack/unpack routines with a specific FloatFmt. */ @@ -2065,7 +2068,7 @@ static FloatParts64 float_to_float(FloatParts64 a, co= nst FloatFmt *dstf, break; } } else if (is_nan(a.cls)) { - return return_nan(a, s); + parts_return_nan(&a, s); } return a; } @@ -2194,7 +2197,8 @@ static FloatParts64 round_to_int(FloatParts64 a, Floa= tRoundMode rmode, switch (a.cls) { case float_class_qnan: case float_class_snan: - return return_nan(a, s); + parts_return_nan(&a, s); + break; =20 case float_class_zero: case float_class_inf: @@ -3590,7 +3594,7 @@ FloatRelation bfloat16_compare_quiet(bfloat16 a, bflo= at16 b, float_status *s) static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status = *s) { if (unlikely(is_nan(a.cls))) { - return return_nan(a, s); + parts_return_nan(&a, s); } if (a.cls =3D=3D float_class_normal) { /* The largest float type (even though not supported by FloatParts= 64) @@ -3658,7 +3662,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_= status *s, const FloatFmt * int bit, last_bit; =20 if (is_nan(a.cls)) { - return return_nan(a, s); + parts_return_nan(&a, s); + return a; } if (a.cls =3D=3D float_class_zero) { return a; /* sqrt(+-0) =3D +-0 */ diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc new file mode 100644 index 0000000000..2a3075d6fe --- /dev/null +++ b/fpu/softfloat-parts.c.inc @@ -0,0 +1,37 @@ +/* + * QEMU float support + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed = below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file after December 1st 2014 will be + * taken to be licensed under the Softfloat-2a license unless specifically + * indicated otherwise. + */ + +static void partsN(return_nan)(FloatPartsN *a, float_status *s) +{ + switch (a->cls) { + case float_class_snan: + float_raise(float_flag_invalid, s); + if (s->default_nan_mode) { + parts_default_nan(a, s); + } else { + parts_silence_nan(a, s); + } + break; + case float_class_qnan: + if (s->default_nan_mode) { + parts_default_nan(a, s); + } + break; + default: + g_assert_not_reached(); + } +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, convert to pointers, rename to parts$N_pick_nan and define a macro for parts_pick_nan using QEMU_GENERIC. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- fpu/softfloat.c | 62 ++++++++++++++++++++++----------------- fpu/softfloat-parts.c.inc | 25 ++++++++++++++++ 2 files changed, 60 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5b26696078..77efaedeaa 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -713,10 +713,39 @@ static void parts128_return_nan(FloatParts128 *a, flo= at_status *s); =20 #define parts_return_nan(P, S) PARTS_GENERIC_64_128(return_nan, P)(P, = S) =20 +static FloatParts64 *parts64_pick_nan(FloatParts64 *a, FloatParts64 *b, + float_status *s); +static FloatParts128 *parts128_pick_nan(FloatParts128 *a, FloatParts128 *b, + float_status *s); + +#define parts_pick_nan(A, B, S) PARTS_GENERIC_64_128(pick_nan, A)(A, B,= S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ =20 +#define FRAC_GENERIC_64_128(NAME, P) \ + QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) + +static int frac64_cmp(FloatParts64 *a, FloatParts64 *b) +{ + return a->frac =3D=3D b->frac ? 0 : a->frac < b->frac ? -1 : 1; +} + +static int frac128_cmp(FloatParts128 *a, FloatParts128 *b) +{ + uint64_t ta =3D a->frac_hi, tb =3D b->frac_hi; + if (ta =3D=3D tb) { + ta =3D a->frac_lo, tb =3D b->frac_lo; + if (ta =3D=3D tb) { + return 0; + } + } + return ta < tb ? -1 : 1; +} + +#define frac_cmp(A, B) FRAC_GENERIC_64_128(cmp, A)(A, B) + static void frac128_shl(FloatParts128 *a, int c) { shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); @@ -918,27 +947,6 @@ static FloatParts64 round_canonical(FloatParts64 p, fl= oat_status *s, return p; } =20 -static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status = *s) -{ - if (is_snan(a.cls) || is_snan(b.cls)) { - float_raise(float_flag_invalid, s); - } - - if (s->default_nan_mode) { - parts_default_nan(&a, s); - } else { - if (pickNaN(a.cls, b.cls, - a.frac > b.frac || - (a.frac =3D=3D b.frac && a.sign < b.sign), s)) { - a =3D b; - } - if (is_snan(a.cls)) { - parts_silence_nan(&a, s); - } - } - return a; -} - static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatP= arts64 c, bool inf_zero, float_status *s) { @@ -1106,7 +1114,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, Flo= atParts64 b, bool subtract, return a; } if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } if (a.cls =3D=3D float_class_inf) { if (b.cls =3D=3D float_class_inf) { @@ -1144,7 +1152,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, Flo= atParts64 b, bool subtract, return a; } if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } if (a.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_zero)= { return a; @@ -1360,7 +1368,7 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatP= arts64 b, float_status *s) } /* handle all the NaN cases */ if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } /* Inf * Zero =3D=3D NaN */ if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || @@ -1887,7 +1895,7 @@ static FloatParts64 div_floats(FloatParts64 a, FloatP= arts64 b, float_status *s) } /* handle all the NaN cases */ if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } /* 0/0 or Inf/Inf */ if (a.cls =3D=3D b.cls @@ -3295,14 +3303,14 @@ static FloatParts64 minmax_floats(FloatParts64 a, F= loatParts64 b, bool ismin, * the invalid exception is raised. */ if (is_snan(a.cls) || is_snan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } else if (is_nan(a.cls) && !is_nan(b.cls)) { return b; } else if (is_nan(b.cls) && !is_nan(a.cls)) { return a; } } - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } else { int a_exp, b_exp; =20 diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 2a3075d6fe..11a71650f7 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -35,3 +35,28 @@ static void partsN(return_nan)(FloatPartsN *a, float_sta= tus *s) g_assert_not_reached(); } } + +static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, + float_status *s) +{ + if (is_snan(a->cls) || is_snan(b->cls)) { + float_raise(float_flag_invalid, s); + } + + if (s->default_nan_mode) { + parts_default_nan(a, s); + } else { + int cmp =3D frac_cmp(a, b); + if (cmp =3D=3D 0) { + cmp =3D a->sign < b->sign; + } + + if (pickNaN(a->cls, b->cls, cmp > 0, s)) { + a =3D b; + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); + } + } + return a; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620439357; cv=none; d=zohomail.com; s=zohoarc; b=Z1sjccH9PAmZCx/m2pQaxoKF9Rzdcko/Dlr1spOxSWnLGlEEFWHiqYs91pGjfRTXLxTAwrLfG0+jvtwPbVHzUz+3SEJxVBSZyLl66mumiPgb2JnkyutIe33rQ+CnVKUBA+fYpIXeITIRoCO/aLzW+5B+PLzM9OlOcGc3JH3x3nY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620439357; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, convert to pointers, rename to pick_nan_muladd$N and define a macro for pick_nan_muladd using QEMU_GENERIC. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- fpu/softfloat.c | 53 ++++++++++----------------------------- fpu/softfloat-parts.c.inc | 40 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 40 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 77efaedeaa..40ee294e35 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -720,6 +720,18 @@ static FloatParts128 *parts128_pick_nan(FloatParts128 = *a, FloatParts128 *b, =20 #define parts_pick_nan(A, B, S) PARTS_GENERIC_64_128(pick_nan, A)(A, B,= S) =20 +static FloatParts64 *parts64_pick_nan_muladd(FloatParts64 *a, FloatParts64= *b, + FloatParts64 *c, float_status= *s, + int ab_mask, int abc_mask); +static FloatParts128 *parts128_pick_nan_muladd(FloatParts128 *a, + FloatParts128 *b, + FloatParts128 *c, + float_status *s, + int ab_mask, int abc_mask); + +#define parts_pick_nan_muladd(A, B, C, S, ABM, ABCM) \ + PARTS_GENERIC_64_128(pick_nan_muladd, A)(A, B, C, S, ABM, ABCM) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -947,45 +959,6 @@ static FloatParts64 round_canonical(FloatParts64 p, fl= oat_status *s, return p; } =20 -static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatP= arts64 c, - bool inf_zero, float_status *s) -{ - int which; - - if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) { - float_raise(float_flag_invalid, s); - } - - which =3D pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); - - if (s->default_nan_mode) { - /* Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag. - */ - which =3D 3; - } - - switch (which) { - case 0: - break; - case 1: - a =3D b; - break; - case 2: - a =3D c; - break; - case 3: - parts_default_nan(&a, s); - break; - default: - g_assert_not_reached(); - } - - if (is_snan(a.cls)) { - parts_silence_nan(&a, s); - } - return a; -} =20 #define partsN(NAME) parts64_##NAME #define FloatPartsN FloatParts64 @@ -1496,7 +1469,7 @@ static FloatParts64 muladd_floats(FloatParts64 a, Flo= atParts64 b, FloatParts64 c * off to the target-specific pick-a-NaN routine. */ if (unlikely(abc_mask & float_cmask_anynan)) { - return pick_nan_muladd(a, b, c, inf_zero, s); + return *parts_pick_nan_muladd(&a, &b, &c, s, ab_mask, abc_mask); } =20 if (inf_zero) { diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 11a71650f7..a78d61ea07 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -60,3 +60,43 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, Flo= atPartsN *b, } return a; } + +static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, + FloatPartsN *c, float_status *= s, + int ab_mask, int abc_mask) +{ + int which; + + if (unlikely(abc_mask & float_cmask_snan)) { + float_raise(float_flag_invalid, s); + } + + which =3D pickNaNMulAdd(a->cls, b->cls, c->cls, + ab_mask =3D=3D float_cmask_infzero, s); + + if (s->default_nan_mode || which =3D=3D 3) { + /* + * Note that this check is after pickNaNMulAdd so that function + * has an opportunity to set the Invalid flag for infzero. + */ + parts_default_nan(a, s); + return a; + } + + switch (which) { + case 0: + break; + case 1: + a =3D b; + break; + case 2: + a =3D c; + break; + default: + g_assert_not_reached(); + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); + } + return a; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440225; cv=none; d=zohomail.com; s=zohoarc; b=DNJzNA7JK+p5XLV/ooDs2sYJa68egBxtR9lI3K0XXwKIOIua1A3k/tP06+rCivI/l9Q9KT8wb+2/jVybPze2hCBzKdVQcvkeynvK8AWqN8hLZlf9MokfAKvcLnN8bpv8yIyVjJNZVL2ZMN//bVbyrzBo0rwNpe/lqjEfyEo+HM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440225; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, convert to pointers, rename to parts$N_canonicalize and define a macro for parts_canonicalize using QEMU_GENERIC. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 117 +++++++++++++++++++++++++------------- fpu/softfloat-parts.c.inc | 33 +++++++++++ 2 files changed, 112 insertions(+), 38 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 40ee294e35..bad4b54cd2 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -732,6 +732,14 @@ static FloatParts128 *parts128_pick_nan_muladd(FloatPa= rts128 *a, #define parts_pick_nan_muladd(A, B, C, S, ABM, ABCM) \ PARTS_GENERIC_64_128(pick_nan_muladd, A)(A, B, C, S, ABM, ABCM) =20 +static void parts64_canonicalize(FloatParts64 *p, float_status *status, + const FloatFmt *fmt); +static void parts128_canonicalize(FloatParts128 *p, float_status *status, + const FloatFmt *fmt); + +#define parts_canonicalize(A, S, F) \ + PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -758,52 +766,85 @@ static int frac128_cmp(FloatParts128 *a, FloatParts12= 8 *b) =20 #define frac_cmp(A, B) FRAC_GENERIC_64_128(cmp, A)(A, B) =20 +static void frac64_clear(FloatParts64 *a) +{ + a->frac =3D 0; +} + +static void frac128_clear(FloatParts128 *a) +{ + a->frac_hi =3D a->frac_lo =3D 0; +} + +#define frac_clear(A) FRAC_GENERIC_64_128(clear, A)(A) + +static bool frac64_eqz(FloatParts64 *a) +{ + return a->frac =3D=3D 0; +} + +static bool frac128_eqz(FloatParts128 *a) +{ + return (a->frac_hi | a->frac_lo) =3D=3D 0; +} + +#define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A) + +static int frac64_normalize(FloatParts64 *a) +{ + if (a->frac) { + int shift =3D clz64(a->frac); + a->frac <<=3D shift; + return shift; + } + return 64; +} + +static int frac128_normalize(FloatParts128 *a) +{ + if (a->frac_hi) { + int shl =3D clz64(a->frac_hi); + if (shl) { + int shr =3D 64 - shl; + a->frac_hi =3D (a->frac_hi << shl) | (a->frac_lo >> shr); + a->frac_lo =3D (a->frac_lo << shl); + } + return shl; + } else if (a->frac_lo) { + int shl =3D clz64(a->frac_lo); + a->frac_hi =3D (a->frac_lo << shl); + a->frac_lo =3D 0; + return shl + 64; + } + return 128; +} + +#define frac_normalize(A) FRAC_GENERIC_64_128(normalize, A)(A) + +static void frac64_shl(FloatParts64 *a, int c) +{ + a->frac <<=3D c; +} + static void frac128_shl(FloatParts128 *a, int c) { shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); } =20 -#define frac_shl(A, C) frac128_shl(A, C) +#define frac_shl(A, C) FRAC_GENERIC_64_128(shl, A)(A, C) + +static void frac64_shr(FloatParts64 *a, int c) +{ + a->frac >>=3D c; +} =20 static void frac128_shr(FloatParts128 *a, int c) { shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); } =20 -#define frac_shr(A, C) frac128_shr(A, C) +#define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C) =20 -/* Canonicalize EXP and FRAC, setting CLS. */ -static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *par= m, - float_status *status) -{ - if (part.exp =3D=3D parm->exp_max && !parm->arm_althp) { - if (part.frac =3D=3D 0) { - part.cls =3D float_class_inf; - } else { - part.frac <<=3D parm->frac_shift; - part.cls =3D (parts_is_snan_frac(part.frac, status) - ? float_class_snan : float_class_qnan); - } - } else if (part.exp =3D=3D 0) { - if (likely(part.frac =3D=3D 0)) { - part.cls =3D float_class_zero; - } else if (status->flush_inputs_to_zero) { - float_raise(float_flag_input_denormal, status); - part.cls =3D float_class_zero; - part.frac =3D 0; - } else { - int shift =3D clz64(part.frac); - part.cls =3D float_class_normal; - part.exp =3D parm->frac_shift - parm->exp_bias - shift + 1; - part.frac <<=3D shift; - } - } else { - part.cls =3D float_class_normal; - part.exp -=3D parm->exp_bias; - part.frac =3D DECOMPOSED_IMPLICIT_BIT + (part.frac << parm->frac_s= hift); - } - return part; -} =20 /* Round and uncanonicalize a floating-point number by parts. There * are FRAC_SHIFT bits that may require rounding at the bottom of the @@ -983,7 +1024,7 @@ static void float16a_unpack_canonical(FloatParts64 *p,= float16 f, float_status *s, const FloatFmt *par= ams) { float16_unpack_raw(p, f); - *p =3D sf_canonicalize(*p, params, s); + parts_canonicalize(p, s, params); } =20 static void float16_unpack_canonical(FloatParts64 *p, float16 f, @@ -996,7 +1037,7 @@ static void bfloat16_unpack_canonical(FloatParts64 *p,= bfloat16 f, float_status *s) { bfloat16_unpack_raw(p, f); - *p =3D sf_canonicalize(*p, &bfloat16_params, s); + parts_canonicalize(p, s, &bfloat16_params); } =20 static float16 float16a_round_pack_canonical(FloatParts64 *p, @@ -1024,7 +1065,7 @@ static void float32_unpack_canonical(FloatParts64 *p,= float32 f, float_status *s) { float32_unpack_raw(p, f); - *p =3D sf_canonicalize(*p, &float32_params, s); + parts_canonicalize(p, s, &float32_params); } =20 static float32 float32_round_pack_canonical(FloatParts64 *p, @@ -1038,7 +1079,7 @@ static void float64_unpack_canonical(FloatParts64 *p,= float64 f, float_status *s) { float64_unpack_raw(p, f); - *p =3D sf_canonicalize(*p, &float64_params, s); + parts_canonicalize(p, s, &float64_params); } =20 static float64 float64_round_pack_canonical(FloatParts64 *p, diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a78d61ea07..25bf99bd0f 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -100,3 +100,36 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatParts= N *a, FloatPartsN *b, } return a; } + +/* + * Canonicalize the FloatParts structure. Determine the class, + * unbias the exponent, and normalize the fraction. + */ +static void partsN(canonicalize)(FloatPartsN *p, float_status *status, + const FloatFmt *fmt) +{ + if (unlikely(p->exp =3D=3D 0)) { + if (likely(frac_eqz(p))) { + p->cls =3D float_class_zero; + } else if (status->flush_inputs_to_zero) { + float_raise(float_flag_input_denormal, status); + p->cls =3D float_class_zero; + frac_clear(p); + } else { + int shift =3D frac_normalize(p); + p->cls =3D float_class_normal; + p->exp =3D fmt->frac_shift - fmt->exp_bias - shift + 1; + } + } else if (likely(p->exp < fmt->exp_max) || fmt->arm_althp) { + p->cls =3D float_class_normal; + p->exp -=3D fmt->exp_bias; + frac_shl(p, fmt->frac_shift); + p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + } else if (likely(frac_eqz(p))) { + p->cls =3D float_class_inf; + } else { + frac_shl(p, fmt->frac_shift); + p->cls =3D (parts_is_snan_frac(p->frac_hi, status) + ? float_class_snan : float_class_qnan); + } +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NGpOakjV0VOj6azWVGKzsBGpzQYOaN2R/8eKbyrZbMU=; b=czqD0PycV2Zr9w+Dq14CTUTIBlCnfQTXQh1jVUcvWX8Jprvx2yETzOFe/JnoGSxsmJ 8IzIWNUBxlPTj7evVB6ZPMKZLZoSugdzHnqr/3UTRbO/pln5VsJZjqTxjcWORKlf3Fus Sw1wqOYR0iIruj5fp0VEVLfIkIyz1XxotvDk6xkHewAfWNXkxPPN+YqRSVINbl7fNmf5 g/k3pClN+O+DCb5Of5a+iIGsVpsYClISpC3tdg9KIXOKgVa7GwOshnpmDMHGZO2rym4Y mKiCxY5JIAwkCW8hDdnXcQdi7QQSDS1d1SdHsh3WmF2yPnToV/2e1tuWek+MV07D1O+Z ba9Q== X-Gm-Message-State: AOAM530AVUiGjQ4DbnF/xUF8EbdpoaSCbz+3/ojfpxAJUkj2u8pyQe43 xrgH02BoI8anF6gx4mY7gPYIU5ybXrvSHw== X-Google-Smtp-Source: ABdhPJy79x5Ck4KQBUi4NCsimPpQL9jOLFJY2suXjkmqCiHxWtYUyAylUuXxkgkAiaqIHy8syQr+WA== X-Received: by 2002:a17:902:4d:b029:ec:94df:c9aa with SMTP id 71-20020a170902004db02900ec94dfc9aamr13263991pla.7.1620438504470; Fri, 07 May 2021 18:48:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 32/72] softfloat: Move round_canonical to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:22 -0700 Message-Id: <20210508014802.892561-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, convert to pointers, renaming to parts$N_uncanon, and define a macro for parts_uncanon using QEMU_GENERIC. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 201 +++++++++----------------------------- fpu/softfloat-parts.c.inc | 148 ++++++++++++++++++++++++++++ 2 files changed, 193 insertions(+), 156 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bad4b54cd2..e9d644385d 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -740,6 +740,14 @@ static void parts128_canonicalize(FloatParts128 *p, fl= oat_status *status, #define parts_canonicalize(A, S, F) \ PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) =20 +static void parts64_uncanon(FloatParts64 *p, float_status *status, + const FloatFmt *fmt); +static void parts128_uncanon(FloatParts128 *p, float_status *status, + const FloatFmt *fmt); + +#define parts_uncanon(A, S, F) \ + PARTS_GENERIC_64_128(uncanon, A)(A, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -747,6 +755,31 @@ static void parts128_canonicalize(FloatParts128 *p, fl= oat_status *status, #define FRAC_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) =20 +static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c) +{ + return uadd64_overflow(a->frac, c, &r->frac); +} + +static bool frac128_addi(FloatParts128 *r, FloatParts128 *a, uint64_t c) +{ + c =3D uadd64_overflow(a->frac_lo, c, &r->frac_lo); + return uadd64_overflow(a->frac_hi, c, &r->frac_hi); +} + +#define frac_addi(R, A, C) FRAC_GENERIC_64_128(addi, R)(R, A, C) + +static void frac64_allones(FloatParts64 *a) +{ + a->frac =3D -1; +} + +static void frac128_allones(FloatParts128 *a) +{ + a->frac_hi =3D a->frac_lo =3D -1; +} + +#define frac_allones(A) FRAC_GENERIC_64_128(allones, A)(A) + static int frac64_cmp(FloatParts64 *a, FloatParts64 *b) { return a->frac =3D=3D b->frac ? 0 : a->frac < b->frac ? -1 : 1; @@ -845,161 +878,17 @@ static void frac128_shr(FloatParts128 *a, int c) =20 #define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C) =20 - -/* Round and uncanonicalize a floating-point number by parts. There - * are FRAC_SHIFT bits that may require rounding at the bottom of the - * fraction; these bits will be removed. The exponent will be biased - * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. - */ - -static FloatParts64 round_canonical(FloatParts64 p, float_status *s, - const FloatFmt *parm) +static void frac64_shrjam(FloatParts64 *a, int c) { - const uint64_t frac_lsb =3D parm->frac_lsb; - const uint64_t frac_lsbm1 =3D parm->frac_lsbm1; - const uint64_t round_mask =3D parm->round_mask; - const uint64_t roundeven_mask =3D parm->roundeven_mask; - const int exp_max =3D parm->exp_max; - const int frac_shift =3D parm->frac_shift; - uint64_t frac, inc; - int exp, flags =3D 0; - bool overflow_norm; - - frac =3D p.frac; - exp =3D p.exp; - - switch (p.cls) { - case float_class_normal: - switch (s->float_rounding_mode) { - case float_round_nearest_even: - overflow_norm =3D false; - inc =3D ((frac & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm1 = : 0); - break; - case float_round_ties_away: - overflow_norm =3D false; - inc =3D frac_lsbm1; - break; - case float_round_to_zero: - overflow_norm =3D true; - inc =3D 0; - break; - case float_round_up: - inc =3D p.sign ? 0 : round_mask; - overflow_norm =3D p.sign; - break; - case float_round_down: - inc =3D p.sign ? round_mask : 0; - overflow_norm =3D !p.sign; - break; - case float_round_to_odd: - overflow_norm =3D true; - inc =3D frac & frac_lsb ? 0 : round_mask; - break; - default: - g_assert_not_reached(); - } - - exp +=3D parm->exp_bias; - if (likely(exp > 0)) { - if (frac & round_mask) { - flags |=3D float_flag_inexact; - if (uadd64_overflow(frac, inc, &frac)) { - frac =3D (frac >> 1) | DECOMPOSED_IMPLICIT_BIT; - exp++; - } - } - frac >>=3D frac_shift; - - if (parm->arm_althp) { - /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ - if (unlikely(exp > exp_max)) { - /* Overflow. Return the maximum normal. */ - flags =3D float_flag_invalid; - exp =3D exp_max; - frac =3D -1; - } - } else if (unlikely(exp >=3D exp_max)) { - flags |=3D float_flag_overflow | float_flag_inexact; - if (overflow_norm) { - exp =3D exp_max - 1; - frac =3D -1; - } else { - p.cls =3D float_class_inf; - goto do_inf; - } - } - } else if (s->flush_to_zero) { - flags |=3D float_flag_output_denormal; - p.cls =3D float_class_zero; - goto do_zero; - } else { - bool is_tiny =3D s->tininess_before_rounding || (exp < 0); - - if (!is_tiny) { - uint64_t discard; - is_tiny =3D !uadd64_overflow(frac, inc, &discard); - } - - shift64RightJamming(frac, 1 - exp, &frac); - if (frac & round_mask) { - /* Need to recompute round-to-even. */ - switch (s->float_rounding_mode) { - case float_round_nearest_even: - inc =3D ((frac & roundeven_mask) !=3D frac_lsbm1 - ? frac_lsbm1 : 0); - break; - case float_round_to_odd: - inc =3D frac & frac_lsb ? 0 : round_mask; - break; - default: - break; - } - flags |=3D float_flag_inexact; - frac +=3D inc; - } - - exp =3D (frac & DECOMPOSED_IMPLICIT_BIT ? 1 : 0); - frac >>=3D frac_shift; - - if (is_tiny && (flags & float_flag_inexact)) { - flags |=3D float_flag_underflow; - } - if (exp =3D=3D 0 && frac =3D=3D 0) { - p.cls =3D float_class_zero; - } - } - break; - - case float_class_zero: - do_zero: - exp =3D 0; - frac =3D 0; - break; - - case float_class_inf: - do_inf: - assert(!parm->arm_althp); - exp =3D exp_max; - frac =3D 0; - break; - - case float_class_qnan: - case float_class_snan: - assert(!parm->arm_althp); - exp =3D exp_max; - frac >>=3D parm->frac_shift; - break; - - default: - g_assert_not_reached(); - } - - float_raise(flags, s); - p.exp =3D exp; - p.frac =3D frac; - return p; + shift64RightJamming(a->frac, c, &a->frac); } =20 +static void frac128_shrjam(FloatParts128 *a, int c) +{ + shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_= lo); +} + +#define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C) =20 #define partsN(NAME) parts64_##NAME #define FloatPartsN FloatParts64 @@ -1044,7 +933,7 @@ static float16 float16a_round_pack_canonical(FloatPart= s64 *p, float_status *s, const FloatFmt *params) { - *p =3D round_canonical(*p, s, params); + parts_uncanon(p, s, params); return float16_pack_raw(p); } =20 @@ -1057,7 +946,7 @@ static float16 float16_round_pack_canonical(FloatParts= 64 *p, static bfloat16 bfloat16_round_pack_canonical(FloatParts64 *p, float_status *s) { - *p =3D round_canonical(*p, s, &bfloat16_params); + parts_uncanon(p, s, &bfloat16_params); return bfloat16_pack_raw(p); } =20 @@ -1071,7 +960,7 @@ static void float32_unpack_canonical(FloatParts64 *p, = float32 f, static float32 float32_round_pack_canonical(FloatParts64 *p, float_status *s) { - *p =3D round_canonical(*p, s, &float32_params); + parts_uncanon(p, s, &float32_params); return float32_pack_raw(p); } =20 @@ -1085,7 +974,7 @@ static void float64_unpack_canonical(FloatParts64 *p, = float64 f, static float64 float64_round_pack_canonical(FloatParts64 *p, float_status *s) { - *p =3D round_canonical(*p, s, &float64_params); + parts_uncanon(p, s, &float64_params); return float64_pack_raw(p); } =20 diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 25bf99bd0f..efdc724770 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -133,3 +133,151 @@ static void partsN(canonicalize)(FloatPartsN *p, floa= t_status *status, ? float_class_snan : float_class_qnan); } } + +/* + * Round and uncanonicalize a floating-point number by parts. There + * are FRAC_SHIFT bits that may require rounding at the bottom of the + * fraction; these bits will be removed. The exponent will be biased + * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. + */ +static void partsN(uncanon)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) +{ + const int exp_max =3D fmt->exp_max; + const int frac_shift =3D fmt->frac_shift; + const uint64_t frac_lsb =3D fmt->frac_lsb; + const uint64_t frac_lsbm1 =3D fmt->frac_lsbm1; + const uint64_t round_mask =3D fmt->round_mask; + const uint64_t roundeven_mask =3D fmt->roundeven_mask; + uint64_t inc; + bool overflow_norm; + int exp, flags =3D 0; + + if (unlikely(p->cls !=3D float_class_normal)) { + switch (p->cls) { + case float_class_zero: + p->exp =3D 0; + frac_clear(p); + return; + case float_class_inf: + g_assert(!fmt->arm_althp); + p->exp =3D fmt->exp_max; + frac_clear(p); + return; + case float_class_qnan: + case float_class_snan: + g_assert(!fmt->arm_althp); + p->exp =3D fmt->exp_max; + frac_shr(p, fmt->frac_shift); + return; + default: + break; + } + g_assert_not_reached(); + } + + switch (s->float_rounding_mode) { + case float_round_nearest_even: + overflow_norm =3D false; + inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm= 1 : 0); + break; + case float_round_ties_away: + overflow_norm =3D false; + inc =3D frac_lsbm1; + break; + case float_round_to_zero: + overflow_norm =3D true; + inc =3D 0; + break; + case float_round_up: + inc =3D p->sign ? 0 : round_mask; + overflow_norm =3D p->sign; + break; + case float_round_down: + inc =3D p->sign ? round_mask : 0; + overflow_norm =3D !p->sign; + break; + case float_round_to_odd: + overflow_norm =3D true; + inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; + break; + default: + g_assert_not_reached(); + } + + exp =3D p->exp + fmt->exp_bias; + if (likely(exp > 0)) { + if (p->frac_lo & round_mask) { + flags |=3D float_flag_inexact; + if (frac_addi(p, p, inc)) { + frac_shr(p, 1); + p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + exp++; + } + } + frac_shr(p, frac_shift); + + if (fmt->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags =3D float_flag_invalid; + exp =3D exp_max; + frac_allones(p); + } + } else if (unlikely(exp >=3D exp_max)) { + flags |=3D float_flag_overflow | float_flag_inexact; + if (overflow_norm) { + exp =3D exp_max - 1; + frac_allones(p); + } else { + p->cls =3D float_class_inf; + exp =3D exp_max; + frac_clear(p); + } + } + } else if (s->flush_to_zero) { + flags |=3D float_flag_output_denormal; + p->cls =3D float_class_zero; + exp =3D 0; + frac_clear(p); + } else { + bool is_tiny =3D s->tininess_before_rounding || exp < 0; + + if (!is_tiny) { + FloatPartsN discard; + is_tiny =3D !frac_addi(&discard, p, inc); + } + + frac_shrjam(p, 1 - exp); + + if (p->frac_lo & round_mask) { + /* Need to recompute round-to-even/round-to-odd. */ + switch (s->float_rounding_mode) { + case float_round_nearest_even: + inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 + ? frac_lsbm1 : 0); + break; + case float_round_to_odd: + inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; + break; + default: + break; + } + flags |=3D float_flag_inexact; + frac_addi(p, p, inc); + } + + exp =3D (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) !=3D 0; + frac_shr(p, frac_shift); + + if (is_tiny && (flags & float_flag_inexact)) { + flags |=3D float_flag_underflow; + } + if (exp =3D=3D 0 && frac_eqz(p)) { + p->cls =3D float_class_zero; + } + } + p->exp =3D exp; + float_raise(flags, s); +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440301; cv=none; d=zohomail.com; s=zohoarc; b=OKkL9ym9Si+4BaYKbQjEkHFIf/eBj+eBi+vYIvOQNV59CS11M939W3iQVxqEw/xf1R6aGV9SG+1RFSQ20XwED2IEHrGeVH7igOq1MJp0xaDxwMut2eHGHSA9M9xNqAKy3N+bGCHNOFajx19cj+sRUiTkJWhXUqMMEzYNjNevMDM= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 33/72] softfloat: Use uadd64_carry, usub64_borrow in softfloat-macros.h Date: Fri, 7 May 2021 18:47:23 -0700 Message-Id: <20210508014802.892561-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use compiler support for carry arithmetic. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/fpu/softfloat-macros.h | 95 +++++++++------------------------- 1 file changed, 25 insertions(+), 70 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index a35ec2893a..2e3760a9c1 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -83,6 +83,7 @@ this code that are retained. #define FPU_SOFTFLOAT_MACROS_H =20 #include "fpu/softfloat-types.h" +#include "qemu/host-utils.h" =20 /*------------------------------------------------------------------------= ---- | Shifts `a' right by the number of bits given in `count'. If any nonzero @@ -403,16 +404,12 @@ static inline void | are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. *-------------------------------------------------------------------------= ---*/ =20 -static inline void - add128( - uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, = uint64_t *z1Ptr ) +static inline void add128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t = b1, + uint64_t *z0Ptr, uint64_t *z1Ptr) { - uint64_t z1; - - z1 =3D a1 + b1; - *z1Ptr =3D z1; - *z0Ptr =3D a0 + b0 + ( z1 < a1 ); - + bool c =3D 0; + *z1Ptr =3D uadd64_carry(a1, b1, &c); + *z0Ptr =3D uadd64_carry(a0, b0, &c); } =20 /*------------------------------------------------------------------------= ---- @@ -423,34 +420,14 @@ static inline void | `z1Ptr', and `z2Ptr'. *-------------------------------------------------------------------------= ---*/ =20 -static inline void - add192( - uint64_t a0, - uint64_t a1, - uint64_t a2, - uint64_t b0, - uint64_t b1, - uint64_t b2, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr - ) +static inline void add192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2, + uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Pt= r) { - uint64_t z0, z1, z2; - int8_t carry0, carry1; - - z2 =3D a2 + b2; - carry1 =3D ( z2 < a2 ); - z1 =3D a1 + b1; - carry0 =3D ( z1 < a1 ); - z0 =3D a0 + b0; - z1 +=3D carry1; - z0 +=3D ( z1 < carry1 ); - z0 +=3D carry0; - *z2Ptr =3D z2; - *z1Ptr =3D z1; - *z0Ptr =3D z0; - + bool c =3D 0; + *z2Ptr =3D uadd64_carry(a2, b2, &c); + *z1Ptr =3D uadd64_carry(a1, b1, &c); + *z0Ptr =3D uadd64_carry(a0, b0, &c); } =20 /*------------------------------------------------------------------------= ---- @@ -461,14 +438,12 @@ static inline void | `z1Ptr'. *-------------------------------------------------------------------------= ---*/ =20 -static inline void - sub128( - uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, = uint64_t *z1Ptr ) +static inline void sub128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t = b1, + uint64_t *z0Ptr, uint64_t *z1Ptr) { - - *z1Ptr =3D a1 - b1; - *z0Ptr =3D a0 - b0 - ( a1 < b1 ); - + bool c =3D 0; + *z1Ptr =3D usub64_borrow(a1, b1, &c); + *z0Ptr =3D usub64_borrow(a0, b0, &c); } =20 /*------------------------------------------------------------------------= ---- @@ -479,34 +454,14 @@ static inline void | pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'. *-------------------------------------------------------------------------= ---*/ =20 -static inline void - sub192( - uint64_t a0, - uint64_t a1, - uint64_t a2, - uint64_t b0, - uint64_t b1, - uint64_t b2, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr - ) +static inline void sub192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2, + uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Pt= r) { - uint64_t z0, z1, z2; - int8_t borrow0, borrow1; - - z2 =3D a2 - b2; - borrow1 =3D ( a2 < b2 ); - z1 =3D a1 - b1; - borrow0 =3D ( a1 < b1 ); - z0 =3D a0 - b0; - z0 -=3D ( z1 < borrow1 ); - z1 -=3D borrow1; - z0 -=3D borrow0; - *z2Ptr =3D z2; - *z1Ptr =3D z1; - *z0Ptr =3D z0; - + bool c =3D 0; + *z2Ptr =3D usub64_borrow(a2, b2, &c); + *z1Ptr =3D usub64_borrow(a1, b1, &c); + *z0Ptr =3D usub64_borrow(a0, b0, &c); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440577; cv=none; d=zohomail.com; s=zohoarc; b=NGenJ3Rjr1lommWl1A/FToWAh1ec1AmDd9rKrb0Q9pm1oD4dWrMjvUfQ53E2tPCcs7ZTHFLFXBbjO74SyQoQUyZRU+dm/tvx+PIMZuk+fyY0hkJNwTP6IjzvdXA8/1DmDyEjTSMIXs6cnEledA94GRzFsaShz8QTlCiMZvQpQjM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TWZr2C9rW9e8Gm21aL9j9NpbBIgKRrAvWFSjjtP/7/E=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In preparation for implementing multiple sizes. Rename to parts_addsub, split out parts_add/sub_normal for future reuse with muladd. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 253 ++++++++++++++----------------- fpu/softfloat-parts-addsub.c.inc | 62 ++++++++ fpu/softfloat-parts.c.inc | 81 ++++++++++ 3 files changed, 255 insertions(+), 141 deletions(-) create mode 100644 fpu/softfloat-parts-addsub.c.inc diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e9d644385d..22dc6da5ef 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -748,6 +748,26 @@ static void parts128_uncanon(FloatParts128 *p, float_s= tatus *status, #define parts_uncanon(A, S, F) \ PARTS_GENERIC_64_128(uncanon, A)(A, S, F) =20 +static void parts64_add_normal(FloatParts64 *a, FloatParts64 *b); +static void parts128_add_normal(FloatParts128 *a, FloatParts128 *b); + +#define parts_add_normal(A, B) \ + PARTS_GENERIC_64_128(add_normal, A)(A, B) + +static bool parts64_sub_normal(FloatParts64 *a, FloatParts64 *b); +static bool parts128_sub_normal(FloatParts128 *a, FloatParts128 *b); + +#define parts_sub_normal(A, B) \ + PARTS_GENERIC_64_128(sub_normal, A)(A, B) + +static FloatParts64 *parts64_addsub(FloatParts64 *a, FloatParts64 *b, + float_status *s, bool subtract); +static FloatParts128 *parts128_addsub(FloatParts128 *a, FloatParts128 *b, + float_status *s, bool subtract); + +#define parts_addsub(A, B, S, Z) \ + PARTS_GENERIC_64_128(addsub, A)(A, B, S, Z) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -755,6 +775,21 @@ static void parts128_uncanon(FloatParts128 *p, float_s= tatus *status, #define FRAC_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) =20 +static bool frac64_add(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) +{ + return uadd64_overflow(a->frac, b->frac, &r->frac); +} + +static bool frac128_add(FloatParts128 *r, FloatParts128 *a, FloatParts128 = *b) +{ + bool c =3D 0; + r->frac_lo =3D uadd64_carry(a->frac_lo, b->frac_lo, &c); + r->frac_hi =3D uadd64_carry(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_add(R, A, B) FRAC_GENERIC_64_128(add, R)(R, A, B) + static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c) { return uadd64_overflow(a->frac, c, &r->frac); @@ -823,6 +858,20 @@ static bool frac128_eqz(FloatParts128 *a) =20 #define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A) =20 +static void frac64_neg(FloatParts64 *a) +{ + a->frac =3D -a->frac; +} + +static void frac128_neg(FloatParts128 *a) +{ + bool c =3D 0; + a->frac_lo =3D usub64_borrow(0, a->frac_lo, &c); + a->frac_hi =3D usub64_borrow(0, a->frac_hi, &c); +} + +#define frac_neg(A) FRAC_GENERIC_64_128(neg, A)(A) + static int frac64_normalize(FloatParts64 *a) { if (a->frac) { @@ -890,18 +939,36 @@ static void frac128_shrjam(FloatParts128 *a, int c) =20 #define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C) =20 -#define partsN(NAME) parts64_##NAME -#define FloatPartsN FloatParts64 +static bool frac64_sub(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) +{ + return usub64_overflow(a->frac, b->frac, &r->frac); +} =20 +static bool frac128_sub(FloatParts128 *r, FloatParts128 *a, FloatParts128 = *b) +{ + bool c =3D 0; + r->frac_lo =3D usub64_borrow(a->frac_lo, b->frac_lo, &c); + r->frac_hi =3D usub64_borrow(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B) + +#define partsN(NAME) glue(glue(glue(parts,N),_),NAME) +#define FloatPartsN glue(FloatParts,N) + +#define N 64 + +#include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" =20 -#undef partsN -#undef FloatPartsN -#define partsN(NAME) parts128_##NAME -#define FloatPartsN FloatParts128 +#undef N +#define N 128 =20 +#include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" =20 +#undef N #undef partsN #undef FloatPartsN =20 @@ -979,165 +1046,73 @@ static float64 float64_round_pack_canonical(FloatPa= rts64 *p, } =20 /* - * Returns the result of adding or subtracting the values of the - * floating-point values `a' and `b'. The operation is performed - * according to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic. + * Addition and subtraction */ =20 -static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool sub= tract, - float_status *s) +static float16 QEMU_FLATTEN +float16_addsub(float16 a, float16 b, float_status *status, bool subtract) { - bool a_sign =3D a.sign; - bool b_sign =3D b.sign ^ subtract; - - if (a_sign !=3D b_sign) { - /* Subtraction */ - - if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_no= rmal) { - if (a.exp > b.exp || (a.exp =3D=3D b.exp && a.frac >=3D b.frac= )) { - shift64RightJamming(b.frac, a.exp - b.exp, &b.frac); - a.frac =3D a.frac - b.frac; - } else { - shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); - a.frac =3D b.frac - a.frac; - a.exp =3D b.exp; - a_sign ^=3D 1; - } - - if (a.frac =3D=3D 0) { - a.cls =3D float_class_zero; - a.sign =3D s->float_rounding_mode =3D=3D float_round_down; - } else { - int shift =3D clz64(a.frac); - a.frac =3D a.frac << shift; - a.exp =3D a.exp - shift; - a.sign =3D a_sign; - } - return a; - } - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - if (a.cls =3D=3D float_class_inf) { - if (b.cls =3D=3D float_class_inf) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - } - return a; - } - if (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_zero= ) { - a.sign =3D s->float_rounding_mode =3D=3D float_round_down; - return a; - } - if (a.cls =3D=3D float_class_zero || b.cls =3D=3D float_class_inf)= { - b.sign =3D a_sign ^ 1; - return b; - } - if (b.cls =3D=3D float_class_zero) { - return a; - } - } else { - /* Addition */ - if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_no= rmal) { - if (a.exp > b.exp) { - shift64RightJamming(b.frac, a.exp - b.exp, &b.frac); - } else if (a.exp < b.exp) { - shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); - a.exp =3D b.exp; - } - - if (uadd64_overflow(a.frac, b.frac, &a.frac)) { - shift64RightJamming(a.frac, 1, &a.frac); - a.frac |=3D DECOMPOSED_IMPLICIT_BIT; - a.exp +=3D 1; - } - return a; - } - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - if (a.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_zero)= { - return a; - } - if (b.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)= { - b.sign =3D b_sign; - return b; - } - } - g_assert_not_reached(); -} - -/* - * Returns the result of adding or subtracting the floating-point - * values `a' and `b'. The operation is performed according to the - * IEC/IEEE Standard for Binary Floating-Point Arithmetic. - */ - -float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *statu= s) -{ - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); - pr =3D addsub_floats(pa, pb, false, status); + pr =3D parts_addsub(&pa, &pb, status, subtract); =20 - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } =20 -float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *statu= s) +float16 float16_add(float16 a, float16 b, float_status *status) { - FloatParts64 pa, pb, pr; + return float16_addsub(a, b, status, false); +} =20 - float16_unpack_canonical(&pa, a, status); - float16_unpack_canonical(&pb, b, status); - pr =3D addsub_floats(pa, pb, true, status); - - return float16_round_pack_canonical(&pr, status); +float16 float16_sub(float16 a, float16 b, float_status *status) +{ + return float16_addsub(a, b, status, true); } =20 static float32 QEMU_SOFTFLOAT_ATTR -soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) +soft_f32_addsub(float32 a, float32 b, float_status *status, bool subtract) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); - pr =3D addsub_floats(pa, pb, subtract, status); + pr =3D parts_addsub(&pa, &pb, status, subtract); =20 - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } =20 -static inline float32 soft_f32_add(float32 a, float32 b, float_status *sta= tus) +static float32 soft_f32_add(float32 a, float32 b, float_status *status) { - return soft_f32_addsub(a, b, false, status); + return soft_f32_addsub(a, b, status, false); } =20 -static inline float32 soft_f32_sub(float32 a, float32 b, float_status *sta= tus) +static float32 soft_f32_sub(float32 a, float32 b, float_status *status) { - return soft_f32_addsub(a, b, true, status); + return soft_f32_addsub(a, b, status, true); } =20 static float64 QEMU_SOFTFLOAT_ATTR -soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) +soft_f64_addsub(float64 a, float64 b, float_status *status, bool subtract) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); - pr =3D addsub_floats(pa, pb, subtract, status); + pr =3D parts_addsub(&pa, &pb, status, subtract); =20 - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } =20 -static inline float64 soft_f64_add(float64 a, float64 b, float_status *sta= tus) +static float64 soft_f64_add(float64 a, float64 b, float_status *status) { - return soft_f64_addsub(a, b, false, status); + return soft_f64_addsub(a, b, status, false); } =20 -static inline float64 soft_f64_sub(float64 a, float64 b, float_status *sta= tus) +static float64 soft_f64_sub(float64 a, float64 b, float_status *status) { - return soft_f64_addsub(a, b, true, status); + return soft_f64_addsub(a, b, status, true); } =20 static float hard_f32_add(float a, float b) @@ -1215,30 +1190,26 @@ float64_sub(float64 a, float64 b, float_status *s) return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub); } =20 -/* - * Returns the result of adding or subtracting the bfloat16 - * values `a' and `b'. - */ -bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *s= tatus) +static bfloat16 QEMU_FLATTEN +bfloat16_addsub(bfloat16 a, bfloat16 b, float_status *status, bool subtrac= t) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); - pr =3D addsub_floats(pa, pb, false, status); + pr =3D parts_addsub(&pa, &pb, status, subtract); =20 - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); } =20 -bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *s= tatus) +bfloat16 bfloat16_add(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa, pb, pr; + return bfloat16_addsub(a, b, status, false); +} =20 - bfloat16_unpack_canonical(&pa, a, status); - bfloat16_unpack_canonical(&pb, b, status); - pr =3D addsub_floats(pa, pb, true, status); - - return bfloat16_round_pack_canonical(&pr, status); +bfloat16 bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) +{ + return bfloat16_addsub(a, b, status, true); } =20 /* diff --git a/fpu/softfloat-parts-addsub.c.inc b/fpu/softfloat-parts-addsub.= c.inc new file mode 100644 index 0000000000..ae5c1017c5 --- /dev/null +++ b/fpu/softfloat-parts-addsub.c.inc @@ -0,0 +1,62 @@ +/* + * Floating point arithmetic implementation + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed = below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file after December 1st 2014 will be + * taken to be licensed under the Softfloat-2a license unless specifically + * indicated otherwise. + */ + +static void partsN(add_normal)(FloatPartsN *a, FloatPartsN *b) +{ + int exp_diff =3D a->exp - b->exp; + + if (exp_diff > 0) { + frac_shrjam(b, exp_diff); + } else if (exp_diff < 0) { + frac_shrjam(a, -exp_diff); + a->exp =3D b->exp; + } + + if (frac_add(a, a, b)) { + frac_shrjam(a, 1); + a->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + a->exp +=3D 1; + } +} + +static bool partsN(sub_normal)(FloatPartsN *a, FloatPartsN *b) +{ + int exp_diff =3D a->exp - b->exp; + int shift; + + if (exp_diff > 0) { + frac_shrjam(b, exp_diff); + frac_sub(a, a, b); + } else if (exp_diff < 0) { + a->exp =3D b->exp; + a->sign ^=3D 1; + frac_shrjam(a, -exp_diff); + frac_sub(a, b, a); + } else if (frac_sub(a, a, b)) { + /* Overflow means that A was less than B. */ + frac_neg(a); + a->sign ^=3D 1; + } + + shift =3D frac_normalize(a); + if (likely(shift < N)) { + a->exp -=3D shift; + return true; + } + a->cls =3D float_class_zero; + return false; +} diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index efdc724770..cfce9f6421 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -281,3 +281,84 @@ static void partsN(uncanon)(FloatPartsN *p, float_stat= us *s, p->exp =3D exp; float_raise(flags, s); } + +/* + * Returns the result of adding or subtracting the values of the + * floating-point values `a' and `b'. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + */ +static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b, + float_status *s, bool subtract) +{ + bool b_sign =3D b->sign ^ subtract; + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + + if (a->sign !=3D b_sign) { + /* Subtraction */ + if (likely(ab_mask =3D=3D float_cmask_normal)) { + if (parts_sub_normal(a, b)) { + return a; + } + /* Subtract was exact, fall through to set sign. */ + ab_mask =3D float_cmask_zero; + } + + if (ab_mask =3D=3D float_cmask_zero) { + a->sign =3D s->float_rounding_mode =3D=3D float_round_down; + return a; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + goto p_nan; + } + + if (ab_mask & float_cmask_inf) { + if (a->cls !=3D float_class_inf) { + /* N - Inf */ + goto return_b; + } + if (b->cls !=3D float_class_inf) { + /* Inf - N */ + return a; + } + /* Inf - Inf */ + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + } else { + /* Addition */ + if (likely(ab_mask =3D=3D float_cmask_normal)) { + parts_add_normal(a, b); + return a; + } + + if (ab_mask =3D=3D float_cmask_zero) { + return a; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + goto p_nan; + } + + if (ab_mask & float_cmask_inf) { + a->cls =3D float_class_inf; + return a; + } + } + + if (b->cls =3D=3D float_class_zero) { + g_assert(a->cls =3D=3D float_class_normal); + return a; + } + + g_assert(a->cls =3D=3D float_class_zero); + g_assert(b->cls =3D=3D float_class_normal); + return_b: + b->sign =3D b_sign; + return b; + + p_nan: + return parts_pick_nan(a, b, s); +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Fri, 07 May 2021 18:48:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 35/72] softfloat: Implement float128_add/sub via parts Date: Fri, 7 May 2021 18:47:25 -0700 Message-Id: <20210508014802.892561-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Replace the existing Berkeley implementation with the FloatParts implementation. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 257 +++++++----------------------------------------- 1 file changed, 36 insertions(+), 221 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 22dc6da5ef..f48e6b1f64 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1045,6 +1045,20 @@ static float64 float64_round_pack_canonical(FloatPar= ts64 *p, return float64_pack_raw(p); } =20 +static void float128_unpack_canonical(FloatParts128 *p, float128 f, + float_status *s) +{ + float128_unpack_raw(p, f); + parts_canonicalize(p, s, &float128_params); +} + +static float128 float128_round_pack_canonical(FloatParts128 *p, + float_status *s) +{ + parts_uncanon(p, s, &float128_params); + return float128_pack_raw(p); +} + /* * Addition and subtraction */ @@ -1212,6 +1226,28 @@ bfloat16 bfloat16_sub(bfloat16 a, bfloat16 b, float_= status *status) return bfloat16_addsub(a, b, status, true); } =20 +static float128 QEMU_FLATTEN +float128_addsub(float128 a, float128 b, float_status *status, bool subtrac= t) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr =3D parts_addsub(&pa, &pb, status, subtract); + + return float128_round_pack_canonical(pr, status); +} + +float128 float128_add(float128 a, float128 b, float_status *status) +{ + return float128_addsub(a, b, status, false); +} + +float128 float128_sub(float128 a, float128 b, float_status *status) +{ + return float128_addsub(a, b, status, true); +} + /* * Returns the result of multiplying the floating-point values `a' and * `b'. The operation is performed according to the IEC/IEEE Standard @@ -7031,227 +7067,6 @@ float128 float128_round_to_int(float128 a, float_st= atus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the absolute values of the quadruple-precis= ion -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float128 addFloat128Sigs(float128 a, float128 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2; - int32_t expDiff; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - bSig1 =3D extractFloat128Frac1( b ); - bSig0 =3D extractFloat128Frac0( b ); - bExp =3D extractFloat128Exp( b ); - expDiff =3D aExp - bExp; - if ( 0 < expDiff ) { - if ( aExp =3D=3D 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - --expDiff; - } - else { - bSig0 |=3D UINT64_C(0x0001000000000000); - } - shift128ExtraRightJamming( - bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 ); - zExp =3D aExp; - } - else if ( expDiff < 0 ) { - if ( bExp =3D=3D 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( aExp =3D=3D 0 ) { - ++expDiff; - } - else { - aSig0 |=3D UINT64_C(0x0001000000000000); - } - shift128ExtraRightJamming( - aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 ); - zExp =3D bExp; - } - else { - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig0 | aSig1 | bSig0 | bSig1 ) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - if ( aExp =3D=3D 0 ) { - if (status->flush_to_zero) { - if (zSig0 | zSig1) { - float_raise(float_flag_output_denormal, status); - } - return packFloat128(zSign, 0, 0, 0); - } - return packFloat128( zSign, 0, zSig0, zSig1 ); - } - zSig2 =3D 0; - zSig0 |=3D UINT64_C(0x0002000000000000); - zExp =3D aExp; - goto shiftRight1; - } - aSig0 |=3D UINT64_C(0x0001000000000000); - add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - --zExp; - if ( zSig0 < UINT64_C(0x0002000000000000) ) goto roundAndPack; - ++zExp; - shiftRight1: - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 ); - roundAndPack: - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the absolute values of the quadruple- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static float128 subFloat128Sigs(float128 a, float128 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1; - int32_t expDiff; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - bSig1 =3D extractFloat128Frac1( b ); - bSig0 =3D extractFloat128Frac0( b ); - bExp =3D extractFloat128Exp( b ); - expDiff =3D aExp - bExp; - shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 ); - shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 ); - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig0 | aSig1 | bSig0 | bSig1 ) { - return propagateFloat128NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - aExp =3D 1; - bExp =3D 1; - } - if ( bSig0 < aSig0 ) goto aBigger; - if ( aSig0 < bSig0 ) goto bBigger; - if ( bSig1 < aSig1 ) goto aBigger; - if ( aSig1 < bSig1 ) goto bBigger; - return packFloat128(status->float_rounding_mode =3D=3D float_round_dow= n, - 0, 0, 0); - bExpBigger: - if ( bExp =3D=3D 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 ); - } - if ( aExp =3D=3D 0 ) { - ++expDiff; - } - else { - aSig0 |=3D UINT64_C(0x4000000000000000); - } - shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 ); - bSig0 |=3D UINT64_C(0x4000000000000000); - bBigger: - sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 ); - zExp =3D bExp; - zSign ^=3D 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp =3D=3D 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - --expDiff; - } - else { - bSig0 |=3D UINT64_C(0x4000000000000000); - } - shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 ); - aSig0 |=3D UINT64_C(0x4000000000000000); - aBigger: - sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - zExp =3D aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat128(zSign, zExp - 14, zSig0, zSig1, - status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the quadruple-precision floating-point valu= es -| `a' and `b'. The operation is performed according to the IEC/IEEE Stand= ard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_add(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign; - - aSign =3D extractFloat128Sign( a ); - bSign =3D extractFloat128Sign( b ); - if ( aSign =3D=3D bSign ) { - return addFloat128Sigs(a, b, aSign, status); - } - else { - return subFloat128Sigs(a, b, aSign, status); - } - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the quadruple-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_sub(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign; - - aSign =3D extractFloat128Sign( a ); - bSign =3D extractFloat128Sign( b ); - if ( aSign =3D=3D bSign ) { - return subFloat128Sigs(a, b, aSign, status); - } - else { - return addFloat128Sigs(a, b, aSign, status); - } - -} - /*------------------------------------------------------------------------= ---- | Returns the result of multiplying the quadruple-precision floating-point | values `a' and `b'. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_mul. Reimplement float128_mul with FloatParts128. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 206 ++++++++++++++------------------------ fpu/softfloat-parts.c.inc | 51 ++++++++++ 2 files changed, 128 insertions(+), 129 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f48e6b1f64..4f498c11e5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -532,6 +532,16 @@ typedef struct { uint64_t frac_lo; } FloatParts128; =20 +typedef struct { + FloatClass cls; + bool sign; + int32_t exp; + uint64_t frac_hi; + uint64_t frac_hm; /* high-middle */ + uint64_t frac_lm; /* low-middle */ + uint64_t frac_lo; +} FloatParts256; + /* These apply to the most significant word of each FloatPartsN. */ #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) @@ -768,6 +778,14 @@ static FloatParts128 *parts128_addsub(FloatParts128 *a= , FloatParts128 *b, #define parts_addsub(A, B, S, Z) \ PARTS_GENERIC_64_128(addsub, A)(A, B, S, Z) =20 +static FloatParts64 *parts64_mul(FloatParts64 *a, FloatParts64 *b, + float_status *s); +static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b, + float_status *s); + +#define parts_mul(A, B, S) \ + PARTS_GENERIC_64_128(mul, A)(A, B, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -858,6 +876,19 @@ static bool frac128_eqz(FloatParts128 *a) =20 #define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A) =20 +static void frac64_mulw(FloatParts128 *r, FloatParts64 *a, FloatParts64 *b) +{ + mulu64(&r->frac_lo, &r->frac_hi, a->frac, b->frac); +} + +static void frac128_mulw(FloatParts256 *r, FloatParts128 *a, FloatParts128= *b) +{ + mul128To256(a->frac_hi, a->frac_lo, b->frac_hi, b->frac_lo, + &r->frac_hi, &r->frac_hm, &r->frac_lm, &r->frac_lo); +} + +#define frac_mulw(R, A, B) FRAC_GENERIC_64_128(mulw, A)(R, A, B) + static void frac64_neg(FloatParts64 *a) { a->frac =3D -a->frac; @@ -954,23 +985,42 @@ static bool frac128_sub(FloatParts128 *r, FloatParts1= 28 *a, FloatParts128 *b) =20 #define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B) =20 +static void frac64_truncjam(FloatParts64 *r, FloatParts128 *a) +{ + r->frac =3D a->frac_hi | (a->frac_lo !=3D 0); +} + +static void frac128_truncjam(FloatParts128 *r, FloatParts256 *a) +{ + r->frac_hi =3D a->frac_hi; + r->frac_lo =3D a->frac_hm | ((a->frac_lm | a->frac_lo) !=3D 0); +} + +#define frac_truncjam(R, A) FRAC_GENERIC_64_128(truncjam, R)(R, A) + #define partsN(NAME) glue(glue(glue(parts,N),_),NAME) #define FloatPartsN glue(FloatParts,N) +#define FloatPartsW glue(FloatParts,W) =20 #define N 64 +#define W 128 =20 #include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" =20 #undef N +#undef W #define N 128 +#define W 256 =20 #include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" =20 #undef N +#undef W #undef partsN #undef FloatPartsN +#undef FloatPartsW =20 /* * Pack/unpack routines with a specific FloatFmt. @@ -1249,89 +1299,42 @@ float128 float128_sub(float128 a, float128 b, float= _status *status) } =20 /* - * Returns the result of multiplying the floating-point values `a' and - * `b'. The operation is performed according to the IEC/IEEE Standard - * for Binary Floating-Point Arithmetic. + * Multiplication */ =20 -static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_statu= s *s) -{ - bool sign =3D a.sign ^ b.sign; - - if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_normal= ) { - uint64_t hi, lo; - int exp =3D a.exp + b.exp; - - mul64To128(a.frac, b.frac, &hi, &lo); - if (hi & DECOMPOSED_IMPLICIT_BIT) { - exp +=3D 1; - } else { - hi <<=3D 1; - } - hi |=3D (lo !=3D 0); - - /* Re-use a */ - a.exp =3D exp; - a.sign =3D sign; - a.frac =3D hi; - return a; - } - /* handle all the NaN cases */ - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - /* Inf * Zero =3D=3D NaN */ - if ((a.cls =3D=3D float_class_inf && b.cls =3D=3D float_class_zero) || - (a.cls =3D=3D float_class_zero && b.cls =3D=3D float_class_inf)) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - /* Multiply by 0 or Inf */ - if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { - a.sign =3D sign; - return a; - } - if (b.cls =3D=3D float_class_inf || b.cls =3D=3D float_class_zero) { - b.sign =3D sign; - return b; - } - g_assert_not_reached(); -} - float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *statu= s) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); - pr =3D mul_floats(pa, pb, status); + pr =3D parts_mul(&pa, &pb, status); =20 - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR soft_f32_mul(float32 a, float32 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); - pr =3D mul_floats(pa, pb, status); + pr =3D parts_mul(&pa, &pb, status); =20 - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_f64_mul(float64 a, float64 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); - pr =3D mul_floats(pa, pb, status); + pr =3D parts_mul(&pa, &pb, status); =20 - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } =20 static float hard_f32_mul(float a, float b) @@ -1358,20 +1361,28 @@ float64_mul(float64 a, float64 b, float_status *s) f64_is_zon2, f64_addsubmul_post); } =20 -/* - * Returns the result of multiplying the bfloat16 - * values `a' and `b'. - */ - -bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *s= tatus) +bfloat16 QEMU_FLATTEN +bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); - pr =3D mul_floats(pa, pb, status); + pr =3D parts_mul(&pa, &pb, status); =20 - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); +} + +float128 QEMU_FLATTEN +float128_mul(float128 a, float128 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr =3D parts_mul(&pa, &pb, status); + + return float128_round_pack_canonical(pr, status); } =20 /* @@ -7067,69 +7078,6 @@ float128 float128_round_to_int(float128 a, float_sta= tus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the quadruple-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_mul(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - bSig1 =3D extractFloat128Frac1( b ); - bSig0 =3D extractFloat128Frac0( b ); - bExp =3D extractFloat128Exp( b ); - bSign =3D extractFloat128Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FFF ) { - if ( ( aSig0 | aSig1 ) - || ( ( bExp =3D=3D 0x7FFF ) && ( bSig0 | bSig1 ) ) ) { - return propagateFloat128NaN(a, b, status); - } - if ( ( bExp | bSig0 | bSig1 ) =3D=3D 0 ) goto invalid; - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( bExp =3D=3D 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - if ( ( aExp | aSig0 | aSig1 ) =3D=3D 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return packFloat128( zSign, 0, 0= , 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - if ( bExp =3D=3D 0 ) { - if ( ( bSig0 | bSig1 ) =3D=3D 0 ) return packFloat128( zSign, 0, 0= , 0 ); - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - zExp =3D aExp + bExp - 0x4000; - aSig0 |=3D UINT64_C(0x0001000000000000); - shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 ); - mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig= 3 ); - add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 ); - zSig2 |=3D ( zSig3 !=3D 0 ); - if (UINT64_C( 0x0002000000000000) <=3D zSig0 ) { - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 ); - ++zExp; - } - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the result of dividing the quadruple-precision floating-point va= lue | `a' by the corresponding value `b'. The operation is performed accordin= g to diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cfce9f6421..9a67ab2bea 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -362,3 +362,54 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, Flo= atPartsN *b, p_nan: return parts_pick_nan(a, b, s); } + +/* + * Returns the result of multiplying the floating-point values `a' and + * `b'. The operation is performed according to the IEC/IEEE Standard + * for Binary Floating-Point Arithmetic. + */ +static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b, + float_status *s) +{ + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + bool sign =3D a->sign ^ b->sign; + + if (likely(ab_mask =3D=3D float_cmask_normal)) { + FloatPartsW tmp; + + frac_mulw(&tmp, a, b); + frac_truncjam(a, &tmp); + + a->exp +=3D b->exp + 1; + if (!(a->frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + frac_add(a, a, a); + a->exp -=3D 1; + } + + a->sign =3D sign; + return a; + } + + /* Inf * Zero =3D=3D NaN */ + if (unlikely(ab_mask =3D=3D float_cmask_infzero)) { + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + return parts_pick_nan(a, b, s); + } + + /* Multiply by 0 or Inf */ + if (ab_mask & float_cmask_inf) { + a->cls =3D float_class_inf; + a->sign =3D sign; + return a; + } + + g_assert(ab_mask & float_cmask_zero); + a->cls =3D float_class_zero; + a->sign =3D sign; + return a; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440229; cv=none; d=zohomail.com; s=zohoarc; b=df5EbkJKOLJgpfMBqbzBfHU/Eej0aSIDfrCoFkchr6T0bPG6OXF0Y3F4aAm9uWsiv1BRa/KcJvVCMzSmqB7GM0yZBaKqZj8apMBCAoW28FaUilRZwcvsAcxqyr0uL+Q/hl4qMuXUHm6xVYnz1R845naOYDWTr4qbmiGnOWEb2T0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440229; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Xkz1ybjWLeUjZCsE7o98Dkj/GU255PMCjv80HfDnbE=; b=CxCcsUPhwE3dQZgZAtLcED1L/MUjFbM2n4IP9HVnR6VsSakYmmI5VuHlqVNR1ydPvMxk9qvh27jRb1GoshyG2azOO/r2ryF4sbs9t1YsEloZOJCW8VrIsYcQFsbqH7IA2Ig/toaYf1c+nOEiFO7msCm+s0FbPOUGqjBGrraZLvA= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_muladd. Implement float128_muladd with FloatParts128. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/fpu/softfloat.h | 2 + fpu/softfloat.c | 406 ++++++++++++++++++-------------------- tests/fp/fp-bench.c | 8 +- tests/fp/fp-test.c | 2 +- fpu/softfloat-parts.c.inc | 126 ++++++++++++ tests/fp/wrap.c.inc | 12 ++ 6 files changed, 342 insertions(+), 214 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 019c2ec66d..53f2c2ea3c 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1197,6 +1197,8 @@ float128 float128_round_to_int(float128, float_status= *status); float128 float128_add(float128, float128, float_status *status); float128 float128_sub(float128, float128, float_status *status); float128 float128_mul(float128, float128, float_status *status); +float128 float128_muladd(float128, float128, float128, int, + float_status *status); float128 float128_div(float128, float128, float_status *status); float128 float128_rem(float128, float128, float_status *status); float128 float128_sqrt(float128, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4f498c11e5..a9ee8498ae 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -715,6 +715,10 @@ static float128 float128_pack_raw(const FloatParts128 = *p) #define PARTS_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) =20 +#define PARTS_GENERIC_64_128_256(NAME, P) \ + QEMU_GENERIC(P, (FloatParts256 *, parts256_##NAME), \ + (FloatParts128 *, parts128_##NAME), parts64_##NAME) + #define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P,= S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P,= S) =20 @@ -760,15 +764,17 @@ static void parts128_uncanon(FloatParts128 *p, float_= status *status, =20 static void parts64_add_normal(FloatParts64 *a, FloatParts64 *b); static void parts128_add_normal(FloatParts128 *a, FloatParts128 *b); +static void parts256_add_normal(FloatParts256 *a, FloatParts256 *b); =20 #define parts_add_normal(A, B) \ - PARTS_GENERIC_64_128(add_normal, A)(A, B) + PARTS_GENERIC_64_128_256(add_normal, A)(A, B) =20 static bool parts64_sub_normal(FloatParts64 *a, FloatParts64 *b); static bool parts128_sub_normal(FloatParts128 *a, FloatParts128 *b); +static bool parts256_sub_normal(FloatParts256 *a, FloatParts256 *b); =20 #define parts_sub_normal(A, B) \ - PARTS_GENERIC_64_128(sub_normal, A)(A, B) + PARTS_GENERIC_64_128_256(sub_normal, A)(A, B) =20 static FloatParts64 *parts64_addsub(FloatParts64 *a, FloatParts64 *b, float_status *s, bool subtract); @@ -786,6 +792,16 @@ static FloatParts128 *parts128_mul(FloatParts128 *a, F= loatParts128 *b, #define parts_mul(A, B, S) \ PARTS_GENERIC_64_128(mul, A)(A, B, S) =20 +static FloatParts64 *parts64_muladd(FloatParts64 *a, FloatParts64 *b, + FloatParts64 *c, int flags, + float_status *s); +static FloatParts128 *parts128_muladd(FloatParts128 *a, FloatParts128 *b, + FloatParts128 *c, int flags, + float_status *s); + +#define parts_muladd(A, B, C, Z, S) \ + PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -793,6 +809,10 @@ static FloatParts128 *parts128_mul(FloatParts128 *a, F= loatParts128 *b, #define FRAC_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) =20 +#define FRAC_GENERIC_64_128_256(NAME, P) \ + QEMU_GENERIC(P, (FloatParts256 *, frac256_##NAME), \ + (FloatParts128 *, frac128_##NAME), frac64_##NAME) + static bool frac64_add(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) { return uadd64_overflow(a->frac, b->frac, &r->frac); @@ -806,7 +826,17 @@ static bool frac128_add(FloatParts128 *r, FloatParts12= 8 *a, FloatParts128 *b) return c; } =20 -#define frac_add(R, A, B) FRAC_GENERIC_64_128(add, R)(R, A, B) +static bool frac256_add(FloatParts256 *r, FloatParts256 *a, FloatParts256 = *b) +{ + bool c =3D 0; + r->frac_lo =3D uadd64_carry(a->frac_lo, b->frac_lo, &c); + r->frac_lm =3D uadd64_carry(a->frac_lm, b->frac_lm, &c); + r->frac_hm =3D uadd64_carry(a->frac_hm, b->frac_hm, &c); + r->frac_hi =3D uadd64_carry(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_add(R, A, B) FRAC_GENERIC_64_128_256(add, R)(R, A, B) =20 static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c) { @@ -901,7 +931,16 @@ static void frac128_neg(FloatParts128 *a) a->frac_hi =3D usub64_borrow(0, a->frac_hi, &c); } =20 -#define frac_neg(A) FRAC_GENERIC_64_128(neg, A)(A) +static void frac256_neg(FloatParts256 *a) +{ + bool c =3D 0; + a->frac_lo =3D usub64_borrow(0, a->frac_lo, &c); + a->frac_lm =3D usub64_borrow(0, a->frac_lm, &c); + a->frac_hm =3D usub64_borrow(0, a->frac_hm, &c); + a->frac_hi =3D usub64_borrow(0, a->frac_hi, &c); +} + +#define frac_neg(A) FRAC_GENERIC_64_128_256(neg, A)(A) =20 static int frac64_normalize(FloatParts64 *a) { @@ -932,7 +971,55 @@ static int frac128_normalize(FloatParts128 *a) return 128; } =20 -#define frac_normalize(A) FRAC_GENERIC_64_128(normalize, A)(A) +static int frac256_normalize(FloatParts256 *a) +{ + uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_hm; + uint64_t a2 =3D a->frac_lm, a3 =3D a->frac_lo; + int ret, shl, shr; + + if (likely(a0)) { + shl =3D clz64(a0); + if (shl =3D=3D 0) { + return 0; + } + ret =3D shl; + } else { + if (a1) { + ret =3D 64; + a0 =3D a1, a1 =3D a2, a2 =3D a3, a3 =3D 0; + } else if (a2) { + ret =3D 128; + a0 =3D a2, a1 =3D a3, a2 =3D 0, a3 =3D 0; + } else if (a3) { + ret =3D 192; + a0 =3D a3, a1 =3D 0, a2 =3D 0, a3 =3D 0; + } else { + ret =3D 256; + a0 =3D 0, a1 =3D 0, a2 =3D 0, a3 =3D 0; + goto done; + } + shl =3D clz64(a0); + if (shl =3D=3D 0) { + goto done; + } + ret +=3D shl; + } + + shr =3D -shl & 63; + a0 =3D (a0 << shl) | (a1 >> shr); + a1 =3D (a1 << shl) | (a2 >> shr); + a2 =3D (a2 << shl) | (a3 >> shr); + a3 =3D (a3 << shl); + + done: + a->frac_hi =3D a0; + a->frac_hm =3D a1; + a->frac_lm =3D a2; + a->frac_lo =3D a3; + return ret; +} + +#define frac_normalize(A) FRAC_GENERIC_64_128_256(normalize, A)(A) =20 static void frac64_shl(FloatParts64 *a, int c) { @@ -968,7 +1055,51 @@ static void frac128_shrjam(FloatParts128 *a, int c) shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_= lo); } =20 -#define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C) +static void frac256_shrjam(FloatParts256 *a, int c) +{ + uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_hm; + uint64_t a2 =3D a->frac_lm, a3 =3D a->frac_lo; + uint64_t sticky =3D 0; + int invc; + + if (unlikely(c =3D=3D 0)) { + return; + } else if (likely(c < 64)) { + /* nothing */ + } else if (likely(c < 256)) { + if (unlikely(c & 128)) { + sticky |=3D a2 | a3; + a3 =3D a1, a2 =3D a0, a1 =3D 0, a0 =3D 0; + } + if (unlikely(c & 64)) { + sticky |=3D a3; + a3 =3D a2, a2 =3D a1, a1 =3D a0, a0 =3D 0; + } + c &=3D 63; + if (c =3D=3D 0) { + goto done; + } + } else { + sticky =3D a0 | a1 | a2 | a3; + a0 =3D a1 =3D a2 =3D a3 =3D 0; + goto done; + } + + invc =3D -c & 63; + sticky |=3D a3 << invc; + a3 =3D (a3 >> c) | (a2 << invc); + a2 =3D (a2 >> c) | (a1 << invc); + a1 =3D (a1 >> c) | (a0 << invc); + a0 =3D (a0 >> c); + + done: + a->frac_lo =3D a3 | (sticky !=3D 0); + a->frac_lm =3D a2; + a->frac_hm =3D a1; + a->frac_hi =3D a0; +} + +#define frac_shrjam(A, C) FRAC_GENERIC_64_128_256(shrjam, A)(A, C) =20 static bool frac64_sub(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) { @@ -983,7 +1114,17 @@ static bool frac128_sub(FloatParts128 *r, FloatParts1= 28 *a, FloatParts128 *b) return c; } =20 -#define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B) +static bool frac256_sub(FloatParts256 *r, FloatParts256 *a, FloatParts256 = *b) +{ + bool c =3D 0; + r->frac_lo =3D usub64_borrow(a->frac_lo, b->frac_lo, &c); + r->frac_lm =3D usub64_borrow(a->frac_lm, b->frac_lm, &c); + r->frac_hm =3D usub64_borrow(a->frac_hm, b->frac_hm, &c); + r->frac_hi =3D usub64_borrow(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_sub(R, A, B) FRAC_GENERIC_64_128_256(sub, R)(R, A, B) =20 static void frac64_truncjam(FloatParts64 *r, FloatParts128 *a) { @@ -998,6 +1139,22 @@ static void frac128_truncjam(FloatParts128 *r, FloatP= arts256 *a) =20 #define frac_truncjam(R, A) FRAC_GENERIC_64_128(truncjam, R)(R, A) =20 +static void frac64_widen(FloatParts128 *r, FloatParts64 *a) +{ + r->frac_hi =3D a->frac; + r->frac_lo =3D 0; +} + +static void frac128_widen(FloatParts256 *r, FloatParts128 *a) +{ + r->frac_hi =3D a->frac_hi; + r->frac_hm =3D a->frac_lo; + r->frac_lm =3D 0; + r->frac_lo =3D 0; +} + +#define frac_widen(A, B) FRAC_GENERIC_64_128(widen, B)(A, B) + #define partsN(NAME) glue(glue(glue(parts,N),_),NAME) #define FloatPartsN glue(FloatParts,N) #define FloatPartsW glue(FloatParts,W) @@ -1016,6 +1173,12 @@ static void frac128_truncjam(FloatParts128 *r, Float= Parts256 *a) #include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" =20 +#undef N +#undef W +#define N 256 + +#include "softfloat-parts-addsub.c.inc" + #undef N #undef W #undef partsN @@ -1386,230 +1549,48 @@ float128_mul(float128 a, float128 b, float_status = *status) } =20 /* - * Returns the result of multiplying the floating-point values `a' and - * `b' then adding 'c', with no intermediate rounding step after the - * multiplication. The operation is performed according to the - * IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008. - * The flags argument allows the caller to select negation of the - * addend, the intermediate product, or the final result. (The - * difference between this and having the caller do a separate - * negation is that negating externally will flip the sign bit on - * NaNs.) + * Fused multiply-add */ =20 -static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatPar= ts64 c, - int flags, float_status *s) -{ - bool inf_zero, p_sign; - bool sign_flip =3D flags & float_muladd_negate_result; - FloatClass p_class; - uint64_t hi, lo; - int p_exp; - int ab_mask, abc_mask; - - ab_mask =3D float_cmask(a.cls) | float_cmask(b.cls); - abc_mask =3D float_cmask(c.cls) | ab_mask; - inf_zero =3D ab_mask =3D=3D float_cmask_infzero; - - /* It is implementation-defined whether the cases of (0,inf,qnan) - * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN - * they return if they do), so we have to hand this information - * off to the target-specific pick-a-NaN routine. - */ - if (unlikely(abc_mask & float_cmask_anynan)) { - return *parts_pick_nan_muladd(&a, &b, &c, s, ab_mask, abc_mask); - } - - if (inf_zero) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - - if (flags & float_muladd_negate_c) { - c.sign ^=3D 1; - } - - p_sign =3D a.sign ^ b.sign; - - if (flags & float_muladd_negate_product) { - p_sign ^=3D 1; - } - - if (ab_mask & float_cmask_inf) { - p_class =3D float_class_inf; - } else if (ab_mask & float_cmask_zero) { - p_class =3D float_class_zero; - } else { - p_class =3D float_class_normal; - } - - if (c.cls =3D=3D float_class_inf) { - if (p_class =3D=3D float_class_inf && p_sign !=3D c.sign) { - float_raise(float_flag_invalid, s); - parts_default_nan(&c, s); - } else { - c.sign ^=3D sign_flip; - } - return c; - } - - if (p_class =3D=3D float_class_inf) { - a.cls =3D float_class_inf; - a.sign =3D p_sign ^ sign_flip; - return a; - } - - if (p_class =3D=3D float_class_zero) { - if (c.cls =3D=3D float_class_zero) { - if (p_sign !=3D c.sign) { - p_sign =3D s->float_rounding_mode =3D=3D float_round_down; - } - c.sign =3D p_sign; - } else if (flags & float_muladd_halve_result) { - c.exp -=3D 1; - } - c.sign ^=3D sign_flip; - return c; - } - - /* a & b should be normals now... */ - assert(a.cls =3D=3D float_class_normal && - b.cls =3D=3D float_class_normal); - - p_exp =3D a.exp + b.exp; - - mul64To128(a.frac, b.frac, &hi, &lo); - - /* Renormalize to the msb. */ - if (hi & DECOMPOSED_IMPLICIT_BIT) { - p_exp +=3D 1; - } else { - shortShift128Left(hi, lo, 1, &hi, &lo); - } - - /* + add/sub */ - if (c.cls !=3D float_class_zero) { - int exp_diff =3D p_exp - c.exp; - if (p_sign =3D=3D c.sign) { - /* Addition */ - if (exp_diff <=3D 0) { - shift64RightJamming(hi, -exp_diff, &hi); - p_exp =3D c.exp; - if (uadd64_overflow(hi, c.frac, &hi)) { - shift64RightJamming(hi, 1, &hi); - hi |=3D DECOMPOSED_IMPLICIT_BIT; - p_exp +=3D 1; - } - } else { - uint64_t c_hi, c_lo, over; - shift128RightJamming(c.frac, 0, exp_diff, &c_hi, &c_lo); - add192(0, hi, lo, 0, c_hi, c_lo, &over, &hi, &lo); - if (over) { - shift64RightJamming(hi, 1, &hi); - hi |=3D DECOMPOSED_IMPLICIT_BIT; - p_exp +=3D 1; - } - } - } else { - /* Subtraction */ - uint64_t c_hi =3D c.frac, c_lo =3D 0; - - if (exp_diff <=3D 0) { - shift128RightJamming(hi, lo, -exp_diff, &hi, &lo); - if (exp_diff =3D=3D 0 - && - (hi > c_hi || (hi =3D=3D c_hi && lo >=3D c_lo))) { - sub128(hi, lo, c_hi, c_lo, &hi, &lo); - } else { - sub128(c_hi, c_lo, hi, lo, &hi, &lo); - p_sign ^=3D 1; - p_exp =3D c.exp; - } - } else { - shift128RightJamming(c_hi, c_lo, - exp_diff, - &c_hi, &c_lo); - sub128(hi, lo, c_hi, c_lo, &hi, &lo); - } - - if (hi =3D=3D 0 && lo =3D=3D 0) { - a.cls =3D float_class_zero; - a.sign =3D s->float_rounding_mode =3D=3D float_round_down; - a.sign ^=3D sign_flip; - return a; - } else { - int shift; - if (hi !=3D 0) { - shift =3D clz64(hi); - } else { - shift =3D clz64(lo) + 64; - } - /* Normalizing to a binary point of 124 is the - correct adjust for the exponent. However since we're - shifting, we might as well put the binary point back - at 63 where we really want it. Therefore shift as - if we're leaving 1 bit at the top of the word, but - adjust the exponent as if we're leaving 3 bits. */ - shift128Left(hi, lo, shift, &hi, &lo); - p_exp -=3D shift; - } - } - } - hi |=3D (lo !=3D 0); - - if (flags & float_muladd_halve_result) { - p_exp -=3D 1; - } - - /* finally prepare our result */ - a.cls =3D float_class_normal; - a.sign =3D p_sign ^ sign_flip; - a.exp =3D p_exp; - a.frac =3D hi; - - return a; -} - float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, - int flags, float_status *s= tatus) + int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; =20 float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); float16_unpack_canonical(&pc, c, status); - pr =3D muladd_floats(pa, pb, pc, flags, status); + pr =3D parts_muladd(&pa, &pb, &pc, flags, status); =20 - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; =20 float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); float32_unpack_canonical(&pc, c, status); - pr =3D muladd_floats(pa, pb, pc, flags, status); + pr =3D parts_muladd(&pa, &pb, &pc, flags, status); =20 - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; =20 float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); float64_unpack_canonical(&pc, c, status); - pr =3D muladd_floats(pa, pb, pc, flags, status); + pr =3D parts_muladd(&pa, &pb, &pc, flags, status); =20 - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } =20 static bool force_soft_fma; @@ -1756,23 +1737,30 @@ float64_muladd(float64 xa, float64 xb, float64 xc, = int flags, float_status *s) return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s); } =20 -/* - * Returns the result of multiplying the bfloat16 values `a' - * and `b' then adding 'c', with no intermediate rounding step after the - * multiplication. - */ - bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; =20 bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); bfloat16_unpack_canonical(&pc, c, status); - pr =3D muladd_floats(pa, pb, pc, flags, status); + pr =3D parts_muladd(&pa, &pb, &pc, flags, status); =20 - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); +} + +float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c, + int flags, float_status *status) +{ + FloatParts128 pa, pb, pc, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + float128_unpack_canonical(&pc, c, status); + pr =3D parts_muladd(&pa, &pb, &pc, flags, status); + + return float128_round_pack_canonical(pr, status); } =20 /* diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index d319993280..c24baf8535 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -386,7 +386,7 @@ static void bench(enum precision prec, enum op op, int = n_ops, bool no_neg) for (i =3D 0; i < OPS_PER_ITER; i++) { float128 a =3D ops[0].f128; float128 b =3D ops[1].f128; - /* float128 c =3D ops[2].f128; */ + float128 c =3D ops[2].f128; =20 switch (op) { case OP_ADD: @@ -401,9 +401,9 @@ static void bench(enum precision prec, enum op op, int = n_ops, bool no_neg) case OP_DIV: res.f128 =3D float128_div(a, b, &soft_status); break; - /* case OP_FMA: */ - /* res.f128 =3D float128_muladd(a, b, c, 0, &soft_stat= us); */ - /* break; */ + case OP_FMA: + res.f128 =3D float128_muladd(a, b, c, 0, &soft_status); + break; case OP_SQRT: res.f128 =3D float128_sqrt(a, &soft_status); break; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5a4cad8c8b..ff131afbde 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -717,7 +717,7 @@ static void do_testfloat(int op, int rmode, bool exact) test_abz_f128(true_abz_f128M, subj_abz_f128M); break; case F128_MULADD: - not_implemented(); + test_abcz_f128(slow_f128M_mulAdd, qemu_f128M_mulAdd); break; case F128_SQRT: test_az_f128(slow_f128M_sqrt, qemu_f128M_sqrt); diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 9a67ab2bea..a203811299 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -413,3 +413,129 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, Float= PartsN *b, a->sign =3D sign; return a; } + +/* + * Returns the result of multiplying the floating-point values `a' and + * `b' then adding 'c', with no intermediate rounding step after the + * multiplication. The operation is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008. + * The flags argument allows the caller to select negation of the + * addend, the intermediate product, or the final result. (The + * difference between this and having the caller do a separate + * negation is that negating externally will flip the sign bit on NaNs.) + * + * Requires A and C extracted into a double-sized structure to provide the + * extra space for the widening multiply. + */ +static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, + FloatPartsN *c, int flags, float_status= *s) +{ + int ab_mask, abc_mask; + FloatPartsW p_widen, c_widen; + + ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + abc_mask =3D float_cmask(c->cls) | ab_mask; + + /* + * It is implementation-defined whether the cases of (0,inf,qnan) + * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN + * they return if they do), so we have to hand this information + * off to the target-specific pick-a-NaN routine. + */ + if (unlikely(abc_mask & float_cmask_anynan)) { + return parts_pick_nan_muladd(a, b, c, s, ab_mask, abc_mask); + } + + if (flags & float_muladd_negate_c) { + c->sign ^=3D 1; + } + + /* Compute the sign of the product into A. */ + a->sign ^=3D b->sign; + if (flags & float_muladd_negate_product) { + a->sign ^=3D 1; + } + + if (unlikely(ab_mask !=3D float_cmask_normal)) { + if (unlikely(ab_mask =3D=3D float_cmask_infzero)) { + goto d_nan; + } + + if (ab_mask & float_cmask_inf) { + if (c->cls =3D=3D float_class_inf && a->sign !=3D c->sign) { + goto d_nan; + } + goto return_inf; + } + + g_assert(ab_mask & float_cmask_zero); + if (c->cls =3D=3D float_class_normal) { + *a =3D *c; + goto return_normal; + } + if (c->cls =3D=3D float_class_zero) { + if (a->sign !=3D c->sign) { + goto return_sub_zero; + } + goto return_zero; + } + g_assert(c->cls =3D=3D float_class_inf); + } + + if (unlikely(c->cls =3D=3D float_class_inf)) { + a->sign =3D c->sign; + goto return_inf; + } + + /* Perform the multiplication step. */ + p_widen.sign =3D a->sign; + p_widen.exp =3D a->exp + b->exp + 1; + frac_mulw(&p_widen, a, b); + if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + frac_add(&p_widen, &p_widen, &p_widen); + p_widen.exp -=3D 1; + } + + /* Perform the addition step. */ + if (c->cls !=3D float_class_zero) { + /* Zero-extend C to less significant bits. */ + frac_widen(&c_widen, c); + c_widen.exp =3D c->exp; + + if (a->sign =3D=3D c->sign) { + parts_add_normal(&p_widen, &c_widen); + } else if (!parts_sub_normal(&p_widen, &c_widen)) { + goto return_sub_zero; + } + } + + /* Narrow with sticky bit, for proper rounding later. */ + frac_truncjam(a, &p_widen); + a->sign =3D p_widen.sign; + a->exp =3D p_widen.exp; + + return_normal: + if (flags & float_muladd_halve_result) { + a->exp -=3D 1; + } + finish_sign: + if (flags & float_muladd_negate_result) { + a->sign ^=3D 1; + } + return a; + + return_sub_zero: + a->sign =3D s->float_rounding_mode =3D=3D float_round_down; + return_zero: + a->cls =3D float_class_zero; + goto finish_sign; + + return_inf: + a->cls =3D float_class_inf; + goto finish_sign; + + d_nan: + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; +} diff --git a/tests/fp/wrap.c.inc b/tests/fp/wrap.c.inc index 0cbd20013e..cb1bb77e4c 100644 --- a/tests/fp/wrap.c.inc +++ b/tests/fp/wrap.c.inc @@ -574,6 +574,18 @@ WRAP_MULADD(qemu_f32_mulAdd, float32_muladd, float32) WRAP_MULADD(qemu_f64_mulAdd, float64_muladd, float64) #undef WRAP_MULADD =20 +static void qemu_f128M_mulAdd(const float128_t *ap, const float128_t *bp, + const float128_t *cp, float128_t *res) +{ + float128 a, b, c, ret; + + a =3D soft_to_qemu128(*ap); + b =3D soft_to_qemu128(*bp); + c =3D soft_to_qemu128(*cp); + ret =3D float128_muladd(a, b, c, 0, &qsf); + *res =3D qemu_to_soft128(ret); +} + #define WRAP_CMP16(name, func, retcond) \ static bool name(float16_t a, float16_t b) \ { \ --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440395; cv=none; d=zohomail.com; s=zohoarc; b=fI6rIV8rtNrc9MLXsbrIiQR6ef0RWTQZhev4MCDQZFVFLx6XGGDNBpPW85ISD54g6DDdOa3V1JccttBwJIrpLE7fwoY5RhqaFhNb6Z+8ueUeikCgrCQX+VtRO80QjB7UTMx+VSoEdXqroQAfZ6s3G9xuF2E6P3FWCTzRh1YAdX0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440395; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Via host-utils.h, we use a host widening multiply for 64-bit hosts, and a common subroutine for 32-bit hosts. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 2e3760a9c1..f6dfbe108d 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -470,27 +470,10 @@ static inline void sub192(uint64_t a0, uint64_t a1, u= int64_t a2, | `z0Ptr' and `z1Ptr'. *-------------------------------------------------------------------------= ---*/ =20 -static inline void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, ui= nt64_t *z1Ptr ) +static inline void +mul64To128(uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr) { - uint32_t aHigh, aLow, bHigh, bLow; - uint64_t z0, zMiddleA, zMiddleB, z1; - - aLow =3D a; - aHigh =3D a>>32; - bLow =3D b; - bHigh =3D b>>32; - z1 =3D ( (uint64_t) aLow ) * bLow; - zMiddleA =3D ( (uint64_t) aLow ) * bHigh; - zMiddleB =3D ( (uint64_t) aHigh ) * bLow; - z0 =3D ( (uint64_t) aHigh ) * bHigh; - zMiddleA +=3D zMiddleB; - z0 +=3D ( ( (uint64_t) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>3= 2 ); - zMiddleA <<=3D 32; - z1 +=3D zMiddleA; - z0 +=3D ( z1 < zMiddleA ); - *z1Ptr =3D z1; - *z0Ptr =3D z0; - + mulu64(z1Ptr, z0Ptr, a, b); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440789; cv=none; d=zohomail.com; s=zohoarc; b=C+dCSo+UlBTgpbVAGqfCC31XMBlSZBLRC0NX9RG1omUR6+rc6VIHopgxC/F3tEvNwYo9xuJOgNK5F47OMsCjlK17+UoAQgrmwZJvl2o3ZeYl6VRPzJg/F3WRKZQkvNWZHCck4ZHpfy7KoGM98bJf7VJ1bfa1UeP4FsMWGjaEgN8= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:48:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 39/72] softfloat: Use add192 in mul128To256 Date: Fri, 7 May 2021 18:47:29 -0700 Message-Id: <20210508014802.892561-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We can perform the operation in 6 total adds instead of 8. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- include/fpu/softfloat-macros.h | 37 +++++++++++----------------------- 1 file changed, 12 insertions(+), 25 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index f6dfbe108d..76327d844d 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -511,34 +511,21 @@ static inline void | the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'. *-------------------------------------------------------------------------= ---*/ =20 -static inline void - mul128To256( - uint64_t a0, - uint64_t a1, - uint64_t b0, - uint64_t b1, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr, - uint64_t *z3Ptr - ) +static inline void mul128To256(uint64_t a0, uint64_t a1, + uint64_t b0, uint64_t b1, + uint64_t *z0Ptr, uint64_t *z1Ptr, + uint64_t *z2Ptr, uint64_t *z3Ptr) { - uint64_t z0, z1, z2, z3; - uint64_t more1, more2; + uint64_t z0, z1, z2; + uint64_t m0, m1, m2, n1, n2; =20 - mul64To128( a1, b1, &z2, &z3 ); - mul64To128( a1, b0, &z1, &more2 ); - add128( z1, more2, 0, z2, &z1, &z2 ); - mul64To128( a0, b0, &z0, &more1 ); - add128( z0, more1, 0, z1, &z0, &z1 ); - mul64To128( a0, b1, &more1, &more2 ); - add128( more1, more2, 0, z2, &more1, &z2 ); - add128( z0, z1, 0, more1, &z0, &z1 ); - *z3Ptr =3D z3; - *z2Ptr =3D z2; - *z1Ptr =3D z1; - *z0Ptr =3D z0; + mul64To128(a1, b0, &m1, &m2); + mul64To128(a0, b1, &n1, &n2); + mul64To128(a1, b1, &z2, z3Ptr); + mul64To128(a0, b0, &z0, &z1); =20 + add192( 0, m1, m2, 0, n1, n2, &m0, &m1, &m2); + add192(m0, m1, m2, z0, z1, z2, z0Ptr, z1Ptr, z2Ptr); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:51:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 40/72] softfloat: Tidy mul128By64To192 Date: Fri, 7 May 2021 18:47:30 -0700 Message-Id: <20210508014802.892561-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Clean up the formatting and variables; no functional change. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/fpu/softfloat-macros.h | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 76327d844d..672c1db555 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -484,24 +484,14 @@ mul64To128(uint64_t a, uint64_t b, uint64_t *z0Ptr, u= int64_t *z1Ptr) *-------------------------------------------------------------------------= ---*/ =20 static inline void - mul128By64To192( - uint64_t a0, - uint64_t a1, - uint64_t b, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr - ) +mul128By64To192(uint64_t a0, uint64_t a1, uint64_t b, + uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr) { - uint64_t z0, z1, z2, more1; - - mul64To128( a1, b, &z1, &z2 ); - mul64To128( a0, b, &z0, &more1 ); - add128( z0, more1, 0, z1, &z0, &z1 ); - *z2Ptr =3D z2; - *z1Ptr =3D z1; - *z0Ptr =3D z0; + uint64_t z0, z1, m1; =20 + mul64To128(a1, b, &m1, z2Ptr); + mul64To128(a0, b, &z0, &z1); + add128(z0, z1, 0, m1, z0Ptr, z1Ptr); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440660; cv=none; d=zohomail.com; s=zohoarc; b=DSQ/Vq6Fi1Uw0UKLvYjfqDVXhdMO4UTQjGUj9F0lN0+fm/1V0iSs7DWBlb2jJ5leFbcgwpYGKy8mIhcBsl6iNqaAGI+w2LgjRK9O4Y54J61XtEqIGCpCTRvA5Z6ZxsJhF87/Jt9NX0ojMpIZB7lkBH7moQ08MNIvJZ9TzrPWxpk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440660; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Have x86_64 assembly for them, with a fallback. This avoids shuffling values through %cl in the x86 case. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/fpu/softfloat-macros.h | 36 ++++++++++++ fpu/softfloat.c | 102 +++++++++++++++++++++++++-------- 2 files changed, 115 insertions(+), 23 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 672c1db555..ec4e27a595 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -85,6 +85,42 @@ this code that are retained. #include "fpu/softfloat-types.h" #include "qemu/host-utils.h" =20 +/** + * shl_double: double-word merging left shift + * @l: left or most-significant word + * @r: right or least-significant word + * @c: shift count + * + * Shift @l left by @c bits, shifting in bits from @r. + */ +static inline uint64_t shl_double(uint64_t l, uint64_t r, int c) +{ +#if defined(__x86_64__) + asm("shld %b2, %1, %0" : "+r"(l) : "r"(r), "ci"(c)); + return l; +#else + return c ? (l << c) | (r >> (64 - c)) : l; +#endif +} + +/** + * shr_double: double-word merging right shift + * @l: left or most-significant word + * @r: right or least-significant word + * @c: shift count + * + * Shift @r right by @c bits, shifting in bits from @l. + */ +static inline uint64_t shr_double(uint64_t l, uint64_t r, int c) +{ +#if defined(__x86_64__) + asm("shrd %b2, %1, %0" : "+r"(r) : "r"(l), "ci"(c)); + return r; +#else + return c ? (r >> c) | (l << (64 - c)) : r; +#endif +} + /*------------------------------------------------------------------------= ---- | Shifts `a' right by the number of bits given in `count'. If any nonzero | bits are shifted off, they are ``jammed'' into the least significant bit= of diff --git a/fpu/softfloat.c b/fpu/softfloat.c index a9ee8498ae..a42c297828 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -956,15 +956,12 @@ static int frac128_normalize(FloatParts128 *a) { if (a->frac_hi) { int shl =3D clz64(a->frac_hi); - if (shl) { - int shr =3D 64 - shl; - a->frac_hi =3D (a->frac_hi << shl) | (a->frac_lo >> shr); - a->frac_lo =3D (a->frac_lo << shl); - } + a->frac_hi =3D shl_double(a->frac_hi, a->frac_lo, shl); + a->frac_lo <<=3D shl; return shl; } else if (a->frac_lo) { int shl =3D clz64(a->frac_lo); - a->frac_hi =3D (a->frac_lo << shl); + a->frac_hi =3D a->frac_lo << shl; a->frac_lo =3D 0; return shl + 64; } @@ -975,7 +972,7 @@ static int frac256_normalize(FloatParts256 *a) { uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_hm; uint64_t a2 =3D a->frac_lm, a3 =3D a->frac_lo; - int ret, shl, shr; + int ret, shl; =20 if (likely(a0)) { shl =3D clz64(a0); @@ -1005,11 +1002,10 @@ static int frac256_normalize(FloatParts256 *a) ret +=3D shl; } =20 - shr =3D -shl & 63; - a0 =3D (a0 << shl) | (a1 >> shr); - a1 =3D (a1 << shl) | (a2 >> shr); - a2 =3D (a2 << shl) | (a3 >> shr); - a3 =3D (a3 << shl); + a0 =3D shl_double(a0, a1, shl); + a1 =3D shl_double(a1, a2, shl); + a2 =3D shl_double(a2, a3, shl); + a3 <<=3D shl; =20 done: a->frac_hi =3D a0; @@ -1028,7 +1024,20 @@ static void frac64_shl(FloatParts64 *a, int c) =20 static void frac128_shl(FloatParts128 *a, int c) { - shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); + uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_lo; + + if (c & 64) { + a0 =3D a1, a1 =3D 0; + } + + c &=3D 63; + if (c) { + a0 =3D shl_double(a0, a1, c); + a1 =3D a1 << c; + } + + a->frac_hi =3D a0; + a->frac_lo =3D a1; } =20 #define frac_shl(A, C) FRAC_GENERIC_64_128(shl, A)(A, C) @@ -1040,19 +1049,68 @@ static void frac64_shr(FloatParts64 *a, int c) =20 static void frac128_shr(FloatParts128 *a, int c) { - shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); + uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_lo; + + if (c & 64) { + a1 =3D a0, a0 =3D 0; + } + + c &=3D 63; + if (c) { + a1 =3D shr_double(a0, a1, c); + a0 =3D a0 >> c; + } + + a->frac_hi =3D a0; + a->frac_lo =3D a1; } =20 #define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C) =20 static void frac64_shrjam(FloatParts64 *a, int c) { - shift64RightJamming(a->frac, c, &a->frac); + uint64_t a0 =3D a->frac; + + if (likely(c !=3D 0)) { + if (likely(c < 64)) { + a0 =3D (a0 >> c) | (shr_double(a0, 0, c) !=3D 0); + } else { + a0 =3D a0 !=3D 0; + } + a->frac =3D a0; + } } =20 static void frac128_shrjam(FloatParts128 *a, int c) { - shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_= lo); + uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_lo; + uint64_t sticky =3D 0; + + if (unlikely(c =3D=3D 0)) { + return; + } else if (likely(c < 64)) { + /* nothing */ + } else if (likely(c < 128)) { + sticky =3D a1; + a1 =3D a0; + a0 =3D 0; + c &=3D 63; + if (c =3D=3D 0) { + goto done; + } + } else { + sticky =3D a0 | a1; + a0 =3D a1 =3D 0; + goto done; + } + + sticky |=3D shr_double(a1, 0, c); + a1 =3D shr_double(a0, a1, c); + a0 =3D a0 >> c; + + done: + a->frac_lo =3D a1 | (sticky !=3D 0); + a->frac_hi =3D a0; } =20 static void frac256_shrjam(FloatParts256 *a, int c) @@ -1060,7 +1118,6 @@ static void frac256_shrjam(FloatParts256 *a, int c) uint64_t a0 =3D a->frac_hi, a1 =3D a->frac_hm; uint64_t a2 =3D a->frac_lm, a3 =3D a->frac_lo; uint64_t sticky =3D 0; - int invc; =20 if (unlikely(c =3D=3D 0)) { return; @@ -1085,12 +1142,11 @@ static void frac256_shrjam(FloatParts256 *a, int c) goto done; } =20 - invc =3D -c & 63; - sticky |=3D a3 << invc; - a3 =3D (a3 >> c) | (a2 << invc); - a2 =3D (a2 >> c) | (a1 << invc); - a1 =3D (a1 >> c) | (a0 << invc); - a0 =3D (a0 >> c); + sticky |=3D shr_double(a3, 0, c); + a3 =3D shr_double(a2, a3, c); + a2 =3D shr_double(a1, a2, c); + a1 =3D shr_double(a0, a1, c); + a0 =3D a0 >> c; =20 done: a->frac_lo =3D a3 | (sticky !=3D 0); --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_div. Implement float128_div with FloatParts128. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 290 +++++++++++++++----------------------- fpu/softfloat-parts.c.inc | 55 ++++++++ 2 files changed, 171 insertions(+), 174 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index a42c297828..8efa52f7ec 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -802,6 +802,14 @@ static FloatParts128 *parts128_muladd(FloatParts128 *a= , FloatParts128 *b, #define parts_muladd(A, B, C, Z, S) \ PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S) =20 +static FloatParts64 *parts64_div(FloatParts64 *a, FloatParts64 *b, + float_status *s); +static FloatParts128 *parts128_div(FloatParts128 *a, FloatParts128 *b, + float_status *s); + +#define parts_div(A, B, S) \ + PARTS_GENERIC_64_128(div, A)(A, B, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -894,6 +902,87 @@ static void frac128_clear(FloatParts128 *a) =20 #define frac_clear(A) FRAC_GENERIC_64_128(clear, A)(A) =20 +static bool frac64_div(FloatParts64 *a, FloatParts64 *b) +{ + uint64_t n1, n0, r, q; + bool ret; + + /* + * We want a 2*N / N-bit division to produce exactly an N-bit + * result, so that we do not lose any precision and so that we + * do not have to renormalize afterward. If A.frac < B.frac, + * then division would produce an (N-1)-bit result; shift A left + * by one to produce the an N-bit result, and return true to + * decrement the exponent to match. + * + * The udiv_qrnnd algorithm that we're using requires normalization, + * i.e. the msb of the denominator must be set, which is already true. + */ + ret =3D a->frac < b->frac; + if (ret) { + n0 =3D a->frac; + n1 =3D 0; + } else { + n0 =3D a->frac >> 1; + n1 =3D a->frac << 63; + } + q =3D udiv_qrnnd(&r, n0, n1, b->frac); + + /* Set lsb if there is a remainder, to set inexact. */ + a->frac =3D q | (r !=3D 0); + + return ret; +} + +static bool frac128_div(FloatParts128 *a, FloatParts128 *b) +{ + uint64_t q0, q1, a0, a1, b0, b1; + uint64_t r0, r1, r2, r3, t0, t1, t2, t3; + bool ret =3D false; + + a0 =3D a->frac_hi, a1 =3D a->frac_lo; + b0 =3D b->frac_hi, b1 =3D b->frac_lo; + + ret =3D lt128(a0, a1, b0, b1); + if (!ret) { + a1 =3D shr_double(a0, a1, 1); + a0 =3D a0 >> 1; + } + + /* Use 128/64 -> 64 division as estimate for 192/128 -> 128 division. = */ + q0 =3D estimateDiv128To64(a0, a1, b0); + + /* + * Estimate is high because B1 was not included (unless B1 =3D=3D 0). + * Reduce quotient and increase remainder until remainder is non-negat= ive. + * This loop will execute 0 to 2 times. + */ + mul128By64To192(b0, b1, q0, &t0, &t1, &t2); + sub192(a0, a1, 0, t0, t1, t2, &r0, &r1, &r2); + while (r0 !=3D 0) { + q0--; + add192(r0, r1, r2, 0, b0, b1, &r0, &r1, &r2); + } + + /* Repeat using the remainder, producing a second word of quotient. */ + q1 =3D estimateDiv128To64(r1, r2, b0); + mul128By64To192(b0, b1, q1, &t1, &t2, &t3); + sub192(r1, r2, 0, t1, t2, t3, &r1, &r2, &r3); + while (r1 !=3D 0) { + q1--; + add192(r1, r2, r3, 0, b0, b1, &r1, &r2, &r3); + } + + /* Any remainder indicates inexact; set sticky bit. */ + q1 |=3D (r2 | r3) !=3D 0; + + a->frac_hi =3D q0; + a->frac_lo =3D q1; + return ret; +} + +#define frac_div(A, B) FRAC_GENERIC_64_128(div, A)(A, B) + static bool frac64_eqz(FloatParts64 *a) { return a->frac =3D=3D 0; @@ -1820,110 +1909,42 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, = float128 b, float128 c, } =20 /* - * Returns the result of dividing the floating-point value `a' by the - * corresponding value `b'. The operation is performed according to - * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + * Division */ =20 -static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_statu= s *s) -{ - bool sign =3D a.sign ^ b.sign; - - if (a.cls =3D=3D float_class_normal && b.cls =3D=3D float_class_normal= ) { - uint64_t n0, n1, q, r; - int exp =3D a.exp - b.exp; - - /* - * We want a 2*N / N-bit division to produce exactly an N-bit - * result, so that we do not lose any precision and so that we - * do not have to renormalize afterward. If A.frac < B.frac, - * then division would produce an (N-1)-bit result; shift A left - * by one to produce the an N-bit result, and decrement the - * exponent to match. - * - * The udiv_qrnnd algorithm that we're using requires normalizatio= n, - * i.e. the msb of the denominator must be set, which is already t= rue. - */ - if (a.frac < b.frac) { - exp -=3D 1; - shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, &n1, &n0); - } else { - shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, &n1, &n0); - } - q =3D udiv_qrnnd(&r, n1, n0, b.frac); - - /* Set lsb if there is a remainder, to set inexact. */ - a.frac =3D q | (r !=3D 0); - a.sign =3D sign; - a.exp =3D exp; - return a; - } - /* handle all the NaN cases */ - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - /* 0/0 or Inf/Inf */ - if (a.cls =3D=3D b.cls - && - (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero)) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - /* Inf / x or 0 / x */ - if (a.cls =3D=3D float_class_inf || a.cls =3D=3D float_class_zero) { - a.sign =3D sign; - return a; - } - /* Div 0 =3D> Inf */ - if (b.cls =3D=3D float_class_zero) { - float_raise(float_flag_divbyzero, s); - a.cls =3D float_class_inf; - a.sign =3D sign; - return a; - } - /* Div by Inf */ - if (b.cls =3D=3D float_class_inf) { - a.cls =3D float_class_zero; - a.sign =3D sign; - return a; - } - g_assert_not_reached(); -} - float16 float16_div(float16 a, float16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); - pr =3D div_floats(pa, pb, status); + pr =3D parts_div(&pa, &pb, status); =20 - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR soft_f32_div(float32 a, float32 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); - pr =3D div_floats(pa, pb, status); + pr =3D parts_div(&pa, &pb, status); =20 - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_f64_div(float64 a, float64 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); - pr =3D div_floats(pa, pb, status); + pr =3D parts_div(&pa, &pb, status); =20 - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } =20 static float hard_f32_div(float a, float b) @@ -1984,20 +2005,28 @@ float64_div(float64 a, float64 b, float_status *s) f64_div_pre, f64_div_post); } =20 -/* - * Returns the result of dividing the bfloat16 - * value `a' by the corresponding value `b'. - */ - -bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) +bfloat16 QEMU_FLATTEN +bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; =20 bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); - pr =3D div_floats(pa, pb, status); + pr =3D parts_div(&pa, &pb, status); =20 - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); +} + +float128 QEMU_FLATTEN +float128_div(float128 a, float128 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr =3D parts_div(&pa, &pb, status); + + return float128_round_pack_canonical(pr, status); } =20 /* @@ -7122,93 +7151,6 @@ float128 float128_round_to_int(float128 a, float_sta= tus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of dividing the quadruple-precision floating-point va= lue -| `a' by the corresponding value `b'. The operation is performed accordin= g to -| the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_div(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2; - uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - bSig1 =3D extractFloat128Frac1( b ); - bSig0 =3D extractFloat128Frac0( b ); - bExp =3D extractFloat128Exp( b ); - bSign =3D extractFloat128Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, b, status); - } - if ( bExp =3D=3D 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - goto invalid; - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( bExp =3D=3D 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return packFloat128( zSign, 0, 0, 0 ); - } - if ( bExp =3D=3D 0 ) { - if ( ( bSig0 | bSig1 ) =3D=3D 0 ) { - if ( ( aExp | aSig0 | aSig1 ) =3D=3D 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - float_raise(float_flag_divbyzero, status); - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - if ( aExp =3D=3D 0 ) { - if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return packFloat128( zSign, 0, 0= , 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - zExp =3D aExp - bExp + 0x3FFD; - shortShift128Left( - aSig0 | UINT64_C(0x0001000000000000), aSig1, 15, &aSig0, &aSig1 ); - shortShift128Left( - bSig0 | UINT64_C(0x0001000000000000), bSig1, 15, &bSig0, &bSig1 ); - if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) { - shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 ); - ++zExp; - } - zSig0 =3D estimateDiv128To64( aSig0, aSig1, bSig0 ); - mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 ); - sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 ); - } - zSig1 =3D estimateDiv128To64( rem1, rem2, bSig0 ); - if ( ( zSig1 & 0x3FFF ) <=3D 4 ) { - mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 ); - sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3= ); - } - zSig1 |=3D ( ( rem1 | rem2 | rem3 ) !=3D 0 ); - } - shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2= ); - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the quadruple-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a203811299..f8165d92f9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -539,3 +539,58 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, Flo= atPartsN *b, parts_default_nan(a, s); return a; } + +/* + * Returns the result of dividing the floating-point value `a' by the + * corresponding value `b'. The operation is performed according to + * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ +static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, + float_status *s) +{ + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + bool sign =3D a->sign ^ b->sign; + + if (likely(ab_mask =3D=3D float_cmask_normal)) { + a->sign =3D sign; + a->exp -=3D b->exp + frac_div(a, b); + return a; + } + + /* 0/0 or Inf/Inf =3D> NaN */ + if (unlikely(ab_mask =3D=3D float_cmask_zero) || + unlikely(ab_mask =3D=3D float_cmask_inf)) { + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + + /* All the NaN cases */ + if (unlikely(ab_mask & float_cmask_anynan)) { + return parts_pick_nan(a, b, s); + } + + a->sign =3D sign; + + /* Inf / X */ + if (a->cls =3D=3D float_class_inf) { + return a; + } + + /* 0 / X */ + if (a->cls =3D=3D float_class_zero) { + return a; + } + + /* X / Inf */ + if (b->cls =3D=3D float_class_inf) { + a->cls =3D float_class_zero; + return a; + } + + /* X / 0 =3D> Inf */ + g_assert(b->cls =3D=3D float_class_zero); + float_raise(float_flag_divbyzero, s); + a->cls =3D float_class_inf; + return a; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440993; cv=none; d=zohomail.com; s=zohoarc; b=V19T138H0S88fN53H6ecwYFJ0XqOn3muR1vMyQlfS/hQr8v4/tvzzXx7famHqTe5q4YvAeaLq3RvS5gU3iLvF9zVbnpq24Ydj7nZb5LPLujBzleblc5bqKvmIcRp92pSLCAitY3zk1tRQKmlq0IV2a31GOrKUnCjz0uQTFab3pw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440993; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Split out parts_float_to_ahp and parts_float_to_float. Convert to pointers. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 174 ++++++++++++++++++++++++++++-------------------- 1 file changed, 101 insertions(+), 73 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8efa52f7ec..06fac8f41c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2036,83 +2036,105 @@ float128_div(float128 a, float128 b, float_status = *status) * conversion is performed according to the IEC/IEEE Standard for * Binary Floating-Point Arithmetic. * - * The float_to_float helper only needs to take care of raising - * invalid exceptions and handling the conversion on NaNs. + * Usually this only needs to take care of raising invalid exceptions + * and handling the conversion on NaNs. */ =20 -static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, - float_status *s) +static void parts_float_to_ahp(FloatParts64 *a, float_status *s) { - if (dstf->arm_althp) { - switch (a.cls) { - case float_class_qnan: - case float_class_snan: - /* There is no NaN in the destination format. Raise Invalid - * and return a zero with the sign of the input NaN. - */ - float_raise(float_flag_invalid, s); - a.cls =3D float_class_zero; - a.frac =3D 0; - a.exp =3D 0; - break; + switch (a->cls) { + case float_class_qnan: + case float_class_snan: + /* + * There is no NaN in the destination format. Raise Invalid + * and return a zero with the sign of the input NaN. + */ + float_raise(float_flag_invalid, s); + a->cls =3D float_class_zero; + break; =20 - case float_class_inf: - /* There is no Inf in the destination format. Raise Invalid - * and return the maximum normal with the correct sign. - */ - float_raise(float_flag_invalid, s); - a.cls =3D float_class_normal; - a.exp =3D dstf->exp_max; - a.frac =3D ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; - break; + case float_class_inf: + /* + * There is no Inf in the destination format. Raise Invalid + * and return the maximum normal with the correct sign. + */ + float_raise(float_flag_invalid, s); + a->cls =3D float_class_normal; + a->exp =3D float16_params_ahp.exp_max; + a->frac =3D MAKE_64BIT_MASK(float16_params_ahp.frac_shift, + float16_params_ahp.frac_size + 1); + break; =20 - default: - break; - } - } else if (is_nan(a.cls)) { - parts_return_nan(&a, s); + case float_class_normal: + case float_class_zero: + break; + + default: + g_assert_not_reached(); } - return a; } =20 +static void parts64_float_to_float(FloatParts64 *a, float_status *s) +{ + if (is_nan(a->cls)) { + parts_return_nan(a, s); + } +} + +static void parts128_float_to_float(FloatParts128 *a, float_status *s) +{ + if (is_nan(a->cls)) { + parts_return_nan(a, s); + } +} + +#define parts_float_to_float(P, S) \ + PARTS_GENERIC_64_128(float_to_float, P)(P, S) + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; =20 - float16a_unpack_canonical(&pa, a, s, fmt16); - pr =3D float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(&pr, s); + float16a_unpack_canonical(&p, a, s, fmt16); + parts_float_to_float(&p, s); + return float32_round_pack_canonical(&p, s); } =20 float64 float16_to_float64(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; =20 - float16a_unpack_canonical(&pa, a, s, fmt16); - pr =3D float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(&pr, s); + float16a_unpack_canonical(&p, a, s, fmt16); + parts_float_to_float(&p, s); + return float64_round_pack_canonical(&p, s); } =20 float16 float32_to_float16(float32 a, bool ieee, float_status *s) { - const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; + const FloatFmt *fmt; =20 - float32_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(&pr, s, fmt16); + float32_unpack_canonical(&p, a, s); + if (ieee) { + parts_float_to_float(&p, s); + fmt =3D &float16_params; + } else { + parts_float_to_ahp(&p, s); + fmt =3D &float16_params_ahp; + } + return float16a_round_pack_canonical(&p, s, fmt); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_float32_to_float64(float32 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float32_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(&pr, s); + float32_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float64_round_pack_canonical(&p, s); } =20 float64 float32_to_float64(float32 a, float_status *s) @@ -2133,57 +2155,63 @@ float64 float32_to_float64(float32 a, float_status = *s) =20 float16 float64_to_float16(float64 a, bool ieee, float_status *s) { - const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; + const FloatFmt *fmt; =20 - float64_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(&pr, s, fmt16); + float64_unpack_canonical(&p, a, s); + if (ieee) { + parts_float_to_float(&p, s); + fmt =3D &float16_params; + } else { + parts_float_to_ahp(&p, s); + fmt =3D &float16_params_ahp; + } + return float16a_round_pack_canonical(&p, s, fmt); } =20 float32 float64_to_float32(float64 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float64_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(&pr, s); + float64_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float32_round_pack_canonical(&p, s); } =20 float32 bfloat16_to_float32(bfloat16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - bfloat16_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(&pr, s); + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float32_round_pack_canonical(&p, s); } =20 float64 bfloat16_to_float64(bfloat16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - bfloat16_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(&pr, s); + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float64_round_pack_canonical(&p, s); } =20 bfloat16 float32_to_bfloat16(float32 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float32_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(&pr, s); + float32_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return bfloat16_round_pack_canonical(&p, s); } =20 bfloat16 float64_to_bfloat16(float64 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float64_unpack_canonical(&pa, a, s); - pr =3D float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(&pr, s); + float64_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return bfloat16_round_pack_canonical(&p, s); } =20 /* --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441108; cv=none; d=zohomail.com; s=zohoarc; b=ZeCQy0XzSAFlrPdR6ES/PcINuMPkW/l46u2gaqSAk0wU9anjsWn5LrTiGQrNZbHnPGJdxjxhl43SYEQX/yvw6N5Wmzi6LmcTMYbzg7ULYUqxCfiCE167yLEzl60ukFVaisRTMJM9KN4d7BRnfjr7PHfDpMUBt+Ud9pPLO0mVNWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441108; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Introduce parts_float_to_float_widen and parts_float_to_float_narrow. Use them for float128_to_float{32,64} and float{32,64}_to_float128. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 203 ++++++++++++++++-------------------------------- 1 file changed, 69 insertions(+), 134 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 06fac8f41c..1b86111279 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2091,6 +2091,35 @@ static void parts128_float_to_float(FloatParts128 *a= , float_status *s) #define parts_float_to_float(P, S) \ PARTS_GENERIC_64_128(float_to_float, P)(P, S) =20 +static void parts_float_to_float_narrow(FloatParts64 *a, FloatParts128 *b, + float_status *s) +{ + a->cls =3D b->cls; + a->sign =3D b->sign; + a->exp =3D b->exp; + + if (a->cls =3D=3D float_class_normal) { + frac_truncjam(a, b); + } else if (is_nan(a->cls)) { + /* Discard the low bits of the NaN. */ + a->frac =3D b->frac_hi; + parts_return_nan(a, s); + } +} + +static void parts_float_to_float_widen(FloatParts128 *a, FloatParts64 *b, + float_status *s) +{ + a->cls =3D b->cls; + a->sign =3D b->sign; + a->exp =3D b->exp; + frac_widen(a, b); + + if (is_nan(a->cls)) { + parts_return_nan(a, s); + } +} + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; @@ -2214,6 +2243,46 @@ bfloat16 float64_to_bfloat16(float64 a, float_status= *s) return bfloat16_round_pack_canonical(&p, s); } =20 +float32 float128_to_float32(float128 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float128_unpack_canonical(&p128, a, s); + parts_float_to_float_narrow(&p64, &p128, s); + return float32_round_pack_canonical(&p64, s); +} + +float64 float128_to_float64(float128 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float128_unpack_canonical(&p128, a, s); + parts_float_to_float_narrow(&p64, &p128, s); + return float64_round_pack_canonical(&p64, s); +} + +float128 float32_to_float128(float32 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float32_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return float128_round_pack_canonical(&p128, s); +} + +float128 float64_to_float128(float64 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float64_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return float128_round_pack_canonical(&p128, s); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. The operation is performed @@ -5174,38 +5243,6 @@ floatx80 float32_to_floatx80(float32 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float32_to_float128(float32 a, float_status *status) -{ - bool aSign; - int aExp; - uint32_t aSig; - - a =3D float32_squash_input_denormal(a, status); - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return commonNaNToFloat128(float32ToCommonNaN(a, status), stat= us); - } - return packFloat128( aSign, 0x7FFF, 0, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat128( aSign, 0, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat128( aSign, aExp + 0x3F80, ( (uint64_t) aSig )<<25, 0 = ); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5479,40 +5516,6 @@ floatx80 float64_to_floatx80(float64 a, float_status= *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the quadruple-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float64_to_float128(float64 a, float_status *status) -{ - bool aSign; - int aExp; - uint64_t aSig, zSig0, zSig1; - - a =3D float64_squash_input_denormal(a, status); - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return commonNaNToFloat128(float64ToCommonNaN(a, status), stat= us); - } - return packFloat128( aSign, 0x7FFF, 0, 0 ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat128( aSign, 0, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - shift128Right( aSig, 0, 4, &zSig0, &zSig1 ); - return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 ); - -} - - /*------------------------------------------------------------------------= ---- | Returns the remainder of the double-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -6914,74 +6917,6 @@ uint32_t float128_to_uint32(float128 a, float_status= *status) return res; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the single-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float128_to_float32(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - uint32_t zSig; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return commonNaNToFloat32(float128ToCommonNaN(a, status), stat= us); - } - return packFloat32( aSign, 0xFF, 0 ); - } - aSig0 |=3D ( aSig1 !=3D 0 ); - shift64RightJamming( aSig0, 18, &aSig0 ); - zSig =3D aSig0; - if ( aExp || zSig ) { - zSig |=3D 0x40000000; - aExp -=3D 0x3F81; - } - return roundAndPackFloat32(aSign, aExp, zSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float128_to_float64(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return commonNaNToFloat64(float128ToCommonNaN(a, status), stat= us); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 ); - aSig0 |=3D ( aSig1 !=3D 0 ); - if ( aExp || aSig0 ) { - aSig0 |=3D UINT64_C(0x4000000000000000); - aExp -=3D 0x3C01; - } - return roundAndPackFloat64(aSign, aExp, aSig0, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point | value `a' to the extended double-precision floating-point format. The --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441246; cv=none; d=zohomail.com; s=zohoarc; b=lRcTK4Z6VT36uM6t03Th4jRQa8ts30j6sl/auPtcnc9UqgYDzPot6wa5/SIiONCN0G7NlC++v1fcZn7ojUYjyY31W7yeZFJZR1mXhLlkQBDBh3L2oZmVgoRzhv46PNjxSSe0Zeuok0krFbzmJTj9EOMV6oIzsUrwwVgyo+K3D8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441246; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lD4M3xdqIE8r914VjTd/jttQJ/e/mxQ3BCpgAvIfUlU=; b=lrXR/bB80869RYewzFzzqEvEXCYXWX7bq5SMiAwFyf3YpHKnA5TJZHtAlZTgHTg4Ssfpox5zIKUv5Mgu0mDm/Dra6soRjxmy9fdQRrE1mRaANcBrD3aDHmeTKXQ3fRzPs0WkhTj7vYFCgZgyn6i5i7B3krS2cVcC1pclkHN5yDA= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the same time, convert to pointers, split out parts$N_round_to_int_normal, define a macro for parts_round_to_int using QEMU_GENERIC. This necessarily meant some rearrangement to the rount_to_{,u}int_and_pack routines, so go ahead and convert to parts_round_to_int_normal, which in turn allows cleaning up of the raised exception handling. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 434 ++++++++++---------------------------- fpu/softfloat-parts.c.inc | 157 ++++++++++++++ 2 files changed, 263 insertions(+), 328 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 1b86111279..ce96ea753c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -810,6 +810,24 @@ static FloatParts128 *parts128_div(FloatParts128 *a, F= loatParts128 *b, #define parts_div(A, B, S) \ PARTS_GENERIC_64_128(div, A)(A, B, S) =20 +static bool parts64_round_to_int_normal(FloatParts64 *a, FloatRoundMode rm, + int scale, int frac_size); +static bool parts128_round_to_int_normal(FloatParts128 *a, FloatRoundMode = r, + int scale, int frac_size); + +#define parts_round_to_int_normal(A, R, C, F) \ + PARTS_GENERIC_64_128(round_to_int_normal, A)(A, R, C, F) + +static void parts64_round_to_int(FloatParts64 *a, FloatRoundMode rm, + int scale, float_status *s, + const FloatFmt *fmt); +static void parts128_round_to_int(FloatParts128 *a, FloatRoundMode r, + int scale, float_status *s, + const FloatFmt *fmt); + +#define parts_round_to_int(A, R, C, S, F) \ + PARTS_GENERIC_64_128(round_to_int, A)(A, R, C, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2284,153 +2302,52 @@ float128 float64_to_float128(float64 a, float_stat= us *s) } =20 /* - * Rounds the floating-point value `a' to an integer, and returns the - * result as a floating-point value. The operation is performed - * according to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic. + * Round to integral value */ =20 -static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, - int scale, float_status *s) -{ - switch (a.cls) { - case float_class_qnan: - case float_class_snan: - parts_return_nan(&a, s); - break; - - case float_class_zero: - case float_class_inf: - /* already "integral" */ - break; - - case float_class_normal: - scale =3D MIN(MAX(scale, -0x10000), 0x10000); - a.exp +=3D scale; - - if (a.exp >=3D DECOMPOSED_BINARY_POINT) { - /* already integral */ - break; - } - if (a.exp < 0) { - bool one; - /* all fractional */ - float_raise(float_flag_inexact, s); - switch (rmode) { - case float_round_nearest_even: - one =3D a.exp =3D=3D -1 && a.frac > DECOMPOSED_IMPLICIT_BI= T; - break; - case float_round_ties_away: - one =3D a.exp =3D=3D -1 && a.frac >=3D DECOMPOSED_IMPLICIT= _BIT; - break; - case float_round_to_zero: - one =3D false; - break; - case float_round_up: - one =3D !a.sign; - break; - case float_round_down: - one =3D a.sign; - break; - case float_round_to_odd: - one =3D true; - break; - default: - g_assert_not_reached(); - } - - if (one) { - a.frac =3D DECOMPOSED_IMPLICIT_BIT; - a.exp =3D 0; - } else { - a.cls =3D float_class_zero; - } - } else { - uint64_t frac_lsb =3D DECOMPOSED_IMPLICIT_BIT >> a.exp; - uint64_t frac_lsbm1 =3D frac_lsb >> 1; - uint64_t rnd_even_mask =3D (frac_lsb - 1) | frac_lsb; - uint64_t rnd_mask =3D rnd_even_mask >> 1; - uint64_t inc; - - switch (rmode) { - case float_round_nearest_even: - inc =3D ((a.frac & rnd_even_mask) !=3D frac_lsbm1 ? frac_l= sbm1 : 0); - break; - case float_round_ties_away: - inc =3D frac_lsbm1; - break; - case float_round_to_zero: - inc =3D 0; - break; - case float_round_up: - inc =3D a.sign ? 0 : rnd_mask; - break; - case float_round_down: - inc =3D a.sign ? rnd_mask : 0; - break; - case float_round_to_odd: - inc =3D a.frac & frac_lsb ? 0 : rnd_mask; - break; - default: - g_assert_not_reached(); - } - - if (a.frac & rnd_mask) { - float_raise(float_flag_inexact, s); - if (uadd64_overflow(a.frac, inc, &a.frac)) { - a.frac >>=3D 1; - a.frac |=3D DECOMPOSED_IMPLICIT_BIT; - a.exp++; - } - a.frac &=3D ~rnd_mask; - } - } - break; - default: - g_assert_not_reached(); - } - return a; -} - float16 float16_round_to_int(float16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float16_unpack_canonical(&pa, a, s); - pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return float16_round_pack_canonical(&pr, s); + float16_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float16_params); + return float16_round_pack_canonical(&p, s); } =20 float32 float32_round_to_int(float32 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float32_unpack_canonical(&pa, a, s); - pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return float32_round_pack_canonical(&pr, s); + float32_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float32_params); + return float32_round_pack_canonical(&p, s); } =20 float64 float64_round_to_int(float64 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float64_unpack_canonical(&pa, a, s); - pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return float64_round_pack_canonical(&pr, s); + float64_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float64_params); + return float64_round_pack_canonical(&p, s); } =20 -/* - * Rounds the bfloat16 value `a' to an integer, and returns the - * result as a bfloat16 value. - */ - bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - bfloat16_unpack_canonical(&pa, a, s); - pr =3D round_to_int(pa, s->float_rounding_mode, 0, s); - return bfloat16_round_pack_canonical(&pr, s); + bfloat16_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &bfloat16_params); + return bfloat16_round_pack_canonical(&p, s); +} + +float128 float128_round_to_int(float128 a, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float128_params); + return float128_round_pack_canonical(&p, s); } =20 /* @@ -2444,48 +2361,58 @@ bfloat16 bfloat16_round_to_int(bfloat16 a, float_st= atus *s) * is returned. */ =20 -static int64_t round_to_int_and_pack(FloatParts64 in, FloatRoundMode rmode, +static int64_t round_to_int_and_pack(FloatParts64 p, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) { + int flags =3D 0; uint64_t r; - int orig_flags =3D get_float_exception_flags(s); - FloatParts64 p =3D round_to_int(in, rmode, scale, s); =20 switch (p.cls) { case float_class_snan: case float_class_qnan: - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return max; + flags =3D float_flag_invalid; + r =3D max; + break; + case float_class_inf: - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return p.sign ? min : max; + flags =3D float_flag_invalid; + r =3D p.sign ? min : max; + break; + case float_class_zero: return 0; + case float_class_normal: + /* TODO: 62 =3D N - 2, frac_size for rounding */ + if (parts_round_to_int_normal(&p, rmode, scale, 62)) { + flags =3D float_flag_inexact; + } + if (p.exp <=3D DECOMPOSED_BINARY_POINT) { r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); } else { r =3D UINT64_MAX; } if (p.sign) { - if (r <=3D -(uint64_t) min) { - return -r; + if (r <=3D -(uint64_t)min) { + r =3D -r; } else { - s->float_exception_flags =3D orig_flags | float_flag_inval= id; - return min; - } - } else { - if (r <=3D max) { - return r; - } else { - s->float_exception_flags =3D orig_flags | float_flag_inval= id; - return max; + flags =3D float_flag_invalid; + r =3D min; } + } else if (r > max) { + flags =3D float_flag_invalid; + r =3D max; } + break; + default: g_assert_not_reached(); } + + float_raise(flags, s); + return r; } =20 int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2748,49 +2675,59 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a,= float_status *s) * flag. */ =20 -static uint64_t round_to_uint_and_pack(FloatParts64 in, FloatRoundMode rmo= de, +static uint64_t round_to_uint_and_pack(FloatParts64 p, FloatRoundMode rmod= e, int scale, uint64_t max, float_status *s) { - int orig_flags =3D get_float_exception_flags(s); - FloatParts64 p =3D round_to_int(in, rmode, scale, s); + int flags =3D 0; uint64_t r; =20 switch (p.cls) { case float_class_snan: case float_class_qnan: - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return max; + flags =3D float_flag_invalid; + r =3D max; + break; + case float_class_inf: - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return p.sign ? 0 : max; + flags =3D float_flag_invalid; + r =3D p.sign ? 0 : max; + break; + case float_class_zero: return 0; + case float_class_normal: + /* TODO: 62 =3D N - 2, frac_size for rounding */ + if (parts_round_to_int_normal(&p, rmode, scale, 62)) { + flags =3D float_flag_inexact; + if (p.cls =3D=3D float_class_zero) { + r =3D 0; + break; + } + } + if (p.sign) { - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return 0; - } - - if (p.exp <=3D DECOMPOSED_BINARY_POINT) { - r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); + flags =3D float_flag_invalid; + r =3D 0; + } else if (p.exp > DECOMPOSED_BINARY_POINT) { + flags =3D float_flag_invalid; + r =3D max; } else { - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return max; + r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); + if (r > max) { + flags =3D float_flag_invalid; + r =3D max; + } } + break; =20 - /* For uint64 this will never trip, but if p.exp is too large - * to shift a decomposed fraction we shall have exited via the - * 3rd leg above. - */ - if (r > max) { - s->float_exception_flags =3D orig_flags | float_flag_invalid; - return max; - } - return r; default: g_assert_not_reached(); } + + float_raise(flags, s); + return r; } =20 uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -6955,165 +6892,6 @@ floatx80 float128_to_floatx80(float128 a, float_sta= tus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Rounds the quadruple-precision floating-point value `a' to an integer, a= nd -| returns the result as a quadruple-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_round_to_int(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t lastBitMask, roundBitsMask; - float128 z; - - aExp =3D extractFloat128Exp( a ); - if ( 0x402F <=3D aExp ) { - if ( 0x406F <=3D aExp ) { - if ( ( aExp =3D=3D 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a = ) ) - ) { - return propagateFloat128NaN(a, a, status); - } - return a; - } - lastBitMask =3D 1; - lastBitMask =3D ( lastBitMask<<( 0x406E - aExp ) )<<1; - roundBitsMask =3D lastBitMask - 1; - z =3D a; - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( lastBitMask ) { - add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low = ); - if ( ( z.low & roundBitsMask ) =3D=3D 0 ) z.low &=3D ~ las= tBitMask; - } - else { - if ( (int64_t) z.low < 0 ) { - ++z.high; - if ( (uint64_t) ( z.low<<1 ) =3D=3D 0 ) z.high &=3D ~1; - } - } - break; - case float_round_ties_away: - if (lastBitMask) { - add128(z.high, z.low, 0, lastBitMask >> 1, &z.high, &z.low= ); - } else { - if ((int64_t) z.low < 0) { - ++z.high; - } - } - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat128Sign(z)) { - add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low); - } - break; - case float_round_down: - if (extractFloat128Sign(z)) { - add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low); - } - break; - case float_round_to_odd: - /* - * Note that if lastBitMask =3D=3D 0, the last bit is the lsb - * of high, and roundBitsMask =3D=3D -1. - */ - if ((lastBitMask ? z.low & lastBitMask : z.high & 1) =3D=3D 0)= { - add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low); - } - break; - default: - abort(); - } - z.low &=3D ~ roundBitsMask; - } - else { - if ( aExp < 0x3FFF ) { - if ( ( ( (uint64_t) ( a.high<<1 ) ) | a.low ) =3D=3D 0 ) retur= n a; - float_raise(float_flag_inexact, status); - aSign =3D extractFloat128Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp =3D=3D 0x3FFE ) - && ( extractFloat128Frac0( a ) - | extractFloat128Frac1( a ) ) - ) { - return packFloat128( aSign, 0x3FFF, 0, 0 ); - } - break; - case float_round_ties_away: - if (aExp =3D=3D 0x3FFE) { - return packFloat128(aSign, 0x3FFF, 0, 0); - } - break; - case float_round_down: - return - aSign ? packFloat128( 1, 0x3FFF, 0, 0 ) - : packFloat128( 0, 0, 0, 0 ); - case float_round_up: - return - aSign ? packFloat128( 1, 0, 0, 0 ) - : packFloat128( 0, 0x3FFF, 0, 0 ); - - case float_round_to_odd: - return packFloat128(aSign, 0x3FFF, 0, 0); - - case float_round_to_zero: - break; - } - return packFloat128( aSign, 0, 0, 0 ); - } - lastBitMask =3D 1; - lastBitMask <<=3D 0x402F - aExp; - roundBitsMask =3D lastBitMask - 1; - z.low =3D 0; - z.high =3D a.high; - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z.high +=3D lastBitMask>>1; - if ( ( ( z.high & roundBitsMask ) | a.low ) =3D=3D 0 ) { - z.high &=3D ~ lastBitMask; - } - break; - case float_round_ties_away: - z.high +=3D lastBitMask>>1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat128Sign(z)) { - z.high |=3D ( a.low !=3D 0 ); - z.high +=3D roundBitsMask; - } - break; - case float_round_down: - if (extractFloat128Sign(z)) { - z.high |=3D (a.low !=3D 0); - z.high +=3D roundBitsMask; - } - break; - case float_round_to_odd: - if ((z.high & lastBitMask) =3D=3D 0) { - z.high |=3D (a.low !=3D 0); - z.high +=3D roundBitsMask; - } - break; - default: - abort(); - } - z.high &=3D ~ roundBitsMask; - } - if ( ( z.low !=3D a.low ) || ( z.high !=3D a.high ) ) { - float_raise(float_flag_inexact, status); - } - return z; - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the quadruple-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index f8165d92f9..b2c4624d8c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -594,3 +594,160 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, Float= PartsN *b, a->cls =3D float_class_inf; return a; } + +/* + * Rounds the floating-point value `a' to an integer, and returns the + * result as a floating-point value. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + * + * parts_round_to_int_normal is an internal helper function for + * normal numbers only, returning true for inexact but not directly + * raising float_flag_inexact. + */ +static bool partsN(round_to_int_normal)(FloatPartsN *a, FloatRoundMode rmo= de, + int scale, int frac_size) +{ + uint64_t frac_lsb, frac_lsbm1, rnd_even_mask, rnd_mask, inc; + int shift_adj; + + scale =3D MIN(MAX(scale, -0x10000), 0x10000); + a->exp +=3D scale; + + if (a->exp < 0) { + bool one; + + /* All fractional */ + switch (rmode) { + case float_round_nearest_even: + one =3D false; + if (a->exp =3D=3D -1) { + FloatPartsN tmp; + /* Shift left one, discarding DECOMPOSED_IMPLICIT_BIT */ + frac_add(&tmp, a, a); + /* Anything remaining means frac > 0.5. */ + one =3D !frac_eqz(&tmp); + } + break; + case float_round_ties_away: + one =3D a->exp =3D=3D -1; + break; + case float_round_to_zero: + one =3D false; + break; + case float_round_up: + one =3D !a->sign; + break; + case float_round_down: + one =3D a->sign; + break; + case float_round_to_odd: + one =3D true; + break; + default: + g_assert_not_reached(); + } + + frac_clear(a); + a->exp =3D 0; + if (one) { + a->frac_hi =3D DECOMPOSED_IMPLICIT_BIT; + } else { + a->cls =3D float_class_zero; + } + return true; + } + + if (a->exp >=3D frac_size) { + /* All integral */ + return false; + } + + if (N > 64 && a->exp < N - 64) { + /* + * Rounding is not in the low word -- shift lsb to bit 2, + * which leaves room for sticky and rounding bit. + */ + shift_adj =3D (N - 1) - (a->exp + 2); + frac_shrjam(a, shift_adj); + frac_lsb =3D 1 << 2; + } else { + shift_adj =3D 0; + frac_lsb =3D DECOMPOSED_IMPLICIT_BIT >> (a->exp & 63); + } + + frac_lsbm1 =3D frac_lsb >> 1; + rnd_mask =3D frac_lsb - 1; + rnd_even_mask =3D rnd_mask | frac_lsb; + + if (!(a->frac_lo & rnd_mask)) { + /* Fractional bits already clear, undo the shift above. */ + frac_shl(a, shift_adj); + return false; + } + + switch (rmode) { + case float_round_nearest_even: + inc =3D ((a->frac_lo & rnd_even_mask) !=3D frac_lsbm1 ? frac_lsbm1= : 0); + break; + case float_round_ties_away: + inc =3D frac_lsbm1; + break; + case float_round_to_zero: + inc =3D 0; + break; + case float_round_up: + inc =3D a->sign ? 0 : rnd_mask; + break; + case float_round_down: + inc =3D a->sign ? rnd_mask : 0; + break; + case float_round_to_odd: + inc =3D a->frac_lo & frac_lsb ? 0 : rnd_mask; + break; + default: + g_assert_not_reached(); + } + + if (shift_adj =3D=3D 0) { + if (frac_addi(a, a, inc)) { + frac_shr(a, 1); + a->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + a->exp++; + } + a->frac_lo &=3D ~rnd_mask; + } else { + frac_addi(a, a, inc); + a->frac_lo &=3D ~rnd_mask; + /* Be careful shifting back, not to overflow */ + frac_shl(a, shift_adj - 1); + if (a->frac_hi & DECOMPOSED_IMPLICIT_BIT) { + a->exp++; + } else { + frac_add(a, a, a); + } + } + return true; +} + +static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode, + int scale, float_status *s, + const FloatFmt *fmt) +{ + switch (a->cls) { + case float_class_qnan: + case float_class_snan: + parts_return_nan(a, s); + break; + case float_class_zero: + case float_class_inf: + break; + case float_class_normal: + if (parts_round_to_int_normal(a, rmode, scale, fmt->frac_size)) { + float_raise(float_flag_inexact, s); + } + break; + default: + g_assert_not_reached(); + } +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440396; cv=none; d=zohomail.com; s=zohoarc; b=je3VHPXh9gBaVzw69t5XzsNy1rIW1LsK5WYVjOuD9p4Itu4oHYWQzyTH3pjBWtO8EjhrWTpaUSFWkhhuNw995eccm0wy5XhPxmgbcSqiM8gC1Oz6nez3MOt7Ep0HwucKNbMterBSFJR7PzP7siOW3hqlWxoLODqB7L4YZdDA6po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440396; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_float_to_sint. Reimplement float128_to_int{32,64}{_round_to_zero} with FloatParts128. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 365 +++++++++----------------------------- fpu/softfloat-parts.c.inc | 64 +++++++ 2 files changed, 145 insertions(+), 284 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ce96ea753c..ac8e726935 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -828,6 +828,16 @@ static void parts128_round_to_int(FloatParts128 *a, Fl= oatRoundMode r, #define parts_round_to_int(A, R, C, S, F) \ PARTS_GENERIC_64_128(round_to_int, A)(A, R, C, S, F) =20 +static int64_t parts64_float_to_sint(FloatParts64 *p, FloatRoundMode rmode, + int scale, int64_t min, int64_t max, + float_status *s); +static int64_t parts128_float_to_sint(FloatParts128 *p, FloatRoundMode rmo= de, + int scale, int64_t min, int64_t max, + float_status *s); + +#define parts_float_to_sint(P, R, Z, MN, MX, S) \ + PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2351,69 +2361,8 @@ float128 float128_round_to_int(float128 a, float_sta= tus *s) } =20 /* - * Returns the result of converting the floating-point value `a' to - * the two's complement integer format. The conversion is performed - * according to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic---which means in particular that the conversion is - * rounded according to the current rounding mode. If `a' is a NaN, - * the largest positive integer is returned. Otherwise, if the - * conversion overflows, the largest integer with the same sign as `a' - * is returned. -*/ - -static int64_t round_to_int_and_pack(FloatParts64 p, FloatRoundMode rmode, - int scale, int64_t min, int64_t max, - float_status *s) -{ - int flags =3D 0; - uint64_t r; - - switch (p.cls) { - case float_class_snan: - case float_class_qnan: - flags =3D float_flag_invalid; - r =3D max; - break; - - case float_class_inf: - flags =3D float_flag_invalid; - r =3D p.sign ? min : max; - break; - - case float_class_zero: - return 0; - - case float_class_normal: - /* TODO: 62 =3D N - 2, frac_size for rounding */ - if (parts_round_to_int_normal(&p, rmode, scale, 62)) { - flags =3D float_flag_inexact; - } - - if (p.exp <=3D DECOMPOSED_BINARY_POINT) { - r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - } else { - r =3D UINT64_MAX; - } - if (p.sign) { - if (r <=3D -(uint64_t)min) { - r =3D -r; - } else { - flags =3D float_flag_invalid; - r =3D min; - } - } else if (r > max) { - flags =3D float_flag_invalid; - r =3D max; - } - break; - - default: - g_assert_not_reached(); - } - - float_raise(flags, s); - return r; -} + * Floating-point to signed integer conversions + */ =20 int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) @@ -2421,7 +2370,7 @@ int8_t float16_to_int8_scalbn(float16 a, FloatRoundMo= de rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT8_MIN, INT8_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT8_MIN, INT8_MAX, s); } =20 int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2430,7 +2379,7 @@ int16_t float16_to_int16_scalbn(float16 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2439,7 +2388,7 @@ int32_t float16_to_int32_scalbn(float16 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2448,7 +2397,7 @@ int64_t float16_to_int64_scalbn(float16 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2457,7 +2406,7 @@ int16_t float32_to_int16_scalbn(float32 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float32_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2466,7 +2415,7 @@ int32_t float32_to_int32_scalbn(float32 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float32_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2475,7 +2424,7 @@ int64_t float32_to_int64_scalbn(float32 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float32_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2484,7 +2433,7 @@ int16_t float64_to_int16_scalbn(float64 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float64_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); } =20 int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2493,7 +2442,7 @@ int32_t float64_to_int32_scalbn(float64 a, FloatRound= Mode rmode, int scale, FloatParts64 p; =20 float64_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); } =20 int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2502,7 +2451,52 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoun= dMode rmode, int scale, FloatParts64 p; =20 float64_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); +} + +int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, + float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); +} + +int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, + float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); +} + +int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, + float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); +} + +static int32_t float128_to_int32_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); +} + +static int64_t float128_to_int64_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 int8_t float16_to_int8(float16 a, float_status *s) @@ -2555,6 +2549,16 @@ int64_t float64_to_int64(float64 a, float_status *s) return float64_to_int64_scalbn(a, s->float_rounding_mode, 0, s); } =20 +int32_t float128_to_int32(float128 a, float_status *s) +{ + return float128_to_int32_scalbn(a, s->float_rounding_mode, 0, s); +} + +int64_t float128_to_int64(float128 a, float_status *s) +{ + return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16_round_to_zero(float16 a, float_status *s) { return float16_to_int16_scalbn(a, float_round_to_zero, 0, s); @@ -2600,36 +2604,14 @@ int64_t float64_to_int64_round_to_zero(float64 a, f= loat_status *s) return float64_to_int64_scalbn(a, float_round_to_zero, 0, s); } =20 -/* - * Returns the result of converting the floating-point value `a' to - * the two's complement integer format. - */ - -int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, - float_status *s) +int32_t float128_to_int32_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return float128_to_int32_scalbn(a, float_round_to_zero, 0, s); } =20 -int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, - float_status *s) +int64_t float128_to_int64_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); -} - -int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int sca= le, - float_status *s) -{ - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return float128_to_int64_scalbn(a, float_round_to_zero, 0, s); } =20 int16_t bfloat16_to_int16(bfloat16 a, float_status *s) @@ -6553,191 +6535,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *st= atus) 0, zExp, zSig0, zSig1, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit two's complement integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, t= he -| largest integer with the same sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t float128_to_int32(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig0, aSig1; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - if ( ( aExp =3D=3D 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign =3D 0; - if ( aExp ) aSig0 |=3D UINT64_C(0x0001000000000000); - aSig0 |=3D ( aSig1 !=3D 0 ); - shiftCount =3D 0x4028 - aExp; - if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 ); - return roundAndPackInt32(aSign, aSig0, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit two's complement integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. If -| `a' is a NaN, the largest positive integer is returned. Otherwise, if t= he -| conversion overflows, the largest integer with the same sign as `a' is -| returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t float128_to_int32_round_to_zero(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig0, aSig1, savedASig; - int32_t z; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - aSig0 |=3D ( aSig1 !=3D 0 ); - if ( 0x401E < aExp ) { - if ( ( aExp =3D=3D 0x7FFF ) && aSig0 ) aSign =3D 0; - goto invalid; - } - else if ( aExp < 0x3FFF ) { - if (aExp || aSig0) { - float_raise(float_flag_inexact, status); - } - return 0; - } - aSig0 |=3D UINT64_C(0x0001000000000000); - shiftCount =3D 0x402F - aExp; - savedASig =3D aSig0; - aSig0 >>=3D shiftCount; - z =3D aSig0; - if ( aSign ) z =3D - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise(float_flag_invalid, status); - return aSign ? INT32_MIN : INT32_MAX; - } - if ( ( aSig0<>( ( - shiftCount ) & 63 ) ); - if ( (uint64_t) ( aSig1<>( - shiftCount ); - if ( aSig1 - || ( shiftCount && (uint64_t) ( aSig0<<( shiftCount & 63 ) ) = ) ) { - float_raise(float_flag_inexact, status); - } - } - if ( aSign ) z =3D - z; - return z; - -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point = value | `a' to the 64-bit unsigned integer format. The conversion is diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index b2c4624d8c..a897a5a743 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -751,3 +751,67 @@ static void partsN(round_to_int)(FloatPartsN *a, Float= RoundMode rmode, g_assert_not_reached(); } } + +/* + * Returns the result of converting the floating-point value `a' to + * the two's complement integer format. The conversion is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic---which means in particular that the conversion is + * rounded according to the current rounding mode. If `a' is a NaN, + * the largest positive integer is returned. Otherwise, if the + * conversion overflows, the largest integer with the same sign as `a' + * is returned. +*/ +static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, + int scale, int64_t min, int64_t max, + float_status *s) +{ + int flags =3D 0; + uint64_t r; + + switch (p->cls) { + case float_class_snan: + case float_class_qnan: + flags =3D float_flag_invalid; + r =3D max; + break; + + case float_class_inf: + flags =3D float_flag_invalid; + r =3D p->sign ? min : max; + break; + + case float_class_zero: + return 0; + + case float_class_normal: + /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ + if (parts_round_to_int_normal(p, rmode, scale, N - 2)) { + flags =3D float_flag_inexact; + } + + if (p->exp <=3D DECOMPOSED_BINARY_POINT) { + r =3D p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); + } else { + r =3D UINT64_MAX; + } + if (p->sign) { + if (r <=3D -(uint64_t)min) { + r =3D -r; + } else { + flags =3D float_flag_invalid; + r =3D min; + } + } else if (r > max) { + flags =3D float_flag_invalid; + r =3D max; + } + break; + + default: + g_assert_not_reached(); + } + + float_raise(flags, s); + return r; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440731; cv=none; d=zohomail.com; s=zohoarc; b=FhKHbcy1tfxDcJb2QuUzwcD/f05503OEjb5Xdux/wr5nKdB2oUEXE4iOU4meAN+l04YbFMNkMm4KIhSk1dJZ0kkDWa+ngBMfsRPAGf217ZbYGCfAA1Q6ZUlGdrQYY7U693oq+jOIovpvrmRvaox/+uyKggWpPGKxMpwYUQIzFm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620440731; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qGY7aCHNZkCzk37MB6QkE9/q/X8JPmp9I2EqeH2GHLs=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_float_to_uint. Reimplement float128_to_uint{32,64}{_round_to_zero} with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 357 +++++++++----------------------------- fpu/softfloat-parts.c.inc | 68 +++++++- 2 files changed, 147 insertions(+), 278 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ac8e726935..235ddda7a0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -838,6 +838,16 @@ static int64_t parts128_float_to_sint(FloatParts128 *p= , FloatRoundMode rmode, #define parts_float_to_sint(P, R, Z, MN, MX, S) \ PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S) =20 +static uint64_t parts64_float_to_uint(FloatParts64 *p, FloatRoundMode rmod= e, + int scale, uint64_t max, + float_status *s); +static uint64_t parts128_float_to_uint(FloatParts128 *p, FloatRoundMode rm= ode, + int scale, uint64_t max, + float_status *s); + +#define parts_float_to_uint(P, R, Z, M, S) \ + PARTS_GENERIC_64_128(float_to_uint, P)(P, R, Z, M, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2645,80 +2655,16 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a,= float_status *s) } =20 /* - * Returns the result of converting the floating-point value `a' to - * the unsigned integer format. The conversion is performed according - * to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic---which means in particular that the conversion is - * rounded according to the current rounding mode. If `a' is a NaN, - * the largest unsigned integer is returned. Otherwise, if the - * conversion overflows, the largest unsigned integer is returned. If - * the 'a' is negative, the result is rounded and zero is returned; - * values that do not round to zero will raise the inexact exception - * flag. + * Floating-point to unsigned integer conversions */ =20 -static uint64_t round_to_uint_and_pack(FloatParts64 p, FloatRoundMode rmod= e, - int scale, uint64_t max, - float_status *s) -{ - int flags =3D 0; - uint64_t r; - - switch (p.cls) { - case float_class_snan: - case float_class_qnan: - flags =3D float_flag_invalid; - r =3D max; - break; - - case float_class_inf: - flags =3D float_flag_invalid; - r =3D p.sign ? 0 : max; - break; - - case float_class_zero: - return 0; - - case float_class_normal: - /* TODO: 62 =3D N - 2, frac_size for rounding */ - if (parts_round_to_int_normal(&p, rmode, scale, 62)) { - flags =3D float_flag_inexact; - if (p.cls =3D=3D float_class_zero) { - r =3D 0; - break; - } - } - - if (p.sign) { - flags =3D float_flag_invalid; - r =3D 0; - } else if (p.exp > DECOMPOSED_BINARY_POINT) { - flags =3D float_flag_invalid; - r =3D max; - } else { - r =3D p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - if (r > max) { - flags =3D float_flag_invalid; - r =3D max; - } - } - break; - - default: - g_assert_not_reached(); - } - - float_raise(flags, s); - return r; -} - uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT8_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT8_MAX, s); } =20 uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int sca= le, @@ -2727,7 +2673,7 @@ uint16_t float16_to_uint16_scalbn(float16 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); } =20 uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode rmode, int sca= le, @@ -2736,7 +2682,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); } =20 uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode rmode, int sca= le, @@ -2745,7 +2691,7 @@ uint64_t float16_to_uint64_scalbn(float16 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); } =20 uint16_t float32_to_uint16_scalbn(float32 a, FloatRoundMode rmode, int sca= le, @@ -2754,7 +2700,7 @@ uint16_t float32_to_uint16_scalbn(float32 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float32_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); } =20 uint32_t float32_to_uint32_scalbn(float32 a, FloatRoundMode rmode, int sca= le, @@ -2763,7 +2709,7 @@ uint32_t float32_to_uint32_scalbn(float32 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float32_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); } =20 uint64_t float32_to_uint64_scalbn(float32 a, FloatRoundMode rmode, int sca= le, @@ -2772,7 +2718,7 @@ uint64_t float32_to_uint64_scalbn(float32 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float32_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); } =20 uint16_t float64_to_uint16_scalbn(float64 a, FloatRoundMode rmode, int sca= le, @@ -2781,7 +2727,7 @@ uint16_t float64_to_uint16_scalbn(float64 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float64_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); } =20 uint32_t float64_to_uint32_scalbn(float64 a, FloatRoundMode rmode, int sca= le, @@ -2790,7 +2736,7 @@ uint32_t float64_to_uint32_scalbn(float64 a, FloatRou= ndMode rmode, int scale, FloatParts64 p; =20 float64_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); } =20 uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int sca= le, @@ -2799,7 +2745,52 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRo= undMode rmode, int scale, FloatParts64 p; =20 float64_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); +} + +uint16_t bfloat16_to_uint16_scalbn(bfloat16 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); +} + +uint32_t bfloat16_to_uint32_scalbn(bfloat16 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); +} + +uint64_t bfloat16_to_uint64_scalbn(bfloat16 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); +} + +static uint32_t float128_to_uint32_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); +} + +static uint64_t float128_to_uint64_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); } =20 uint8_t float16_to_uint8(float16 a, float_status *s) @@ -2852,6 +2843,16 @@ uint64_t float64_to_uint64(float64 a, float_status *= s) return float64_to_uint64_scalbn(a, s->float_rounding_mode, 0, s); } =20 +uint32_t float128_to_uint32(float128 a, float_status *s) +{ + return float128_to_uint32_scalbn(a, s->float_rounding_mode, 0, s); +} + +uint64_t float128_to_uint64(float128 a, float_status *s) +{ + return float128_to_uint64_scalbn(a, s->float_rounding_mode, 0, s); +} + uint16_t float16_to_uint16_round_to_zero(float16 a, float_status *s) { return float16_to_uint16_scalbn(a, float_round_to_zero, 0, s); @@ -2897,36 +2898,14 @@ uint64_t float64_to_uint64_round_to_zero(float64 a,= float_status *s) return float64_to_uint64_scalbn(a, float_round_to_zero, 0, s); } =20 -/* - * Returns the result of converting the bfloat16 value `a' to - * the unsigned integer format. - */ - -uint16_t bfloat16_to_uint16_scalbn(bfloat16 a, FloatRoundMode rmode, - int scale, float_status *s) +uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return float128_to_uint32_scalbn(a, float_round_to_zero, 0, s); } =20 -uint32_t bfloat16_to_uint32_scalbn(bfloat16 a, FloatRoundMode rmode, - int scale, float_status *s) +uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); -} - -uint64_t bfloat16_to_uint64_scalbn(bfloat16 a, FloatRoundMode rmode, - int scale, float_status *s) -{ - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return float128_to_uint64_scalbn(a, float_round_to_zero, 0, s); } =20 uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s) @@ -4122,66 +4101,6 @@ static int64_t roundAndPackInt64(bool zSign, uint64_= t absZ0, uint64_t absZ1, =20 } =20 -/*------------------------------------------------------------------------= ---- -| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and -| `absZ1', with binary point between bits 63 and 64 (between the input wor= ds), -| and returns the properly rounded 64-bit unsigned integer corresponding t= o the -| input. Ordinarily, the fixed-point input is simply rounded to an intege= r, -| with the inexact exception raised if the input cannot be represented exa= ctly -| as an integer. However, if the fixed-point input is too large, the inva= lid -| exception is raised and the largest unsigned integer is returned. -*-------------------------------------------------------------------------= ---*/ - -static int64_t roundAndPackUint64(bool zSign, uint64_t absZ0, - uint64_t absZ1, float_status *status) -{ - int8_t roundingMode; - bool roundNearestEven, increment; - - roundingMode =3D status->float_rounding_mode; - roundNearestEven =3D (roundingMode =3D=3D float_round_nearest_even); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment =3D ((int64_t)absZ1 < 0); - break; - case float_round_to_zero: - increment =3D 0; - break; - case float_round_up: - increment =3D !zSign && absZ1; - break; - case float_round_down: - increment =3D zSign && absZ1; - break; - case float_round_to_odd: - increment =3D !(absZ0 & 1) && absZ1; - break; - default: - abort(); - } - if (increment) { - ++absZ0; - if (absZ0 =3D=3D 0) { - float_raise(float_flag_invalid, status); - return UINT64_MAX; - } - if (!(absZ1 << 1) && roundNearestEven) { - absZ0 &=3D ~1; - } - } - - if (zSign && absZ0) { - float_raise(float_flag_invalid, status); - return 0; - } - - if (absZ1) { - float_raise(float_flag_inexact, status); - } - return absZ0; -} - /*------------------------------------------------------------------------= ---- | Normalizes the subnormal single-precision floating-point value represent= ed | by the denormalized significand `aSig'. The normalized exponent and @@ -6535,122 +6454,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *st= atus) 0, zExp, zSig0, zSig1, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point = value -| `a' to the 64-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. If the conversion overflows, the -| largest unsigned integer is returned. If 'a' is negative, the value is -| rounded and zero is returned; negative values that do not round to zero -| will raise the inexact exception. -*-------------------------------------------------------------------------= ---*/ - -uint64_t float128_to_uint64(float128 a, float_status *status) -{ - bool aSign; - int aExp; - int shiftCount; - uint64_t aSig0, aSig1; - - aSig0 =3D extractFloat128Frac0(a); - aSig1 =3D extractFloat128Frac1(a); - aExp =3D extractFloat128Exp(a); - aSign =3D extractFloat128Sign(a); - if (aSign && (aExp > 0x3FFE)) { - float_raise(float_flag_invalid, status); - if (float128_is_any_nan(a)) { - return UINT64_MAX; - } else { - return 0; - } - } - if (aExp) { - aSig0 |=3D UINT64_C(0x0001000000000000); - } - shiftCount =3D 0x402F - aExp; - if (shiftCount <=3D 0) { - if (0x403E < aExp) { - float_raise(float_flag_invalid, status); - return UINT64_MAX; - } - shortShift128Left(aSig0, aSig1, -shiftCount, &aSig0, &aSig1); - } else { - shift64ExtraRightJamming(aSig0, aSig1, shiftCount, &aSig0, &aSig1); - } - return roundAndPackUint64(aSign, aSig0, aSig1, status); -} - -uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *status) -{ - uint64_t v; - signed char current_rounding_mode =3D status->float_rounding_mode; - - set_float_rounding_mode(float_round_to_zero, status); - v =3D float128_to_uint64(a, status); - set_float_rounding_mode(current_rounding_mode, status); - - return v; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit unsigned integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, -| if the conversion overflows, the largest unsigned integer is returned. -| If 'a' is negative, the value is rounded and zero is returned; negative -| values that do not round to zero will raise the inexact exception. -*-------------------------------------------------------------------------= ---*/ - -uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *status) -{ - uint64_t v; - uint32_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float128_to_uint64_round_to_zero(a, status); - if (v > 0xffffffff) { - res =3D 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point = value -| `a' to the 32-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. If the conversion overflows, the -| largest unsigned integer is returned. If 'a' is negative, the value is -| rounded and zero is returned; negative values that do not round to zero -| will raise the inexact exception. -*-------------------------------------------------------------------------= ---*/ - -uint32_t float128_to_uint32(float128 a, float_status *status) -{ - uint64_t v; - uint32_t res; - int old_exc_flags =3D get_float_exception_flags(status); - - v =3D float128_to_uint64(a, status); - if (v > 0xffffffff) { - res =3D 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point | value `a' to the extended double-precision floating-point format. The diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a897a5a743..c6e327547f 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -761,7 +761,7 @@ static void partsN(round_to_int)(FloatPartsN *a, FloatR= oundMode rmode, * the largest positive integer is returned. Otherwise, if the * conversion overflows, the largest integer with the same sign as `a' * is returned. -*/ + */ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) @@ -815,3 +815,69 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, F= loatRoundMode rmode, float_raise(flags, s); return r; } + +/* + * Returns the result of converting the floating-point value `a' to + * the unsigned integer format. The conversion is performed according + * to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic---which means in particular that the conversion is + * rounded according to the current rounding mode. If `a' is a NaN, + * the largest unsigned integer is returned. Otherwise, if the + * conversion overflows, the largest unsigned integer is returned. If + * the 'a' is negative, the result is rounded and zero is returned; + * values that do not round to zero will raise the inexact exception + * flag. + */ +static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, + int scale, uint64_t max, float_statu= s *s) +{ + int flags =3D 0; + uint64_t r; + + switch (p->cls) { + case float_class_snan: + case float_class_qnan: + flags =3D float_flag_invalid; + r =3D max; + break; + + case float_class_inf: + flags =3D float_flag_invalid; + r =3D p->sign ? 0 : max; + break; + + case float_class_zero: + return 0; + + case float_class_normal: + /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ + if (parts_round_to_int_normal(p, rmode, scale, N - 2)) { + flags =3D float_flag_inexact; + if (p->cls =3D=3D float_class_zero) { + r =3D 0; + break; + } + } + + if (p->sign) { + flags =3D float_flag_invalid; + r =3D 0; + } else if (p->exp > DECOMPOSED_BINARY_POINT) { + flags =3D float_flag_invalid; + r =3D max; + } else { + r =3D p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); + if (r > max) { + flags =3D float_flag_invalid; + r =3D max; + } + } + break; + + default: + g_assert_not_reached(); + } + + float_raise(flags, s); + return r; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441057; cv=none; d=zohomail.com; s=zohoarc; b=eTV1yTigHqES5M6YvB7ZVsdH8A67YhQ3vbDNvSMrGoZw7vuGkMMrT9Zud04gIQ7M0qsAz8WdBQ/SqGWPzEU7vNI6ViMN68hC6rtmsmCsi9luukiI2ltg1u0YJc7UC1m7E83l7bAOg1W2b3/2aOjWVKgf/Pnr/mIpJFlq2qZZBmM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441057; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_sint_to_float. Reimplement int{32,64}_to_float128 with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 136 +++++++++++--------------------------- fpu/softfloat-parts.c.inc | 32 +++++++++ 2 files changed, 70 insertions(+), 98 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 235ddda7a0..d843ea67c4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -848,6 +848,14 @@ static uint64_t parts128_float_to_uint(FloatParts128 *= p, FloatRoundMode rmode, #define parts_float_to_uint(P, R, Z, M, S) \ PARTS_GENERIC_64_128(float_to_uint, P)(P, R, Z, M, S) =20 +static void parts64_sint_to_float(FloatParts64 *p, int64_t a, + int scale, float_status *s); +static void parts128_sint_to_float(FloatParts128 *p, int64_t a, + int scale, float_status *s); + +#define parts_sint_to_float(P, I, Z, S) \ + PARTS_GENERIC_64_128(sint_to_float, P)(P, I, Z, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2939,42 +2947,15 @@ uint64_t bfloat16_to_uint64_round_to_zero(bfloat16 = a, float_status *s) } =20 /* - * Integer to float conversions - * - * Returns the result of converting the two's complement integer `a' - * to the floating-point format. The conversion is performed according - * to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + * Signed integer to floating-point conversions */ =20 -static FloatParts64 int_to_float(int64_t a, int scale, float_status *statu= s) -{ - FloatParts64 r =3D { .sign =3D false }; - - if (a =3D=3D 0) { - r.cls =3D float_class_zero; - } else { - uint64_t f =3D a; - int shift; - - r.cls =3D float_class_normal; - if (a < 0) { - f =3D -f; - r.sign =3D true; - } - shift =3D clz64(f); - scale =3D MIN(MAX(scale, -0x10000), 0x10000); - - r.exp =3D DECOMPOSED_BINARY_POINT - shift + scale; - r.frac =3D f << shift; - } - - return r; -} - float16 int64_to_float16_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa =3D int_to_float(a, scale, status); - return float16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_sint_to_float(&p, a, scale, status); + return float16_round_pack_canonical(&p, status); } =20 float16 int32_to_float16_scalbn(int32_t a, int scale, float_status *status) @@ -3009,8 +2990,10 @@ float16 int8_to_float16(int8_t a, float_status *stat= us) =20 float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa =3D int_to_float(a, scale, status); - return float32_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts64_sint_to_float(&p, a, scale, status); + return float32_round_pack_canonical(&p, status); } =20 float32 int32_to_float32_scalbn(int32_t a, int scale, float_status *status) @@ -3040,8 +3023,10 @@ float32 int16_to_float32(int16_t a, float_status *st= atus) =20 float64 int64_to_float64_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa =3D int_to_float(a, scale, status); - return float64_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_sint_to_float(&p, a, scale, status); + return float64_round_pack_canonical(&p, status); } =20 float64 int32_to_float64_scalbn(int32_t a, int scale, float_status *status) @@ -3069,15 +3054,12 @@ float64 int16_to_float64(int16_t a, float_status *s= tatus) return int64_to_float64_scalbn(a, 0, status); } =20 -/* - * Returns the result of converting the two's complement integer `a' - * to the bfloat16 format. - */ - bfloat16 int64_to_bfloat16_scalbn(int64_t a, int scale, float_status *stat= us) { - FloatParts64 pa =3D int_to_float(a, scale, status); - return bfloat16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_sint_to_float(&p, a, scale, status); + return bfloat16_round_pack_canonical(&p, status); } =20 bfloat16 int32_to_bfloat16_scalbn(int32_t a, int scale, float_status *stat= us) @@ -3105,6 +3087,19 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status *= status) return int64_to_bfloat16_scalbn(a, 0, status); } =20 +float128 int64_to_float128(int64_t a, float_status *status) +{ + FloatParts128 p; + + parts_sint_to_float(&p, a, 0, status); + return float128_round_pack_canonical(&p, status); +} + +float128 int32_to_float128(int32_t a, float_status *status) +{ + return int64_to_float128(a, status); +} + /* * Unsigned Integer to float conversions * @@ -4955,28 +4950,6 @@ floatx80 int32_to_floatx80(int32_t a, float_status *= status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the 32-bit two's complement integer `a'= to -| the quadruple-precision floating-point format. The conversion is perfor= med -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 int32_to_float128(int32_t a, float_status *status) -{ - bool zSign; - uint32_t absA; - int8_t shiftCount; - uint64_t zSig0; - - if ( a =3D=3D 0 ) return packFloat128( 0, 0, 0, 0 ); - zSign =3D ( a < 0 ); - absA =3D zSign ? - a : a; - shiftCount =3D clz32(absA) + 17; - zSig0 =3D absA; - return packFloat128( zSign, 0x402E - shiftCount, zSig0<cls =3D float_class_zero; + return; + } + + p->cls =3D float_class_normal; + if (a < 0) { + f =3D -f; + p->sign =3D true; + } + shift =3D clz64(f); + scale =3D MIN(MAX(scale, -0x10000), 0x10000); + + p->exp =3D DECOMPOSED_BINARY_POINT - shift + scale; + p->frac_hi =3D f << shift; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:51:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 49/72] softfloat: Move uint_to_float to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:39 -0700 Message-Id: <20210508014802.892561-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_uint_to_float. Reimplement uint64_to_float128 with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 83 ++++++++++++++++----------------------- fpu/softfloat-parts.c.inc | 23 +++++++++++ 2 files changed, 56 insertions(+), 50 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d843ea67c4..586ea5d67a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -856,6 +856,14 @@ static void parts128_sint_to_float(FloatParts128 *p, i= nt64_t a, #define parts_sint_to_float(P, I, Z, S) \ PARTS_GENERIC_64_128(sint_to_float, P)(P, I, Z, S) =20 +static void parts64_uint_to_float(FloatParts64 *p, uint64_t a, + int scale, float_status *s); +static void parts128_uint_to_float(FloatParts128 *p, uint64_t a, + int scale, float_status *s); + +#define parts_uint_to_float(P, I, Z, S) \ + PARTS_GENERIC_64_128(uint_to_float, P)(P, I, Z, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3101,35 +3109,15 @@ float128 int32_to_float128(int32_t a, float_status = *status) } =20 /* - * Unsigned Integer to float conversions - * - * Returns the result of converting the unsigned integer `a' to the - * floating-point format. The conversion is performed according to the - * IEC/IEEE Standard for Binary Floating-Point Arithmetic. + * Unsigned Integer to floating-point conversions */ =20 -static FloatParts64 uint_to_float(uint64_t a, int scale, float_status *sta= tus) -{ - FloatParts64 r =3D { .sign =3D false }; - int shift; - - if (a =3D=3D 0) { - r.cls =3D float_class_zero; - } else { - scale =3D MIN(MAX(scale, -0x10000), 0x10000); - shift =3D clz64(a); - r.cls =3D float_class_normal; - r.exp =3D DECOMPOSED_BINARY_POINT - shift + scale; - r.frac =3D a << shift; - } - - return r; -} - float16 uint64_to_float16_scalbn(uint64_t a, int scale, float_status *stat= us) { - FloatParts64 pa =3D uint_to_float(a, scale, status); - return float16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return float16_round_pack_canonical(&p, status); } =20 float16 uint32_to_float16_scalbn(uint32_t a, int scale, float_status *stat= us) @@ -3164,8 +3152,10 @@ float16 uint8_to_float16(uint8_t a, float_status *st= atus) =20 float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *stat= us) { - FloatParts64 pa =3D uint_to_float(a, scale, status); - return float32_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return float32_round_pack_canonical(&p, status); } =20 float32 uint32_to_float32_scalbn(uint32_t a, int scale, float_status *stat= us) @@ -3195,8 +3185,10 @@ float32 uint16_to_float32(uint16_t a, float_status *= status) =20 float64 uint64_to_float64_scalbn(uint64_t a, int scale, float_status *stat= us) { - FloatParts64 pa =3D uint_to_float(a, scale, status); - return float64_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return float64_round_pack_canonical(&p, status); } =20 float64 uint32_to_float64_scalbn(uint32_t a, int scale, float_status *stat= us) @@ -3224,15 +3216,12 @@ float64 uint16_to_float64(uint16_t a, float_status = *status) return uint64_to_float64_scalbn(a, 0, status); } =20 -/* - * Returns the result of converting the unsigned integer `a' to the - * bfloat16 format. - */ - bfloat16 uint64_to_bfloat16_scalbn(uint64_t a, int scale, float_status *st= atus) { - FloatParts64 pa =3D uint_to_float(a, scale, status); - return bfloat16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return bfloat16_round_pack_canonical(&p, status); } =20 bfloat16 uint32_to_bfloat16_scalbn(uint32_t a, int scale, float_status *st= atus) @@ -3260,6 +3249,14 @@ bfloat16 uint16_to_bfloat16(uint16_t a, float_status= *status) return uint64_to_bfloat16_scalbn(a, 0, status); } =20 +float128 uint64_to_float128(uint64_t a, float_status *status) +{ + FloatParts128 p; + + parts_uint_to_float(&p, a, 0, status); + return float128_round_pack_canonical(&p, status); +} + /* Float Min/Max */ /* min() and max() functions. These can't be implemented as * 'compare and pick one input' because that would mishandle @@ -4971,20 +4968,6 @@ floatx80 int64_to_floatx80(int64_t a, float_status *= status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the 64-bit unsigned integer `a' -| to the quadruple-precision floating-point format. The conversion is per= formed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 uint64_to_float128(uint64_t a, float_status *status) -{ - if (a =3D=3D 0) { - return float128_zero; - } - return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the single-precision floating-point val= ue | `a' to the extended double-precision floating-point format. The convers= ion diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 8102de1307..f3c4f8c8d2 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -913,3 +913,26 @@ static void partsN(sint_to_float)(FloatPartsN *p, int6= 4_t a, p->exp =3D DECOMPOSED_BINARY_POINT - shift + scale; p->frac_hi =3D f << shift; } + +/* + * Unsigned Integer to float conversions + * + * Returns the result of converting the unsigned integer `a' to the + * floating-point format. The conversion is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ +static void partsN(uint_to_float)(FloatPartsN *p, uint64_t a, + int scale, float_status *status) +{ + memset(p, 0, sizeof(*p)); + + if (a =3D=3D 0) { + p->cls =3D float_class_zero; + } else { + int shift =3D clz64(a); + scale =3D MIN(MAX(scale, -0x10000), 0x10000); + p->cls =3D float_class_normal; + p->exp =3D DECOMPOSED_BINARY_POINT - shift + scale; + p->frac_hi =3D a << shift; + } +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620440955; cv=none; d=zohomail.com; s=zohoarc; b=FgKHHSXV92IBAudEGFYANHsUnZdPXgM2n7dZOMUGR4LLtlU61nZBkxtWY59a+SNMg3+gPEQC4ywVDIJSghMTJhwoKOBas88cEJNvbnLjA7yEVgnk3QqjzvWLfGNbulTNQpMswM768T7yMxX5hKpHMbFAfHcvKyEOpA3jqhu1nug= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 50/72] softfloat: Move minmax_flags to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:40 -0700 Message-Id: <20210508014802.892561-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_minmax. Combine 3 bool arguments to a bitmask, return a tri-state value to indicate nan vs unchanged operand. Introduce ftype_minmax functions as a common optimization point. Fold bfloat16 expansions into the same macro as the other types. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 216 ++++++++++++++++---------------------- fpu/softfloat-parts.c.inc | 69 ++++++++++++ 2 files changed, 158 insertions(+), 127 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 586ea5d67a..4c04e88a3a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -482,6 +482,15 @@ enum { float_cmask_anynan =3D float_cmask_qnan | float_cmask_snan, }; =20 +/* Flags for parts_minmax. */ +enum { + /* Set for minimum; clear for maximum. */ + minmax_ismin =3D 1, + /* Set for the IEEE 754-2008 minNum() and maxNum() operations. */ + minmax_isnum =3D 2, + /* Set for the IEEE 754-2008 minNumMag() and minNumMag() operations. */ + minmax_ismag =3D 4 | minmax_isnum +}; =20 /* Simple helpers for checking if, or what kind of, NaN we have */ static inline __attribute__((unused)) bool is_nan(FloatClass c) @@ -864,6 +873,14 @@ static void parts128_uint_to_float(FloatParts128 *p, u= int64_t a, #define parts_uint_to_float(P, I, Z, S) \ PARTS_GENERIC_64_128(uint_to_float, P)(P, I, Z, S) =20 +static int parts64_minmax(FloatParts64 *a, FloatParts64 *b, + float_status *s, int flags, const FloatFmt *fmt); +static int parts128_minmax(FloatParts128 *a, FloatParts128 *b, + float_status *s, int flags, const FloatFmt *fmt= ); + +#define parts_minmax(A, B, S, Z, F) \ + PARTS_GENERIC_64_128(minmax, A)(A, B, S, Z, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3257,145 +3274,90 @@ float128 uint64_to_float128(uint64_t a, float_stat= us *status) return float128_round_pack_canonical(&p, status); } =20 -/* Float Min/Max */ -/* min() and max() functions. These can't be implemented as - * 'compare and pick one input' because that would mishandle - * NaNs and +0 vs -0. - * - * minnum() and maxnum() functions. These are similar to the min() - * and max() functions but if one of the arguments is a QNaN and - * the other is numerical then the numerical argument is returned. - * SNaNs will get quietened before being returned. - * minnum() and maxnum correspond to the IEEE 754-2008 minNum() - * and maxNum() operations. min() and max() are the typical min/max - * semantics provided by many CPUs which predate that specification. - * - * minnummag() and maxnummag() functions correspond to minNumMag() - * and minNumMag() from the IEEE-754 2008. +/* + * Minimum and maximum */ -static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ism= in, - bool ieee, bool ismag, float_status *s) + +static float16 float16_minmax(float16 a, float16 b, float_status *s, int f= lags) { - if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { - if (ieee) { - /* Takes two floating-point values `a' and `b', one of - * which is a NaN, and returns the appropriate NaN - * result. If either `a' or `b' is a signaling NaN, - * the invalid exception is raised. - */ - if (is_snan(a.cls) || is_snan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } else if (is_nan(a.cls) && !is_nan(b.cls)) { - return b; - } else if (is_nan(b.cls) && !is_nan(a.cls)) { - return a; - } - } - return *parts_pick_nan(&a, &b, s); - } else { - int a_exp, b_exp; + FloatParts64 pa, pb; + int which; =20 - switch (a.cls) { - case float_class_normal: - a_exp =3D a.exp; - break; - case float_class_inf: - a_exp =3D INT_MAX; - break; - case float_class_zero: - a_exp =3D INT_MIN; - break; - default: - g_assert_not_reached(); - break; - } - switch (b.cls) { - case float_class_normal: - b_exp =3D b.exp; - break; - case float_class_inf: - b_exp =3D INT_MAX; - break; - case float_class_zero: - b_exp =3D INT_MIN; - break; - default: - g_assert_not_reached(); - break; - } - - if (ismag && (a_exp !=3D b_exp || a.frac !=3D b.frac)) { - bool a_less =3D a_exp < b_exp; - if (a_exp =3D=3D b_exp) { - a_less =3D a.frac < b.frac; - } - return a_less ^ ismin ? b : a; - } - - if (a.sign =3D=3D b.sign) { - bool a_less =3D a_exp < b_exp; - if (a_exp =3D=3D b_exp) { - a_less =3D a.frac < b.frac; - } - return a.sign ^ a_less ^ ismin ? b : a; - } else { - return a.sign ^ ismin ? b : a; - } + float16_unpack_canonical(&pa, a, s); + float16_unpack_canonical(&pb, b, s); + which =3D parts_minmax(&pa, &pb, s, flags, &float16_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return float16_round_pack_canonical(&pa, s); } + return which ? b : a; } =20 -#define MINMAX(sz, name, ismin, isiee, ismag) \ -float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ - float_status *s) \ -{ \ - FloatParts64 pa, pb, pr; \ - float ## sz ## _unpack_canonical(&pa, a, s); \ - float ## sz ## _unpack_canonical(&pb, b, s); \ - pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return float ## sz ## _round_pack_canonical(&pr, s); \ +static bfloat16 bfloat16_minmax(bfloat16 a, bfloat16 b, + float_status *s, int flags) +{ + FloatParts64 pa, pb; + int which; + + bfloat16_unpack_canonical(&pa, a, s); + bfloat16_unpack_canonical(&pb, b, s); + which =3D parts_minmax(&pa, &pb, s, flags, &float16_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return bfloat16_round_pack_canonical(&pa, s); + } + return which ? b : a; } =20 -MINMAX(16, min, true, false, false) -MINMAX(16, minnum, true, true, false) -MINMAX(16, minnummag, true, true, true) -MINMAX(16, max, false, false, false) -MINMAX(16, maxnum, false, true, false) -MINMAX(16, maxnummag, false, true, true) +static float32 float32_minmax(float32 a, float32 b, float_status *s, int f= lags) +{ + FloatParts64 pa, pb; + int which; =20 -MINMAX(32, min, true, false, false) -MINMAX(32, minnum, true, true, false) -MINMAX(32, minnummag, true, true, true) -MINMAX(32, max, false, false, false) -MINMAX(32, maxnum, false, true, false) -MINMAX(32, maxnummag, false, true, true) - -MINMAX(64, min, true, false, false) -MINMAX(64, minnum, true, true, false) -MINMAX(64, minnummag, true, true, true) -MINMAX(64, max, false, false, false) -MINMAX(64, maxnum, false, true, false) -MINMAX(64, maxnummag, false, true, true) - -#undef MINMAX - -#define BF16_MINMAX(name, ismin, isiee, ismag) \ -bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ -{ \ - FloatParts64 pa, pb, pr; \ - bfloat16_unpack_canonical(&pa, a, s); \ - bfloat16_unpack_canonical(&pb, b, s); \ - pr =3D minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return bfloat16_round_pack_canonical(&pr, s); \ + float32_unpack_canonical(&pa, a, s); + float32_unpack_canonical(&pb, b, s); + which =3D parts_minmax(&pa, &pb, s, flags, &float32_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return float32_round_pack_canonical(&pa, s); + } + return which ? b : a; } =20 -BF16_MINMAX(min, true, false, false) -BF16_MINMAX(minnum, true, true, false) -BF16_MINMAX(minnummag, true, true, true) -BF16_MINMAX(max, false, false, false) -BF16_MINMAX(maxnum, false, true, false) -BF16_MINMAX(maxnummag, false, true, true) +static float64 float64_minmax(float64 a, float64 b, float_status *s, int f= lags) +{ + FloatParts64 pa, pb; + int which; =20 -#undef BF16_MINMAX + float64_unpack_canonical(&pa, a, s); + float64_unpack_canonical(&pb, b, s); + which =3D parts_minmax(&pa, &pb, s, flags, &float64_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return float64_round_pack_canonical(&pa, s); + } + return which ? b : a; +} + +#define MINMAX_1(type, name, flags) \ + type type##_##name(type a, type b, float_status *s) \ + { return type##_minmax(a, b, s, flags); } + +#define MINMAX_2(type) \ + MINMAX_1(type, max, 0) \ + MINMAX_1(type, maxnum, minmax_isnum) \ + MINMAX_1(type, maxnummag, minmax_ismag) \ + MINMAX_1(type, min, minmax_ismin) \ + MINMAX_1(type, minnum, minmax_ismin | minmax_isnum) \ + MINMAX_1(type, minnummag, minmax_ismin | minmax_ismag) + +MINMAX_2(float16) +MINMAX_2(bfloat16) +MINMAX_2(float32) +MINMAX_2(float64) + +#undef MINMAX_1 +#undef MINMAX_2 =20 /* Floating point compare */ static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool i= s_quiet, diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index f3c4f8c8d2..4d91ef0d32 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -936,3 +936,72 @@ static void partsN(uint_to_float)(FloatPartsN *p, uint= 64_t a, p->frac_hi =3D a << shift; } } + +/* + * Float min/max. + * + * Return -1 to return the chosen nan in *a; + * return 0 to use the a input unchanged; 1 to use the b input unchanged. + */ +static int partsN(minmax)(FloatPartsN *a, FloatPartsN *b, + float_status *s, int flags, const FloatFmt *fmt) +{ + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + int a_exp, b_exp; + bool a_less; + + if (unlikely(ab_mask & float_cmask_anynan)) { + /* + * For minnum/maxnum, if one operand is a QNaN, and the other + * operand is numerical, then return numerical argument. + */ + if ((flags & minmax_isnum) + && !(ab_mask & float_cmask_snan) + && (ab_mask & ~float_cmask_qnan)) { + return is_nan(a->cls); + } + *a =3D *parts_pick_nan(a, b, s); + return -1; + } + + a_exp =3D a->exp; + b_exp =3D b->exp; + + if (unlikely(ab_mask !=3D float_cmask_normal)) { + switch (a->cls) { + case float_class_normal: + break; + case float_class_inf: + a_exp =3D INT_MAX; + break; + case float_class_zero: + a_exp =3D INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + switch (b->cls) { + case float_class_normal: + break; + case float_class_inf: + b_exp =3D INT_MAX; + break; + case float_class_zero: + b_exp =3D INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + } + + if (a->sign !=3D b->sign && !(flags & minmax_ismag)) { + a_less =3D a->sign; + } else if (a_exp !=3D b_exp) { + a_less =3D a_exp < b_exp; + } else { + a_less =3D frac_cmp(a, b) < 0; + } + return a_less ^ !!(flags & minmax_ismin); +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441399; cv=none; d=zohomail.com; s=zohoarc; b=MHiZsEgfNdiaIO6jOwPWsGQNFuKomKJ6S3aXtKhHO6BnVnhPxHiHoP4s9NDrcsznwDOZHeLwIeRdJ2YLHDCarLpPYpAREPoR47WDADDv03mSRVqgy2oQ2ZrzWtK5R03rB/dgHptSgh349zuXQVEco5GKVQn8zw4fLCKdB3W+/jE= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 51/72] softfloat: Move compare_floats to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:41 -0700 Message-Id: <20210508014802.892561-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_compare. Rename all of the intermediate functions to ftype_do_compare. Rename the hard-float functions to ftype_hs_compare. Convert float128 to FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 208 ++++++++++++++------------------------ fpu/softfloat-parts.c.inc | 57 +++++++++++ 2 files changed, 133 insertions(+), 132 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4c04e88a3a..2faceadf8b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -881,6 +881,14 @@ static int parts128_minmax(FloatParts128 *a, FloatPart= s128 *b, #define parts_minmax(A, B, S, Z, F) \ PARTS_GENERIC_64_128(minmax, A)(A, B, S, Z, F) =20 +static int parts64_compare(FloatParts64 *a, FloatParts64 *b, + float_status *s, bool q); +static int parts128_compare(FloatParts128 *a, FloatParts128 *b, + float_status *s, bool q); + +#define parts_compare(A, B, S, Q) \ + PARTS_GENERIC_64_128(compare, A)(A, B, S, Q) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3359,92 +3367,42 @@ MINMAX_2(float64) #undef MINMAX_1 #undef MINMAX_2 =20 -/* Floating point compare */ -static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool i= s_quiet, - float_status *s) +/* + * Floating point compare + */ + +static FloatRelation QEMU_FLATTEN +float16_do_compare(float16 a, float16 b, float_status *s, bool is_quiet) { - if (is_nan(a.cls) || is_nan(b.cls)) { - if (!is_quiet || - a.cls =3D=3D float_class_snan || - b.cls =3D=3D float_class_snan) { - float_raise(float_flag_invalid, s); - } - return float_relation_unordered; - } + FloatParts64 pa, pb; =20 - if (a.cls =3D=3D float_class_zero) { - if (b.cls =3D=3D float_class_zero) { - return float_relation_equal; - } - return b.sign ? float_relation_greater : float_relation_less; - } else if (b.cls =3D=3D float_class_zero) { - return a.sign ? float_relation_less : float_relation_greater; - } - - /* The only really important thing about infinity is its sign. If - * both are infinities the sign marks the smallest of the two. - */ - if (a.cls =3D=3D float_class_inf) { - if ((b.cls =3D=3D float_class_inf) && (a.sign =3D=3D b.sign)) { - return float_relation_equal; - } - return a.sign ? float_relation_less : float_relation_greater; - } else if (b.cls =3D=3D float_class_inf) { - return b.sign ? float_relation_greater : float_relation_less; - } - - if (a.sign !=3D b.sign) { - return a.sign ? float_relation_less : float_relation_greater; - } - - if (a.exp =3D=3D b.exp) { - if (a.frac =3D=3D b.frac) { - return float_relation_equal; - } - if (a.sign) { - return a.frac > b.frac ? - float_relation_less : float_relation_greater; - } else { - return a.frac > b.frac ? - float_relation_greater : float_relation_less; - } - } else { - if (a.sign) { - return a.exp > b.exp ? float_relation_less : float_relation_gr= eater; - } else { - return a.exp > b.exp ? float_relation_greater : float_relation= _less; - } - } + float16_unpack_canonical(&pa, a, s); + float16_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); } =20 -#define COMPARE(name, attr, sz) \ -static int attr \ -name(float ## sz a, float ## sz b, bool is_quiet, float_status *s) \ -{ \ - FloatParts64 pa, pb; \ - float ## sz ## _unpack_canonical(&pa, a, s); \ - float ## sz ## _unpack_canonical(&pb, b, s); \ - return compare_floats(pa, pb, is_quiet, s); \ -} - -COMPARE(soft_f16_compare, QEMU_FLATTEN, 16) -COMPARE(soft_f32_compare, QEMU_SOFTFLOAT_ATTR, 32) -COMPARE(soft_f64_compare, QEMU_SOFTFLOAT_ATTR, 64) - -#undef COMPARE - FloatRelation float16_compare(float16 a, float16 b, float_status *s) { - return soft_f16_compare(a, b, false, s); + return float16_do_compare(a, b, s, false); } =20 FloatRelation float16_compare_quiet(float16 a, float16 b, float_status *s) { - return soft_f16_compare(a, b, true, s); + return float16_do_compare(a, b, s, true); +} + +static FloatRelation QEMU_SOFTFLOAT_ATTR +float32_do_compare(float32 a, float32 b, float_status *s, bool is_quiet) +{ + FloatParts64 pa, pb; + + float32_unpack_canonical(&pa, a, s); + float32_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); } =20 static FloatRelation QEMU_FLATTEN -f32_compare(float32 xa, float32 xb, bool is_quiet, float_status *s) +float32_hs_compare(float32 xa, float32 xb, float_status *s, bool is_quiet) { union_float32 ua, ub; =20 @@ -3465,25 +3423,36 @@ f32_compare(float32 xa, float32 xb, bool is_quiet, = float_status *s) if (likely(isless(ua.h, ub.h))) { return float_relation_less; } - /* The only condition remaining is unordered. + /* + * The only condition remaining is unordered. * Fall through to set flags. */ soft: - return soft_f32_compare(ua.s, ub.s, is_quiet, s); + return float32_do_compare(ua.s, ub.s, s, is_quiet); } =20 FloatRelation float32_compare(float32 a, float32 b, float_status *s) { - return f32_compare(a, b, false, s); + return float32_hs_compare(a, b, s, false); } =20 FloatRelation float32_compare_quiet(float32 a, float32 b, float_status *s) { - return f32_compare(a, b, true, s); + return float32_hs_compare(a, b, s, true); +} + +static FloatRelation QEMU_SOFTFLOAT_ATTR +float64_do_compare(float64 a, float64 b, float_status *s, bool is_quiet) +{ + FloatParts64 pa, pb; + + float64_unpack_canonical(&pa, a, s); + float64_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); } =20 static FloatRelation QEMU_FLATTEN -f64_compare(float64 xa, float64 xb, bool is_quiet, float_status *s) +float64_hs_compare(float64 xa, float64 xb, float_status *s, bool is_quiet) { union_float64 ua, ub; =20 @@ -3504,41 +3473,62 @@ f64_compare(float64 xa, float64 xb, bool is_quiet, = float_status *s) if (likely(isless(ua.h, ub.h))) { return float_relation_less; } - /* The only condition remaining is unordered. + /* + * The only condition remaining is unordered. * Fall through to set flags. */ soft: - return soft_f64_compare(ua.s, ub.s, is_quiet, s); + return float64_do_compare(ua.s, ub.s, s, is_quiet); } =20 FloatRelation float64_compare(float64 a, float64 b, float_status *s) { - return f64_compare(a, b, false, s); + return float64_hs_compare(a, b, s, false); } =20 FloatRelation float64_compare_quiet(float64 a, float64 b, float_status *s) { - return f64_compare(a, b, true, s); + return float64_hs_compare(a, b, s, true); } =20 static FloatRelation QEMU_FLATTEN -soft_bf16_compare(bfloat16 a, bfloat16 b, bool is_quiet, float_status *s) +bfloat16_do_compare(bfloat16 a, bfloat16 b, float_status *s, bool is_quiet) { FloatParts64 pa, pb; =20 bfloat16_unpack_canonical(&pa, a, s); bfloat16_unpack_canonical(&pb, b, s); - return compare_floats(pa, pb, is_quiet, s); + return parts_compare(&pa, &pb, s, is_quiet); } =20 FloatRelation bfloat16_compare(bfloat16 a, bfloat16 b, float_status *s) { - return soft_bf16_compare(a, b, false, s); + return bfloat16_do_compare(a, b, s, false); } =20 FloatRelation bfloat16_compare_quiet(bfloat16 a, bfloat16 b, float_status = *s) { - return soft_bf16_compare(a, b, true, s); + return bfloat16_do_compare(a, b, s, true); +} + +static FloatRelation QEMU_FLATTEN +float128_do_compare(float128 a, float128 b, float_status *s, bool is_quiet) +{ + FloatParts128 pa, pb; + + float128_unpack_canonical(&pa, a, s); + float128_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); +} + +FloatRelation float128_compare(float128 a, float128 b, float_status *s) +{ + return float128_do_compare(a, b, s, false); +} + +FloatRelation float128_compare_quiet(float128 a, float128 b, float_status = *s) +{ + return float128_do_compare(a, b, s, true); } =20 /* Multiply A by 2 raised to the power N. */ @@ -6611,52 +6601,6 @@ FloatRelation floatx80_compare_quiet(floatx80 a, flo= atx80 b, return floatx80_compare_internal(a, b, 1, status); } =20 -static inline FloatRelation -float128_compare_internal(float128 a, float128 b, bool is_quiet, - float_status *status) -{ - bool aSign, bSign; - - if (( ( extractFloat128Exp( a ) =3D=3D 0x7fff ) && - ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) || - ( ( extractFloat128Exp( b ) =3D=3D 0x7fff ) && - ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )) { - if (!is_quiet || - float128_is_signaling_nan(a, status) || - float128_is_signaling_nan(b, status)) { - float_raise(float_flag_invalid, status); - } - return float_relation_unordered; - } - aSign =3D extractFloat128Sign( a ); - bSign =3D extractFloat128Sign( b ); - if ( aSign !=3D bSign ) { - if ( ( ( ( a.high | b.high )<<1 ) | a.low | b.low ) =3D=3D 0 ) { - /* zero case */ - return float_relation_equal; - } else { - return 1 - (2 * aSign); - } - } else { - if (a.low =3D=3D b.low && a.high =3D=3D b.high) { - return float_relation_equal; - } else { - return 1 - 2 * (aSign ^ ( lt128( a.high, a.low, b.high, b.low = ) )); - } - } -} - -FloatRelation float128_compare(float128 a, float128 b, float_status *statu= s) -{ - return float128_compare_internal(a, b, 0, status); -} - -FloatRelation float128_compare_quiet(float128 a, float128 b, - float_status *status) -{ - return float128_compare_internal(a, b, 1, status); -} - floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) { bool aSign; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 4d91ef0d32..4e11aa8b3b 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1005,3 +1005,60 @@ static int partsN(minmax)(FloatPartsN *a, FloatParts= N *b, } return a_less ^ !!(flags & minmax_ismin); } + +/* + * Floating point compare + */ +static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b, + float_status *s, bool is_quiet) +{ + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + int cmp; + + if (likely(ab_mask =3D=3D float_cmask_normal)) { + if (a->sign !=3D b->sign) { + goto a_sign; + } + if (a->exp !=3D b->exp) { + cmp =3D a->exp < b->exp ? -1 : 1; + } else { + cmp =3D frac_cmp(a, b); + } + if (a->sign) { + cmp =3D -cmp; + } + return cmp; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + if (!is_quiet || (ab_mask & float_cmask_snan)) { + float_raise(float_flag_invalid, s); + } + return float_relation_unordered; + } + + if (ab_mask & float_cmask_zero) { + if (ab_mask =3D=3D float_cmask_zero) { + return float_relation_equal; + } else if (a->cls =3D=3D float_class_zero) { + goto b_sign; + } else { + goto a_sign; + } + } + + if (ab_mask =3D=3D float_cmask_inf) { + if (a->sign =3D=3D b->sign) { + return float_relation_equal; + } + } else if (b->cls =3D=3D float_class_inf) { + goto b_sign; + } else { + g_assert(a->cls =3D=3D float_class_inf); + } + + a_sign: + return a->sign ? float_relation_less : float_relation_greater; + b_sign: + return b->sign ? float_relation_greater : float_relation_less; +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441148; cv=none; d=zohomail.com; s=zohoarc; b=RmvKuoEifx4ZULwRz/1Vq/JPCRqgE23k0Ervhi4LICQ3xlPCtKQ7jrcMP2qeaLWmwdN5dwFeBk23e1ANZINFy5mX1zPjY98qmbsdX1/VV0IGKmfkdRVRCk4l93SDaeVRoXWK5lycSuVzG7hcfA2eKLmcsWJxTlj5YT9MBlbnqe0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441148; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_scalbn. Reimplement float128_scalbn with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 103 +++++++++++++------------------------- fpu/softfloat-parts.c.inc | 21 ++++++++ 2 files changed, 55 insertions(+), 69 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2faceadf8b..f83ca20000 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -889,6 +889,12 @@ static int parts128_compare(FloatParts128 *a, FloatPar= ts128 *b, #define parts_compare(A, B, S, Q) \ PARTS_GENERIC_64_128(compare, A)(A, B, S, Q) =20 +static void parts64_scalbn(FloatParts64 *a, int n, float_status *s); +static void parts128_scalbn(FloatParts128 *a, int n, float_status *s); + +#define parts_scalbn(A, N, S) \ + PARTS_GENERIC_64_128(scalbn, A)(A, N, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3531,58 +3537,53 @@ FloatRelation float128_compare_quiet(float128 a, fl= oat128 b, float_status *s) return float128_do_compare(a, b, s, true); } =20 -/* Multiply A by 2 raised to the power N. */ -static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status = *s) -{ - if (unlikely(is_nan(a.cls))) { - parts_return_nan(&a, s); - } - if (a.cls =3D=3D float_class_normal) { - /* The largest float type (even though not supported by FloatParts= 64) - * is float128, which has a 15 bit exponent. Bounding N to 16 bits - * still allows rounding to infinity, without allowing overflow - * within the int32_t that backs FloatParts64.exp. - */ - n =3D MIN(MAX(n, -0x10000), 0x10000); - a.exp +=3D n; - } - return a; -} +/* + * Scale by 2**N + */ =20 float16 float16_scalbn(float16 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float16_unpack_canonical(&pa, a, status); - pr =3D scalbn_decomposed(pa, n, status); - return float16_round_pack_canonical(&pr, status); + float16_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float16_round_pack_canonical(&p, status); } =20 float32 float32_scalbn(float32 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float32_unpack_canonical(&pa, a, status); - pr =3D scalbn_decomposed(pa, n, status); - return float32_round_pack_canonical(&pr, status); + float32_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float32_round_pack_canonical(&p, status); } =20 float64 float64_scalbn(float64 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float64_unpack_canonical(&pa, a, status); - pr =3D scalbn_decomposed(pa, n, status); - return float64_round_pack_canonical(&pr, status); + float64_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float64_round_pack_canonical(&p, status); } =20 bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - bfloat16_unpack_canonical(&pa, a, status); - pr =3D scalbn_decomposed(pa, n, status); - return bfloat16_round_pack_canonical(&pr, status); + bfloat16_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return bfloat16_round_pack_canonical(&p, status); +} + +float128 float128_scalbn(float128 a, int n, float_status *status) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float128_round_pack_canonical(&p, status); } =20 /* @@ -6640,42 +6641,6 @@ floatx80 floatx80_scalbn(floatx80 a, int n, float_st= atus *status) aSign, aExp, aSig, 0, status); } =20 -float128 float128_scalbn(float128 a, int n, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return propagateFloat128NaN(a, a, status); - } - return a; - } - if (aExp !=3D 0) { - aSig0 |=3D UINT64_C(0x0001000000000000); - } else if (aSig0 =3D=3D 0 && aSig1 =3D=3D 0) { - return a; - } else { - aExp++; - } - - if (n > 0x10000) { - n =3D 0x10000; - } else if (n < -0x10000) { - n =3D -0x10000; - } - - aExp +=3D n - 1; - return normalizeRoundAndPackFloat128( aSign, aExp, aSig0, aSig1 - , status); - -} - static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 4e11aa8b3b..9749c11a6b 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1062,3 +1062,24 @@ static FloatRelation partsN(compare)(FloatPartsN *a,= FloatPartsN *b, b_sign: return b->sign ? float_relation_greater : float_relation_less; } + +/* + * Multiply A by 2 raised to the power N. + */ +static void partsN(scalbn)(FloatPartsN *a, int n, float_status *s) +{ + switch (a->cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(a, s); + break; + case float_class_zero: + case float_class_inf: + break; + case float_class_normal: + a->exp +=3D MIN(MAX(n, -0x10000), 0x10000); + break; + default: + g_assert_not_reached(); + } +} --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441282; cv=none; d=zohomail.com; s=zohoarc; b=dKkqsMzP8zIEsN0Vs4gnQJrbHrZHO/btzH9DpqDb4f8HokRHDcjTdnohR7M8/8fhf7066MRgcDf8cCLvJHwb7Ji7ZbAHwXVg4Pnxo7LH7J0qL2mePYCDr0eS2WT9G3vMPpeNiGS/CNQwPlT02F+UYwEVjpPWlWUJdeY4YUMTG/k= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 53/72] softfloat: Move sqrt_float to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:43 -0700 Message-Id: <20210508014802.892561-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_sqrt. Reimplement float128_sqrt with FloatParts128. Reimplement with the inverse sqrt newton-raphson algorithm from musl. This is significantly faster than even the berkeley sqrt n-r algorithm, because it does not use division instructions, only multiplication. Ordinarily, changing algorithms at the same time as migrating code is a bad idea, but this is the only way I found that didn't break one of the routines at the same time. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 207 ++++++++++---------------------------- fpu/softfloat-parts.c.inc | 206 +++++++++++++++++++++++++++++++++++++ 2 files changed, 261 insertions(+), 152 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f83ca20000..75a3bb881d 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -819,6 +819,12 @@ static FloatParts128 *parts128_div(FloatParts128 *a, F= loatParts128 *b, #define parts_div(A, B, S) \ PARTS_GENERIC_64_128(div, A)(A, B, S) =20 +static void parts64_sqrt(FloatParts64 *a, float_status *s, const FloatFmt = *f); +static void parts128_sqrt(FloatParts128 *a, float_status *s, const FloatFm= t *f); + +#define parts_sqrt(A, S, F) \ + PARTS_GENERIC_64_128(sqrt, A)(A, S, F) + static bool parts64_round_to_int_normal(FloatParts64 *a, FloatRoundMode rm, int scale, int frac_size); static bool parts128_round_to_int_normal(FloatParts128 *a, FloatRoundMode = r, @@ -1385,6 +1391,30 @@ static void frac128_widen(FloatParts256 *r, FloatPar= ts128 *a) =20 #define frac_widen(A, B) FRAC_GENERIC_64_128(widen, B)(A, B) =20 +/* + * Reciprocal sqrt table. 1 bit of exponent, 6-bits of mantessa. + * From https://git.musl-libc.org/cgit/musl/tree/src/math/sqrt_data.c + * and thus MIT licenced. + */ +static const uint16_t rsqrt_tab[128] =3D { + 0xb451, 0xb2f0, 0xb196, 0xb044, 0xaef9, 0xadb6, 0xac79, 0xab43, + 0xaa14, 0xa8eb, 0xa7c8, 0xa6aa, 0xa592, 0xa480, 0xa373, 0xa26b, + 0xa168, 0xa06a, 0x9f70, 0x9e7b, 0x9d8a, 0x9c9d, 0x9bb5, 0x9ad1, + 0x99f0, 0x9913, 0x983a, 0x9765, 0x9693, 0x95c4, 0x94f8, 0x9430, + 0x936b, 0x92a9, 0x91ea, 0x912e, 0x9075, 0x8fbe, 0x8f0a, 0x8e59, + 0x8daa, 0x8cfe, 0x8c54, 0x8bac, 0x8b07, 0x8a64, 0x89c4, 0x8925, + 0x8889, 0x87ee, 0x8756, 0x86c0, 0x862b, 0x8599, 0x8508, 0x8479, + 0x83ec, 0x8361, 0x82d8, 0x8250, 0x81c9, 0x8145, 0x80c2, 0x8040, + 0xff02, 0xfd0e, 0xfb25, 0xf947, 0xf773, 0xf5aa, 0xf3ea, 0xf234, + 0xf087, 0xeee3, 0xed47, 0xebb3, 0xea27, 0xe8a3, 0xe727, 0xe5b2, + 0xe443, 0xe2dc, 0xe17a, 0xe020, 0xdecb, 0xdd7d, 0xdc34, 0xdaf1, + 0xd9b3, 0xd87b, 0xd748, 0xd61a, 0xd4f1, 0xd3cd, 0xd2ad, 0xd192, + 0xd07b, 0xcf69, 0xce5b, 0xcd51, 0xcc4a, 0xcb48, 0xca4a, 0xc94f, + 0xc858, 0xc764, 0xc674, 0xc587, 0xc49d, 0xc3b7, 0xc2d4, 0xc1f4, + 0xc116, 0xc03c, 0xbf65, 0xbe90, 0xbdbe, 0xbcef, 0xbc23, 0xbb59, + 0xba91, 0xb9cc, 0xb90a, 0xb84a, 0xb78c, 0xb6d0, 0xb617, 0xb560, +}; + #define partsN(NAME) glue(glue(glue(parts,N),_),NAME) #define FloatPartsN glue(FloatParts,N) #define FloatPartsW glue(FloatParts,W) @@ -3588,103 +3618,35 @@ float128 float128_scalbn(float128 a, int n, float_= status *status) =20 /* * Square Root - * - * The old softfloat code did an approximation step before zeroing in - * on the final result. However for simpleness we just compute the - * square root by iterating down from the implicit bit to enough extra - * bits to ensure we get a correctly rounded result. - * - * This does mean however the calculation is slower than before, - * especially for 64 bit floats. */ =20 -static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const Floa= tFmt *p) -{ - uint64_t a_frac, r_frac, s_frac; - int bit, last_bit; - - if (is_nan(a.cls)) { - parts_return_nan(&a, s); - return a; - } - if (a.cls =3D=3D float_class_zero) { - return a; /* sqrt(+-0) =3D +-0 */ - } - if (a.sign) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - if (a.cls =3D=3D float_class_inf) { - return a; /* sqrt(+inf) =3D +inf */ - } - - assert(a.cls =3D=3D float_class_normal); - - /* We need two overflow bits at the top. Adding room for that is a - * right shift. If the exponent is odd, we can discard the low bit - * by multiplying the fraction by 2; that's a left shift. Combine - * those and we shift right by 1 if the exponent is odd, otherwise 2. - */ - a_frac =3D a.frac >> (2 - (a.exp & 1)); - a.exp >>=3D 1; - - /* Bit-by-bit computation of sqrt. */ - r_frac =3D 0; - s_frac =3D 0; - - /* Iterate from implicit bit down to the 3 extra bits to compute a - * properly rounded result. Remember we've inserted two more bits - * at the top, so these positions are two less. - */ - bit =3D DECOMPOSED_BINARY_POINT - 2; - last_bit =3D MAX(p->frac_shift - 4, 0); - do { - uint64_t q =3D 1ULL << bit; - uint64_t t_frac =3D s_frac + q; - if (t_frac <=3D a_frac) { - s_frac =3D t_frac + q; - a_frac -=3D t_frac; - r_frac +=3D q; - } - a_frac <<=3D 1; - } while (--bit >=3D last_bit); - - /* Undo the right shift done above. If there is any remaining - * fraction, the result is inexact. Set the sticky bit. - */ - a.frac =3D (r_frac << 2) + (a_frac !=3D 0); - - return a; -} - float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float16_unpack_canonical(&pa, a, status); - pr =3D sqrt_float(pa, status, &float16_params); - return float16_round_pack_canonical(&pr, status); + float16_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float16_params); + return float16_round_pack_canonical(&p, status); } =20 static float32 QEMU_SOFTFLOAT_ATTR soft_f32_sqrt(float32 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float32_unpack_canonical(&pa, a, status); - pr =3D sqrt_float(pa, status, &float32_params); - return float32_round_pack_canonical(&pr, status); + float32_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float32_params); + return float32_round_pack_canonical(&p, status); } =20 static float64 QEMU_SOFTFLOAT_ATTR soft_f64_sqrt(float64 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - float64_unpack_canonical(&pa, a, status); - pr =3D sqrt_float(pa, status, &float64_params); - return float64_round_pack_canonical(&pr, status); + float64_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float64_params); + return float64_round_pack_canonical(&p, status); } =20 float32 QEMU_FLATTEN float32_sqrt(float32 xa, float_status *s) @@ -3743,11 +3705,20 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float= _status *s) =20 bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; =20 - bfloat16_unpack_canonical(&pa, a, status); - pr =3D sqrt_float(pa, status, &bfloat16_params); - return bfloat16_round_pack_canonical(&pr, status); + bfloat16_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &bfloat16_params); + return bfloat16_round_pack_canonical(&p, status); +} + +float128 QEMU_FLATTEN float128_sqrt(float128 a, float_status *status) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float128_params); + return float128_round_pack_canonical(&p, status); } =20 /*------------------------------------------------------------------------= ---- @@ -6475,74 +6446,6 @@ float128 float128_rem(float128 a, float128 b, float_= status *status) status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the square root of the quadruple-precision floating-point value = `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_sqrt(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp, zExp; - uint64_t aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0; - uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, a, status); - } - if ( ! aSign ) return a; - goto invalid; - } - if ( aSign ) { - if ( ( aExp | aSig0 | aSig1 ) =3D=3D 0 ) return a; - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return packFloat128( 0, 0, 0, 0 = ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - zExp =3D ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE; - aSig0 |=3D UINT64_C(0x0001000000000000); - zSig0 =3D estimateSqrt32( aExp, aSig0>>17 ); - shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 ); - zSig0 =3D estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 = ); - doubleZSig0 =3D zSig0<<1; - mul64To128( zSig0, zSig0, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - doubleZSig0 -=3D 2; - add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 ); - } - zSig1 =3D estimateDiv128To64( rem1, 0, doubleZSig0 ); - if ( ( zSig1 & 0x1FFF ) <=3D 5 ) { - if ( zSig1 =3D=3D 0 ) zSig1 =3D 1; - mul64To128( doubleZSig0, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - mul64To128( zSig1, zSig1, &term2, &term3 ); - sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - shortShift128Left( 0, zSig1, 1, &term2, &term3 ); - term3 |=3D 1; - term2 |=3D doubleZSig0; - add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3= ); - } - zSig1 |=3D ( ( rem1 | rem2 | rem3 ) !=3D 0 ); - } - shift128ExtraRightJamming( zSig0, zSig1, 0, 14, &zSig0, &zSig1, &zSig2= ); - return roundAndPackFloat128(0, zExp, zSig0, zSig1, zSig2, status); - -} - static inline FloatRelation floatx80_compare_internal(floatx80 a, floatx80 b, bool is_quiet, float_status *status) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 9749c11a6b..293029711c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -595,6 +595,212 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, Float= PartsN *b, return a; } =20 +/* + * Square Root + * + * The base algorithm is lifted from + * https://git.musl-libc.org/cgit/musl/tree/src/math/sqrtf.c + * https://git.musl-libc.org/cgit/musl/tree/src/math/sqrt.c + * https://git.musl-libc.org/cgit/musl/tree/src/math/sqrtl.c + * and is thus MIT licenced. + */ +static void partsN(sqrt)(FloatPartsN *a, float_status *status, + const FloatFmt *fmt) +{ + const uint32_t three32 =3D 3u << 30; + const uint64_t three64 =3D 3ull << 62; + uint32_t d32, m32, r32, s32, u32; /* 32-bit computation */ + uint64_t d64, m64, r64, s64, u64; /* 64-bit computation */ + uint64_t dh, dl, rh, rl, sh, sl, uh, ul; /* 128-bit computation */ + uint64_t d0h, d0l, d1h, d1l, d2h, d2l; + uint64_t discard; + bool exp_odd; + size_t index; + + if (unlikely(a->cls !=3D float_class_normal)) { + switch (a->cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(a, status); + return; + case float_class_zero: + return; + case float_class_inf: + if (unlikely(a->sign)) { + goto d_nan; + } + return; + default: + g_assert_not_reached(); + } + } + + if (unlikely(a->sign)) { + goto d_nan; + } + + /* + * Argument reduction. + * x =3D 4^e frac; with integer e, and frac in [1, 4) + * m =3D frac fixed point at bit 62, since we're in base 4. + * If base-2 exponent is odd, exchange that for multiply by 2, + * which results in no shift. + */ + exp_odd =3D a->exp & 1; + index =3D extract64(a->frac_hi, 57, 6) | (!exp_odd << 6); + if (!exp_odd) { + frac_shr(a, 1); + } + + /* + * Approximate r ~=3D 1/sqrt(m) and s ~=3D sqrt(m) when m in [1, 4). + * + * Initial estimate: + * 7-bit lookup table (1-bit exponent and 6-bit significand). + * + * The relative error (e =3D r0*sqrt(m)-1) of a linear estimate + * (r0 =3D a*m + b) is |e| < 0.085955 ~ 0x1.6p-4 at best; + * a table lookup is faster and needs one less iteration. + * The 7-bit table gives |e| < 0x1.fdp-9. + * + * A Newton-Raphson iteration for r is + * s =3D m*r + * d =3D s*r + * u =3D 3 - d + * r =3D r*u/2 + * + * Fixed point representations: + * m, s, d, u, three are all 2.30; r is 0.32 + */ + m64 =3D a->frac_hi; + m32 =3D m64 >> 32; + + r32 =3D rsqrt_tab[index] << 16; + /* |r*sqrt(m) - 1| < 0x1.FDp-9 */ + + s32 =3D ((uint64_t)m32 * r32) >> 32; + d32 =3D ((uint64_t)s32 * r32) >> 32; + u32 =3D three32 - d32; + + if (N =3D=3D 64) { + /* float64 or smaller */ + + r32 =3D ((uint64_t)r32 * u32) >> 31; + /* |r*sqrt(m) - 1| < 0x1.7Bp-16 */ + + s32 =3D ((uint64_t)m32 * r32) >> 32; + d32 =3D ((uint64_t)s32 * r32) >> 32; + u32 =3D three32 - d32; + + if (fmt->frac_size <=3D 23) { + /* float32 or smaller */ + + s32 =3D ((uint64_t)s32 * u32) >> 32; /* 3.29 */ + s32 =3D (s32 - 1) >> 6; /* 9.23 */ + /* s < sqrt(m) < s + 0x1.08p-23 */ + + /* compute nearest rounded result to 2.23 bits */ + uint32_t d0 =3D (m32 << 16) - s32 * s32; + uint32_t d1 =3D s32 - d0; + uint32_t d2 =3D d1 + s32 + 1; + s32 +=3D d1 >> 31; + a->frac_hi =3D (uint64_t)s32 << (64 - 25); + + /* increment or decrement for inexact */ + if (d2 !=3D 0) { + a->frac_hi +=3D ((int32_t)(d1 ^ d2) < 0 ? -1 : 1); + } + goto done; + } + + /* float64 */ + + r64 =3D (uint64_t)r32 * u32 * 2; + /* |r*sqrt(m) - 1| < 0x1.37-p29; convert to 64-bit arithmetic */ + mul64To128(m64, r64, &s64, &discard); + mul64To128(s64, r64, &d64, &discard); + u64 =3D three64 - d64; + + mul64To128(s64, u64, &s64, &discard); /* 3.61 */ + s64 =3D (s64 - 2) >> 9; /* 12.52 */ + + /* Compute nearest rounded result */ + uint64_t d0 =3D (m64 << 42) - s64 * s64; + uint64_t d1 =3D s64 - d0; + uint64_t d2 =3D d1 + s64 + 1; + s64 +=3D d1 >> 63; + a->frac_hi =3D s64 << (64 - 54); + + /* increment or decrement for inexact */ + if (d2 !=3D 0) { + a->frac_hi +=3D ((int64_t)(d1 ^ d2) < 0 ? -1 : 1); + } + goto done; + } + + r64 =3D (uint64_t)r32 * u32 * 2; + /* |r*sqrt(m) - 1| < 0x1.7Bp-16; convert to 64-bit arithmetic */ + + mul64To128(m64, r64, &s64, &discard); + mul64To128(s64, r64, &d64, &discard); + u64 =3D three64 - d64; + mul64To128(u64, r64, &r64, &discard); + r64 <<=3D 1; + /* |r*sqrt(m) - 1| < 0x1.a5p-31 */ + + mul64To128(m64, r64, &s64, &discard); + mul64To128(s64, r64, &d64, &discard); + u64 =3D three64 - d64; + mul64To128(u64, r64, &rh, &rl); + add128(rh, rl, rh, rl, &rh, &rl); + /* |r*sqrt(m) - 1| < 0x1.c001p-59; change to 128-bit arithmetic */ + + mul128To256(a->frac_hi, a->frac_lo, rh, rl, &sh, &sl, &discard, &disca= rd); + mul128To256(sh, sl, rh, rl, &dh, &dl, &discard, &discard); + sub128(three64, 0, dh, dl, &uh, &ul); + mul128To256(uh, ul, sh, sl, &sh, &sl, &discard, &discard); /* 3.125 */ + /* -0x1p-116 < s - sqrt(m) < 0x3.8001p-125 */ + + sub128(sh, sl, 0, 4, &sh, &sl); + shift128Right(sh, sl, 13, &sh, &sl); /* 16.112 */ + /* s < sqrt(m) < s + 1ulp */ + + /* Compute nearest rounded result */ + mul64To128(sl, sl, &d0h, &d0l); + d0h +=3D 2 * sh * sl; + sub128(a->frac_lo << 34, 0, d0h, d0l, &d0h, &d0l); + sub128(sh, sl, d0h, d0l, &d1h, &d1l); + add128(sh, sl, 0, 1, &d2h, &d2l); + add128(d2h, d2l, d1h, d1l, &d2h, &d2l); + add128(sh, sl, 0, d1h >> 63, &sh, &sl); + shift128Left(sh, sl, 128 - 114, &sh, &sl); + + /* increment or decrement for inexact */ + if (d2h | d2l) { + if ((int64_t)(d1h ^ d2h) < 0) { + sub128(sh, sl, 0, 1, &sh, &sl); + } else { + add128(sh, sl, 0, 1, &sh, &sl); + } + } + a->frac_lo =3D sl; + a->frac_hi =3D sh; + + done: + /* Convert back from base 4 to base 2. */ + a->exp >>=3D 1; + if (!(a->frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + frac_add(a, a, a); + } else { + a->exp +=3D 1; + } + return; + + d_nan: + float_raise(float_flag_invalid, status); + parts_default_nan(a, status); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We will need to treat the non-normal cases of floatx80 specially, so split out the normal case that we can reuse. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 8 ++++++ fpu/softfloat-parts.c.inc | 56 ++++++++++++++++++++++----------------- 2 files changed, 39 insertions(+), 25 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 75a3bb881d..4df69029ec 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -763,6 +763,14 @@ static void parts128_canonicalize(FloatParts128 *p, fl= oat_status *status, #define parts_canonicalize(A, S, F) \ PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) =20 +static void parts64_uncanon_normal(FloatParts64 *p, float_status *status, + const FloatFmt *fmt); +static void parts128_uncanon_normal(FloatParts128 *p, float_status *status, + const FloatFmt *fmt); + +#define parts_uncanon_normal(A, S, F) \ + PARTS_GENERIC_64_128(uncanon_normal, A)(A, S, F) + static void parts64_uncanon(FloatParts64 *p, float_status *status, const FloatFmt *fmt); static void parts128_uncanon(FloatParts128 *p, float_status *status, diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 293029711c..65462bf6cb 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -140,8 +140,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_= status *status, * fraction; these bits will be removed. The exponent will be biased * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. */ -static void partsN(uncanon)(FloatPartsN *p, float_status *s, - const FloatFmt *fmt) +static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) { const int exp_max =3D fmt->exp_max; const int frac_shift =3D fmt->frac_shift; @@ -153,29 +153,6 @@ static void partsN(uncanon)(FloatPartsN *p, float_stat= us *s, bool overflow_norm; int exp, flags =3D 0; =20 - if (unlikely(p->cls !=3D float_class_normal)) { - switch (p->cls) { - case float_class_zero: - p->exp =3D 0; - frac_clear(p); - return; - case float_class_inf: - g_assert(!fmt->arm_althp); - p->exp =3D fmt->exp_max; - frac_clear(p); - return; - case float_class_qnan: - case float_class_snan: - g_assert(!fmt->arm_althp); - p->exp =3D fmt->exp_max; - frac_shr(p, fmt->frac_shift); - return; - default: - break; - } - g_assert_not_reached(); - } - switch (s->float_rounding_mode) { case float_round_nearest_even: overflow_norm =3D false; @@ -282,6 +259,35 @@ static void partsN(uncanon)(FloatPartsN *p, float_stat= us *s, float_raise(flags, s); } =20 +static void partsN(uncanon)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) +{ + if (likely(p->cls =3D=3D float_class_normal)) { + parts_uncanon_normal(p, s, fmt); + } else { + switch (p->cls) { + case float_class_zero: + p->exp =3D 0; + frac_clear(p); + return; + case float_class_inf: + g_assert(!fmt->arm_althp); + p->exp =3D fmt->exp_max; + frac_clear(p); + return; + case float_class_qnan: + case float_class_snan: + g_assert(!fmt->arm_althp); + p->exp =3D fmt->exp_max; + frac_shr(p, fmt->frac_shift); + return; + default: + break; + } + g_assert_not_reached(); + } +} + /* * Returns the result of adding or subtracting the values of the * floating-point values `a' and `b'. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Remove frac_lsb, frac_lsbm1, roundeven_mask. Compute these from round_mask in parts$N_uncanon_normal. With floatx80, round_mask will not be tied to frac_shift. Everything else is easily computable. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 29 ++++++++++++----------------- fpu/softfloat-parts.c.inc | 6 +++--- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4df69029ec..6a77e35663 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -562,9 +562,7 @@ typedef struct { * frac_size: the size of the fraction field * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_PO= INT * The following are computed based the size of fraction - * frac_lsb: least significant bit of fraction - * frac_lsbm1: the bit below the least significant bit (for rounding) - * round_mask/roundeven_mask: masks used for rounding + * round_mask: bits below lsb which must be rounded * The following optional modifiers are available: * arm_althp: handle ARM Alternative Half Precision */ @@ -574,24 +572,21 @@ typedef struct { int exp_max; int frac_size; int frac_shift; - uint64_t frac_lsb; - uint64_t frac_lsbm1; - uint64_t round_mask; - uint64_t roundeven_mask; bool arm_althp; + uint64_t round_mask; } FloatFmt; =20 /* Expand fields based on the size of exponent and fraction */ -#define FLOAT_PARAMS(E, F) \ - .exp_size =3D E, \ - .exp_bias =3D ((1 << E) - 1) >> 1, \ - .exp_max =3D (1 << E) - 1, \ - .frac_size =3D F, \ - .frac_shift =3D (-F - 1) & 63, \ - .frac_lsb =3D 1ull << ((-F - 1) & 63), \ - .frac_lsbm1 =3D 1ull << ((-F - 2) & 63), \ - .round_mask =3D (1ull << ((-F - 1) & 63)) - 1, \ - .roundeven_mask =3D (2ull << ((-F - 1) & 63)) - 1 +#define FLOAT_PARAMS_(E, F) \ + .exp_size =3D E, \ + .exp_bias =3D ((1 << E) - 1) >> 1, \ + .exp_max =3D (1 << E) - 1, \ + .frac_size =3D F + +#define FLOAT_PARAMS(E, F) \ + FLOAT_PARAMS_(E, F), \ + .frac_shift =3D (-F - 1) & 63, \ + .round_mask =3D (1ull << ((-F - 1) & 63)) - 1 =20 static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 65462bf6cb..3ee6552d5a 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -145,10 +145,10 @@ static void partsN(uncanon_normal)(FloatPartsN *p, fl= oat_status *s, { const int exp_max =3D fmt->exp_max; const int frac_shift =3D fmt->frac_shift; - const uint64_t frac_lsb =3D fmt->frac_lsb; - const uint64_t frac_lsbm1 =3D fmt->frac_lsbm1; const uint64_t round_mask =3D fmt->round_mask; - const uint64_t roundeven_mask =3D fmt->roundeven_mask; + const uint64_t frac_lsb =3D round_mask + 1; + const uint64_t frac_lsbm1 =3D round_mask ^ (round_mask >> 1); + const uint64_t roundeven_mask =3D round_mask | frac_lsb; uint64_t inc; bool overflow_norm; int exp, flags =3D 0; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441869; cv=none; d=zohomail.com; s=zohoarc; b=d9VK4xiUH2VYqNpJ2/ZgyJjsy2uatl8LjDQX+zHs2ICGpaDXt4ITNu3qLE4ShY740zxxwKJ4qxJpjCiasft36Mk91TMkA11nzHYZ24OKPyXW8Qzp+BG7ioqFVWFkmy6dh+y2F6v4ySXjwckXLh3tl2UZ70yTLnpeaWdThH+drU0= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 56/72] softfloat: Introduce Floatx80RoundPrec Date: Fri, 7 May 2021 18:47:46 -0700 Message-Id: <20210508014802.892561-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Use an enumeration instead of raw 32/64/80 values. Signed-off-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 5 +- include/fpu/softfloat-types.h | 10 +++- include/fpu/softfloat.h | 4 +- fpu/softfloat.c | 32 ++++++------ linux-user/arm/nwfpe/fpa11.c | 41 +++++++-------- target/i386/tcg/fpu_helper.c | 79 +++++++++++++++++------------ target/m68k/fpu_helper.c | 50 +++++++++--------- target/m68k/softfloat.c | 90 ++++++++++++++++++++------------- tests/fp/fp-test.c | 5 +- 9 files changed, 182 insertions(+), 134 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helper= s.h index 2f0674fbdd..34f4cf92ae 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -69,7 +69,7 @@ static inline void set_float_exception_flags(int val, flo= at_status *status) status->float_exception_flags =3D val; } =20 -static inline void set_floatx80_rounding_precision(int val, +static inline void set_floatx80_rounding_precision(FloatX80RoundPrec val, float_status *status) { status->floatx80_rounding_precision =3D val; @@ -120,7 +120,8 @@ static inline int get_float_exception_flags(float_statu= s *status) return status->float_exception_flags; } =20 -static inline int get_floatx80_rounding_precision(float_status *status) +static inline FloatX80RoundPrec +get_floatx80_rounding_precision(float_status *status) { return status->floatx80_rounding_precision; } diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8a3f20fae9..1f83378c20 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -152,6 +152,14 @@ enum { float_flag_output_denormal =3D 128 }; =20 +/* + * Rounding precision for floatx80. + */ +typedef enum __attribute__((__packed__)) { + floatx80_precision_x, + floatx80_precision_d, + floatx80_precision_s, +} FloatX80RoundPrec; =20 /* * Floating Point Status. Individual architectures may maintain @@ -163,7 +171,7 @@ enum { typedef struct float_status { FloatRoundMode float_rounding_mode; uint8_t float_exception_flags; - signed char floatx80_rounding_precision; + FloatX80RoundPrec floatx80_rounding_precision; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 53f2c2ea3c..94f7841b9f 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1152,7 +1152,7 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b,= float_status *status); | Floating-Point Arithmetic. *-------------------------------------------------------------------------= ---*/ =20 -floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, +floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zS= ign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status); =20 @@ -1165,7 +1165,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, bool zSign, | normalized. *-------------------------------------------------------------------------= ---*/ =20 -floatx80 normalizeRoundAndPackFloatx80(int8_t roundingPrecision, +floatx80 normalizeRoundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6a77e35663..441b8f9dc1 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4344,10 +4344,10 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int3= 2_t *zExpPtr, | a subnormal number, and the underflow and inexact exceptions are raised = if | the abstract input cannot be represented exactly as a subnormal extended | double-precision floating-point number. -| If `roundingPrecision' is 32 or 64, the result is rounded to the same -| number of bits as single or double precision, respectively. Otherwise, = the -| result is rounded to the full precision of the extended double-precision -| format. +| If `roundingPrecision' is floatx80_precision_s or floatx80_precision= _d, +| the result is rounded to the same number of bits as single or double +| precision, respectively. Otherwise, the result is rounded to the full +| precision of the extended double-precision format. | The input significand must be normalized or smaller. If the input | significand is not normalized, `zExp' must be 0; in that case, the result | returned is a subnormal number, and it must not require rounding. The @@ -4355,27 +4355,29 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int3= 2_t *zExpPtr, | Floating-Point Arithmetic. *-------------------------------------------------------------------------= ---*/ =20 -floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, +floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zS= ign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status) { - int8_t roundingMode; + FloatRoundMode roundingMode; bool roundNearestEven, increment, isTiny; int64_t roundIncrement, roundMask, roundBits; =20 roundingMode =3D status->float_rounding_mode; roundNearestEven =3D ( roundingMode =3D=3D float_round_nearest_even ); - if ( roundingPrecision =3D=3D 80 ) goto precision80; - if ( roundingPrecision =3D=3D 64 ) { + switch (roundingPrecision) { + case floatx80_precision_x: + goto precision80; + case floatx80_precision_d: roundIncrement =3D UINT64_C(0x0000000000000400); roundMask =3D UINT64_C(0x00000000000007FF); - } - else if ( roundingPrecision =3D=3D 32 ) { + break; + case floatx80_precision_s: roundIncrement =3D UINT64_C(0x0000008000000000); roundMask =3D UINT64_C(0x000000FFFFFFFFFF); - } - else { - goto precision80; + break; + default: + g_assert_not_reached(); } zSig0 |=3D ( zSig1 !=3D 0 ); switch (roundingMode) { @@ -4552,7 +4554,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecisio= n, bool zSign, | normalized. *-------------------------------------------------------------------------= ---*/ =20 -floatx80 normalizeRoundAndPackFloatx80(int8_t roundingPrecision, +floatx80 normalizeRoundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status) @@ -6205,7 +6207,7 @@ floatx80 floatx80_modrem(floatx80 a, floatx80 b, bool= mod, uint64_t *quotient, } return normalizeRoundAndPackFloatx80( - 80, zSign, bExp + expDiff, aSig0, aSig1, status); + floatx80_precision_x, zSign, bExp + expDiff, aSig0, aSig1, sta= tus); =20 } =20 diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index f6f8163eab..9a93610d24 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -97,37 +97,38 @@ void SetRoundingMode(const unsigned int opcode) =20 void SetRoundingPrecision(const unsigned int opcode) { - int rounding_precision; - FPA11 *fpa11 =3D GET_FPA11(); + FloatX80RoundPrec rounding_precision; + FPA11 *fpa11 =3D GET_FPA11(); #ifdef MAINTAIN_FPCR - fpa11->fpcr &=3D ~MASK_ROUNDING_PRECISION; + fpa11->fpcr &=3D ~MASK_ROUNDING_PRECISION; #endif - switch (opcode & MASK_ROUNDING_PRECISION) - { - case ROUND_SINGLE: - rounding_precision =3D 32; + switch (opcode & MASK_ROUNDING_PRECISION) { + case ROUND_SINGLE: + rounding_precision =3D floatx80_precision_s; #ifdef MAINTAIN_FPCR - fpa11->fpcr |=3D ROUND_SINGLE; + fpa11->fpcr |=3D ROUND_SINGLE; #endif - break; + break; =20 - case ROUND_DOUBLE: - rounding_precision =3D 64; + case ROUND_DOUBLE: + rounding_precision =3D floatx80_precision_d; #ifdef MAINTAIN_FPCR - fpa11->fpcr |=3D ROUND_DOUBLE; + fpa11->fpcr |=3D ROUND_DOUBLE; #endif - break; + break; =20 - case ROUND_EXTENDED: - rounding_precision =3D 80; + case ROUND_EXTENDED: + rounding_precision =3D floatx80_precision_x; #ifdef MAINTAIN_FPCR - fpa11->fpcr |=3D ROUND_EXTENDED; + fpa11->fpcr |=3D ROUND_EXTENDED; #endif - break; + break; =20 - default: rounding_precision =3D 80; - } - set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status); + default: + rounding_precision =3D floatx80_precision_x; + break; + } + set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status); } =20 /* Emulate the instruction in the opcode. */ diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 60ed93520a..e495ddf1aa 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -711,38 +711,40 @@ uint32_t helper_fnstcw(CPUX86State *env) =20 void update_fp_status(CPUX86State *env) { - int rnd_type; + FloatRoundMode rnd_mode; + FloatX80RoundPrec rnd_prec; =20 /* set rounding mode */ switch (env->fpuc & FPU_RC_MASK) { default: case FPU_RC_NEAR: - rnd_type =3D float_round_nearest_even; + rnd_mode =3D float_round_nearest_even; break; case FPU_RC_DOWN: - rnd_type =3D float_round_down; + rnd_mode =3D float_round_down; break; case FPU_RC_UP: - rnd_type =3D float_round_up; + rnd_mode =3D float_round_up; break; case FPU_RC_CHOP: - rnd_type =3D float_round_to_zero; + rnd_mode =3D float_round_to_zero; break; } - set_float_rounding_mode(rnd_type, &env->fp_status); + set_float_rounding_mode(rnd_mode, &env->fp_status); + switch ((env->fpuc >> 8) & 3) { case 0: - rnd_type =3D 32; + rnd_prec =3D floatx80_precision_s; break; case 2: - rnd_type =3D 64; + rnd_prec =3D floatx80_precision_d; break; case 3: default: - rnd_type =3D 80; + rnd_prec =3D floatx80_precision_x; break; } - set_floatx80_rounding_precision(rnd_type, &env->fp_status); + set_floatx80_rounding_precision(rnd_prec, &env->fp_status); } =20 void helper_fldcw(CPUX86State *env, uint32_t val) @@ -1112,7 +1114,8 @@ void helper_f2xm1(CPUX86State *env) &sig2); /* This result is inexact. */ sig1 |=3D 1; - ST0 =3D normalizeRoundAndPackFloatx80(80, sign, exp, sig0, sig= 1, + ST0 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + sign, exp, sig0, sig1, &env->fp_status); } } else { @@ -1121,9 +1124,10 @@ void helper_f2xm1(CPUX86State *env) int32_t n, aexp, bexp; uint64_t asig0, asig1, asig2, bsig0, bsig1; FloatRoundMode save_mode =3D env->fp_status.float_rounding_mode; - signed char save_prec =3D env->fp_status.floatx80_rounding_precisi= on; + FloatX80RoundPrec save_prec =3D + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode =3D float_round_nearest_even; - env->fp_status.floatx80_rounding_precision =3D 80; + env->fp_status.floatx80_rounding_precision =3D floatx80_precision_= x; =20 /* Find the nearest multiple of 1/32 to the argument. */ tmp =3D floatx80_scalbn(ST0, 5, &env->fp_status); @@ -1221,7 +1225,8 @@ void helper_f2xm1(CPUX86State *env) env->fp_status.float_rounding_mode =3D save_mode; /* This result is inexact. */ asig1 |=3D 1; - ST0 =3D normalizeRoundAndPackFloatx80(80, asign, aexp, asig0, = asig1, + ST0 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + asign, aexp, asig0, asig1, &env->fp_status); } =20 @@ -1339,8 +1344,9 @@ void helper_fpatan(CPUX86State *env) * division is exact, the result of fpatan is still inexact * (and underflowing where appropriate). */ - signed char save_prec =3D env->fp_status.floatx80_rounding_precisi= on; - env->fp_status.floatx80_rounding_precision =3D 80; + FloatX80RoundPrec save_prec =3D + env->fp_status.floatx80_rounding_precision; + env->fp_status.floatx80_rounding_precision =3D floatx80_precision_= x; ST1 =3D floatx80_div(ST1, ST0, &env->fp_status); env->fp_status.floatx80_rounding_precision =3D save_prec; if (!floatx80_is_zero(ST1) && @@ -1359,7 +1365,8 @@ void helper_fpatan(CPUX86State *env) if (exp =3D=3D 0) { normalizeFloatx80Subnormal(sig, &exp, &sig); } - ST1 =3D normalizeRoundAndPackFloatx80(80, sign, exp, sig - 1, + ST1 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + sign, exp, sig - 1, -1, &env->fp_status); } } else { @@ -1415,9 +1422,10 @@ void helper_fpatan(CPUX86State *env) uint64_t azsig2, azsig3, axsig0, axsig1; floatx80 x8; FloatRoundMode save_mode =3D env->fp_status.float_rounding_mod= e; - signed char save_prec =3D env->fp_status.floatx80_rounding_pre= cision; + FloatX80RoundPrec save_prec =3D + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode =3D float_round_nearest_eve= n; - env->fp_status.floatx80_rounding_precision =3D 80; + env->fp_status.floatx80_rounding_precision =3D floatx80_precis= ion_x; =20 if (arg0_exp =3D=3D 0) { normalizeFloatx80Subnormal(arg0_sig, &arg0_exp, &arg0_sig); @@ -1486,7 +1494,8 @@ void helper_fpatan(CPUX86State *env) * Split x as x =3D t + y, where t =3D n/8 is the nearest * multiple of 1/8 to x. */ - x8 =3D normalizeRoundAndPackFloatx80(80, false, xexp + 3, xsig= 0, + x8 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + false, xexp + 3, xsig0, xsig1, &env->fp_status); n =3D floatx80_to_int32(x8, &env->fp_status); if (n =3D=3D 0) { @@ -1607,7 +1616,7 @@ void helper_fpatan(CPUX86State *env) /* Compute z^2. */ mul128To256(zsig0, zsig1, zsig0, zsig1, &z2sig0, &z2sig1, &z2sig2, &z2sig3); - z2 =3D normalizeRoundAndPackFloatx80(80, false, + z2 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x,= false, zexp + zexp - 0x3ffe, z2sig0, z2sig1, &env->fp_status); @@ -1727,7 +1736,7 @@ void helper_fpatan(CPUX86State *env) } /* This result is inexact. */ rsig1 |=3D 1; - ST1 =3D normalizeRoundAndPackFloatx80(80, rsign, rexp, + ST1 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, rsign,= rexp, rsig0, rsig1, &env->fp_status); } =20 @@ -1928,7 +1937,8 @@ static void helper_fyl2x_common(CPUX86State *env, flo= atx80 arg, int32_t *exp, */ mul128To256(tsig0, tsig1, tsig0, tsig1, &t2sig0, &t2sig1, &t2sig2, &t2sig3); - t2 =3D normalizeRoundAndPackFloatx80(80, false, texp + texp - 0x3ffe, + t2 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, false, + texp + texp - 0x3ffe, t2sig0, t2sig1, &env->fp_status); =20 /* Compute the lower parts of the polynomial expansion. */ @@ -2042,15 +2052,17 @@ void helper_fyl2xp1(CPUX86State *env) exp +=3D arg1_exp - 0x3ffe; /* This result is inexact. */ sig1 |=3D 1; - ST1 =3D normalizeRoundAndPackFloatx80(80, arg0_sign ^ arg1_sign, e= xp, + ST1 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + arg0_sign ^ arg1_sign, exp, sig0, sig1, &env->fp_status); } else { int32_t aexp; uint64_t asig0, asig1, asig2; FloatRoundMode save_mode =3D env->fp_status.float_rounding_mode; - signed char save_prec =3D env->fp_status.floatx80_rounding_precisi= on; + FloatX80RoundPrec save_prec =3D + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode =3D float_round_nearest_even; - env->fp_status.floatx80_rounding_precision =3D 80; + env->fp_status.floatx80_rounding_precision =3D floatx80_precision_= x; =20 helper_fyl2x_common(env, ST0, &aexp, &asig0, &asig1); /* @@ -2065,7 +2077,8 @@ void helper_fyl2xp1(CPUX86State *env) /* This result is inexact. */ asig1 |=3D 1; env->fp_status.float_rounding_mode =3D save_mode; - ST1 =3D normalizeRoundAndPackFloatx80(80, arg0_sign ^ arg1_sign, a= exp, + ST1 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + arg0_sign ^ arg1_sign, aexp, asig0, asig1, &env->fp_status); env->fp_status.floatx80_rounding_precision =3D save_prec; } @@ -2149,9 +2162,10 @@ void helper_fyl2x(CPUX86State *env) int32_t int_exp; floatx80 arg0_m1; FloatRoundMode save_mode =3D env->fp_status.float_rounding_mode; - signed char save_prec =3D env->fp_status.floatx80_rounding_precisi= on; + FloatX80RoundPrec save_prec =3D + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode =3D float_round_nearest_even; - env->fp_status.floatx80_rounding_precision =3D 80; + env->fp_status.floatx80_rounding_precision =3D floatx80_precision_= x; =20 if (arg0_exp =3D=3D 0) { normalizeFloatx80Subnormal(arg0_sig, &arg0_exp, &arg0_sig); @@ -2208,7 +2222,8 @@ void helper_fyl2x(CPUX86State *env) /* This result is inexact. */ asig1 |=3D 1; env->fp_status.float_rounding_mode =3D save_mode; - ST1 =3D normalizeRoundAndPackFloatx80(80, asign ^ arg1_sign, a= exp, + ST1 =3D normalizeRoundAndPackFloatx80(floatx80_precision_x, + asign ^ arg1_sign, aexp, asig0, asig1, &env->fp_sta= tus); } =20 @@ -2290,12 +2305,12 @@ void helper_fscale(CPUX86State *env) } } else { int n; - signed char save =3D env->fp_status.floatx80_rounding_precision; + FloatX80RoundPrec save =3D env->fp_status.floatx80_rounding_precis= ion; uint8_t save_flags =3D get_float_exception_flags(&env->fp_status); set_float_exception_flags(0, &env->fp_status); n =3D floatx80_to_int32_round_to_zero(ST1, &env->fp_status); set_float_exception_flags(save_flags, &env->fp_status); - env->fp_status.floatx80_rounding_precision =3D 80; + env->fp_status.floatx80_rounding_precision =3D floatx80_precision_= x; ST0 =3D floatx80_scalbn(ST0, n, &env->fp_status); env->fp_status.floatx80_rounding_precision =3D save; } diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 797000e748..fdc4937e29 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -94,13 +94,13 @@ static void m68k_restore_precision_mode(CPUM68KState *e= nv) { switch (env->fpcr & FPCR_PREC_MASK) { case FPCR_PREC_X: /* extended */ - set_floatx80_rounding_precision(80, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_x, &env->fp_sta= tus); break; case FPCR_PREC_S: /* single */ - set_floatx80_rounding_precision(32, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_s, &env->fp_sta= tus); break; case FPCR_PREC_D: /* double */ - set_floatx80_rounding_precision(64, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_d, &env->fp_sta= tus); break; case FPCR_PREC_U: /* undefined */ default: @@ -111,9 +111,9 @@ static void m68k_restore_precision_mode(CPUM68KState *e= nv) static void cf_restore_precision_mode(CPUM68KState *env) { if (env->fpcr & FPCR_PREC_S) { /* single */ - set_floatx80_rounding_precision(32, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_s, &env->fp_sta= tus); } else { /* double */ - set_floatx80_rounding_precision(64, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_d, &env->fp_sta= tus); } } =20 @@ -166,8 +166,8 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) =20 #define PREC_BEGIN(prec) \ do { \ - int old; \ - old =3D get_floatx80_rounding_precision(&env->fp_status); \ + FloatX80RoundPrec old =3D \ + get_floatx80_rounding_precision(&env->fp_status); \ set_floatx80_rounding_precision(prec, &env->fp_status) \ =20 #define PREC_END() \ @@ -176,14 +176,14 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) =20 void HELPER(fsround)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_round(val->d, &env->fp_status); PREC_END(); } =20 void HELPER(fdround)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_round(val->d, &env->fp_status); PREC_END(); } @@ -195,14 +195,14 @@ void HELPER(fsqrt)(CPUM68KState *env, FPReg *res, FPR= eg *val) =20 void HELPER(fssqrt)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_sqrt(val->d, &env->fp_status); PREC_END(); } =20 void HELPER(fdsqrt)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_sqrt(val->d, &env->fp_status); PREC_END(); } @@ -214,14 +214,14 @@ void HELPER(fabs)(CPUM68KState *env, FPReg *res, FPRe= g *val) =20 void HELPER(fsabs)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_round(floatx80_abs(val->d), &env->fp_status); PREC_END(); } =20 void HELPER(fdabs)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_round(floatx80_abs(val->d), &env->fp_status); PREC_END(); } @@ -233,14 +233,14 @@ void HELPER(fneg)(CPUM68KState *env, FPReg *res, FPRe= g *val) =20 void HELPER(fsneg)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_round(floatx80_chs(val->d), &env->fp_status); PREC_END(); } =20 void HELPER(fdneg)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_round(floatx80_chs(val->d), &env->fp_status); PREC_END(); } @@ -252,14 +252,14 @@ void HELPER(fadd)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) =20 void HELPER(fsadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_add(val0->d, val1->d, &env->fp_status); PREC_END(); } =20 void HELPER(fdadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_add(val0->d, val1->d, &env->fp_status); PREC_END(); } @@ -271,14 +271,14 @@ void HELPER(fsub)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) =20 void HELPER(fssub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_sub(val1->d, val0->d, &env->fp_status); PREC_END(); } =20 void HELPER(fdsub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_sub(val1->d, val0->d, &env->fp_status); PREC_END(); } @@ -290,14 +290,14 @@ void HELPER(fmul)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) =20 void HELPER(fsmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_mul(val0->d, val1->d, &env->fp_status); PREC_END(); } =20 void HELPER(fdmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_mul(val0->d, val1->d, &env->fp_status); PREC_END(); } @@ -307,7 +307,7 @@ void HELPER(fsglmul)(CPUM68KState *env, FPReg *res, FPR= eg *val0, FPReg *val1) FloatRoundMode rounding_mode =3D get_float_rounding_mode(&env->fp_stat= us); floatx80 a, b; =20 - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); set_float_rounding_mode(float_round_to_zero, &env->fp_status); a =3D floatx80_round(val0->d, &env->fp_status); b =3D floatx80_round(val1->d, &env->fp_status); @@ -323,14 +323,14 @@ void HELPER(fdiv)(CPUM68KState *env, FPReg *res, FPRe= g *val0, FPReg *val1) =20 void HELPER(fsdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d =3D floatx80_div(val1->d, val0->d, &env->fp_status); PREC_END(); } =20 void HELPER(fddiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d =3D floatx80_div(val1->d, val0->d, &env->fp_status); PREC_END(); } @@ -340,7 +340,7 @@ void HELPER(fsgldiv)(CPUM68KState *env, FPReg *res, FPR= eg *val0, FPReg *val1) FloatRoundMode rounding_mode =3D get_float_rounding_mode(&env->fp_stat= us); floatx80 a, b; =20 - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); set_float_rounding_mode(float_round_to_zero, &env->fp_status); a =3D floatx80_round(val1->d, &env->fp_status); b =3D floatx80_round(val0->d, &env->fp_status); diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index b6d0ed7acf..02dcc03d15 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -227,7 +227,8 @@ floatx80 floatx80_lognp1(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig, fSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, j, k; floatx80 fp0, fp1, fp2, fp3, f, logof2, klog2, saveu; @@ -270,7 +271,7 @@ floatx80 floatx80_lognp1(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -426,7 +427,8 @@ floatx80 floatx80_logn(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig, fSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, j, k, adjk; floatx80 fp0, fp1, fp2, fp3, f, logof2, klog2, saveu; @@ -469,7 +471,7 @@ floatx80 floatx80_logn(floatx80 a, float_status *status) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -594,7 +596,8 @@ floatx80 floatx80_log10(floatx80 a, float_status *statu= s) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 floatx80 fp0, fp1; =20 @@ -626,7 +629,7 @@ floatx80 floatx80_log10(floatx80 a, float_status *statu= s) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 fp0 =3D floatx80_logn(a, status); fp1 =3D packFloatx80(0, 0x3FFD, UINT64_C(0xDE5BD8A937287195)); /* INV_= L10 */ @@ -651,7 +654,8 @@ floatx80 floatx80_log2(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 floatx80 fp0, fp1; =20 @@ -686,7 +690,7 @@ floatx80 floatx80_log2(floatx80 a, float_status *status) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 if (aSig =3D=3D one_sig) { /* X is 2^k */ status->float_rounding_mode =3D user_rnd_mode; @@ -718,7 +722,8 @@ floatx80 floatx80_etox(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, n, j, k, m, m1; floatx80 fp0, fp1, fp2, fp3, l2, scale, adjscale; @@ -746,7 +751,7 @@ floatx80 floatx80_etox(floatx80 a, float_status *status) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 adjflag =3D 0; =20 @@ -902,7 +907,8 @@ floatx80 floatx80_twotox(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, n, j, l, m, m1; floatx80 fp0, fp1, fp2, fp3, adjfact, fact1, fact2; @@ -929,7 +935,7 @@ floatx80 floatx80_twotox(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 fp0 =3D a; =20 @@ -1052,7 +1058,8 @@ floatx80 floatx80_tentox(floatx80 a, float_status *st= atus) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, n, j, l, m, m1; floatx80 fp0, fp1, fp2, fp3, adjfact, fact1, fact2; @@ -1079,7 +1086,7 @@ floatx80 floatx80_tentox(floatx80 a, float_status *st= atus) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 fp0 =3D a; =20 @@ -1207,7 +1214,8 @@ floatx80 floatx80_tan(floatx80 a, float_status *statu= s) int32_t aExp, xExp; uint64_t aSig, xSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, l, n, j; floatx80 fp0, fp1, fp2, fp3, fp4, fp5, invtwopi, twopi1, twopi2; @@ -1233,7 +1241,7 @@ floatx80 floatx80_tan(floatx80 a, float_status *statu= s) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -1417,7 +1425,8 @@ floatx80 floatx80_sin(floatx80 a, float_status *statu= s) int32_t aExp, xExp; uint64_t aSig, xSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, l, n, j; floatx80 fp0, fp1, fp2, fp3, fp4, fp5, x, invtwopi, twopi1, twopi2; @@ -1443,7 +1452,7 @@ floatx80 floatx80_sin(floatx80 a, float_status *statu= s) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -1656,7 +1665,8 @@ floatx80 floatx80_cos(floatx80 a, float_status *statu= s) int32_t aExp, xExp; uint64_t aSig, xSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, l, n, j; floatx80 fp0, fp1, fp2, fp3, fp4, fp5, x, invtwopi, twopi1, twopi2; @@ -1682,7 +1692,7 @@ floatx80 floatx80_cos(floatx80 a, float_status *statu= s) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -1893,7 +1903,8 @@ floatx80 floatx80_atan(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, tbl_index; floatx80 fp0, fp1, fp2, fp3, xsave; @@ -1920,7 +1931,7 @@ floatx80 floatx80_atan(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 if (compact < 0x3FFB8000 || compact > 0x4002FFFF) { /* |X| >=3D 16 or |X| < 1/16 */ @@ -2090,7 +2101,8 @@ floatx80 floatx80_asin(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact; floatx80 fp0, fp1, fp2, one; @@ -2124,7 +2136,7 @@ floatx80 floatx80_asin(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 one =3D packFloatx80(0, one_exp, one_sig); fp0 =3D a; @@ -2155,7 +2167,8 @@ floatx80 floatx80_acos(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact; floatx80 fp0, fp1, one; @@ -2193,7 +2206,7 @@ floatx80 floatx80_acos(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 one =3D packFloatx80(0, one_exp, one_sig); fp0 =3D a; @@ -2224,7 +2237,8 @@ floatx80 floatx80_atanh(floatx80 a, float_status *sta= tus) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact; floatx80 fp0, fp1, fp2, one; @@ -2257,7 +2271,7 @@ floatx80 floatx80_atanh(floatx80 a, float_status *sta= tus) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 one =3D packFloatx80(0, one_exp, one_sig); fp2 =3D packFloatx80(aSign, 0x3FFE, one_sig); /* SIGN(X) * (1/2) */ @@ -2289,7 +2303,8 @@ floatx80 floatx80_etoxm1(floatx80 a, float_status *st= atus) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact, n, j, m, m1; floatx80 fp0, fp1, fp2, fp3, l2, sc, onebysc; @@ -2316,7 +2331,7 @@ floatx80 floatx80_etoxm1(floatx80 a, float_status *st= atus) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 if (aExp >=3D 0x3FFD) { /* |X| >=3D 1/4 */ compact =3D floatx80_make_compact(aExp, aSig); @@ -2541,7 +2556,8 @@ floatx80 floatx80_tanh(floatx80 a, float_status *stat= us) int32_t aExp, vExp; uint64_t aSig, vSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact; floatx80 fp0, fp1; @@ -2565,7 +2581,7 @@ floatx80 floatx80_tanh(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -2656,7 +2672,8 @@ floatx80 floatx80_sinh(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact; floatx80 fp0, fp1, fp2; @@ -2681,7 +2698,7 @@ floatx80 floatx80_sinh(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 @@ -2744,7 +2761,8 @@ floatx80 floatx80_cosh(floatx80 a, float_status *stat= us) int32_t aExp; uint64_t aSig; =20 - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; =20 int32_t compact; floatx80 fp0, fp1; @@ -2767,7 +2785,7 @@ floatx80 floatx80_cosh(floatx80 a, float_status *stat= us) user_rnd_mode =3D status->float_rounding_mode; user_rnd_prec =3D status->floatx80_rounding_precision; status->float_rounding_mode =3D float_round_nearest_even; - status->floatx80_rounding_precision =3D 80; + status->floatx80_rounding_precision =3D floatx80_precision_x; =20 compact =3D floatx80_make_compact(aExp, aSig); =20 diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index ff131afbde..1be3a9788a 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -963,18 +963,21 @@ static void QEMU_NORETURN run_test(void) verCases_usesExact =3D !!(attrs & FUNC_ARG_EXACT); =20 for (k =3D 0; k < 3; k++) { + FloatX80RoundPrec qsf_prec80 =3D floatx80_precision_s; int prec80 =3D 32; int l; =20 if (k =3D=3D 1) { prec80 =3D 64; + qsf_prec80 =3D floatx80_precision_d; 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Fri, 07 May 2021 18:51:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 57/72] softfloat: Adjust parts_uncanon_normal for floatx80 Date: Fri, 7 May 2021 18:47:47 -0700 Message-Id: <20210508014802.892561-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" With floatx80_precision_x, the rounding happens across the break between words. Notice this case with frac_lsb =3D round_mask + 1 -> 0 and check the bits in frac_hi as needed. In addition, since frac_shift =3D=3D 0, we won't implicitly clear round_mask via the right-shift, so explicitly clear those bits. This fixes rounding for floatx80_precision_[sd]. Signed-off-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3ee6552d5a..c18f77f2cf 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -156,7 +156,13 @@ static void partsN(uncanon_normal)(FloatPartsN *p, flo= at_status *s, switch (s->float_rounding_mode) { case float_round_nearest_even: overflow_norm =3D false; - inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm= 1 : 0); + if (N > 64 && frac_lsb =3D=3D 0) { + inc =3D ((p->frac_hi & 1) || (p->frac_lo & round_mask) !=3D fr= ac_lsbm1 + ? frac_lsbm1 : 0); + } else { + inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 + ? frac_lsbm1 : 0); + } break; case float_round_ties_away: overflow_norm =3D false; @@ -176,7 +182,11 @@ static void partsN(uncanon_normal)(FloatPartsN *p, flo= at_status *s, break; case float_round_to_odd: overflow_norm =3D true; - inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; + if (N > 64 && frac_lsb =3D=3D 0) { + inc =3D p->frac_hi & 1 ? 0 : round_mask; + } else { + inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; + } break; default: g_assert_not_reached(); @@ -191,8 +201,8 @@ static void partsN(uncanon_normal)(FloatPartsN *p, floa= t_status *s, p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; exp++; } + p->frac_lo &=3D ~round_mask; } - frac_shr(p, frac_shift); =20 if (fmt->arm_althp) { /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ @@ -201,18 +211,21 @@ static void partsN(uncanon_normal)(FloatPartsN *p, fl= oat_status *s, flags =3D float_flag_invalid; exp =3D exp_max; frac_allones(p); + p->frac_lo &=3D ~round_mask; } } else if (unlikely(exp >=3D exp_max)) { flags |=3D float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp =3D exp_max - 1; frac_allones(p); + p->frac_lo &=3D ~round_mask; } else { p->cls =3D float_class_inf; exp =3D exp_max; frac_clear(p); } } + frac_shr(p, frac_shift); } else if (s->flush_to_zero) { flags |=3D float_flag_output_denormal; p->cls =3D float_class_zero; @@ -232,17 +245,28 @@ static void partsN(uncanon_normal)(FloatPartsN *p, fl= oat_status *s, /* Need to recompute round-to-even/round-to-odd. */ switch (s->float_rounding_mode) { case float_round_nearest_even: - inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 - ? frac_lsbm1 : 0); + if (N > 64 && frac_lsb =3D=3D 0) { + inc =3D ((p->frac_hi & 1) || + (p->frac_lo & round_mask) !=3D frac_lsbm1 + ? frac_lsbm1 : 0); + } else { + inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 + ? frac_lsbm1 : 0); + } break; case float_round_to_odd: - inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; + if (N > 64 && frac_lsb =3D=3D 0) { + inc =3D p->frac_hi & 1 ? 0 : round_mask; + } else { + inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; + } break; default: break; } flags |=3D float_flag_inexact; frac_addi(p, p, inc); + p->frac_lo &=3D ~round_mask; } =20 exp =3D (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) !=3D 0; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Many qemu softfloat will check floatx80_rounding_precision even when berkeley testfloat will not. So begin with floatx80_precision_x, so that's the one we use when !FUNC_EFF_ROUNDINGPRECISION. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tests/fp/fp-test.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 1be3a9788a..352dd71c44 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -963,16 +963,16 @@ static void QEMU_NORETURN run_test(void) verCases_usesExact =3D !!(attrs & FUNC_ARG_EXACT); =20 for (k =3D 0; k < 3; k++) { - FloatX80RoundPrec qsf_prec80 =3D floatx80_precision_s; - int prec80 =3D 32; + FloatX80RoundPrec qsf_prec80 =3D floatx80_precision_x; + int prec80 =3D 80; int l; =20 if (k =3D=3D 1) { prec80 =3D 64; qsf_prec80 =3D floatx80_precision_d; } else if (k =3D=3D 2) { - prec80 =3D 80; - qsf_prec80 =3D floatx80_precision_x; + prec80 =3D 32; + qsf_prec80 =3D floatx80_precision_s; } =20 verCases_roundingPrecision =3D 0; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 07 May 2021 18:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 59/72] softfloat: Convert floatx80_add/sub to FloatParts Date: Fri, 7 May 2021 18:47:49 -0700 Message-Id: <20210508014802.892561-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since this is the first such, this includes all of the packing and unpacking routines as well. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 339 +++++++++++++++++++----------------------------- 1 file changed, 136 insertions(+), 203 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 441b8f9dc1..3c6751e4d0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -577,14 +577,14 @@ typedef struct { } FloatFmt; =20 /* Expand fields based on the size of exponent and fraction */ -#define FLOAT_PARAMS_(E, F) \ +#define FLOAT_PARAMS_(E) \ .exp_size =3D E, \ .exp_bias =3D ((1 << E) - 1) >> 1, \ - .exp_max =3D (1 << E) - 1, \ - .frac_size =3D F + .exp_max =3D (1 << E) - 1 =20 #define FLOAT_PARAMS(E, F) \ - FLOAT_PARAMS_(E, F), \ + FLOAT_PARAMS_(E), \ + .frac_size =3D F, \ .frac_shift =3D (-F - 1) & 63, \ .round_mask =3D (1ull << ((-F - 1) & 63)) - 1 =20 @@ -613,6 +613,18 @@ static const FloatFmt float128_params =3D { FLOAT_PARAMS(15, 112) }; =20 +#define FLOATX80_PARAMS(R) \ + FLOAT_PARAMS_(15), \ + .frac_size =3D R =3D=3D 64 ? 63 : R, \ + .frac_shift =3D 0, \ + .round_mask =3D R =3D=3D 64 ? -1 : (1ull << ((-R - 1) & 63)) - 1 + +static const FloatFmt floatx80_params[3] =3D { + [floatx80_precision_s] =3D { FLOATX80_PARAMS(23) }, + [floatx80_precision_d] =3D { FLOATX80_PARAMS(52) }, + [floatx80_precision_x] =3D { FLOATX80_PARAMS(64) }, +}; + /* Unpack a float to parts, but do not canonicalize. */ static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t ra= w) { @@ -647,6 +659,16 @@ static inline void float64_unpack_raw(FloatParts64 *p,= float64 f) unpack_raw64(p, &float64_params, f); } =20 +static void floatx80_unpack_raw(FloatParts128 *p, floatx80 f) +{ + *p =3D (FloatParts128) { + .cls =3D float_class_unclassified, + .sign =3D extract32(f.high, 15, 1), + .exp =3D extract32(f.high, 0, 15), + .frac_hi =3D f.low + }; +} + static void float128_unpack_raw(FloatParts128 *p, float128 f) { const int f_size =3D float128_params.frac_size - 64; @@ -1535,6 +1557,92 @@ static float128 float128_round_pack_canonical(FloatP= arts128 *p, return float128_pack_raw(p); } =20 +/* Returns false if the encoding is invalid. */ +static bool floatx80_unpack_canonical(FloatParts128 *p, floatx80 f, + float_status *s) +{ + /* Ensure rounding precision is set before beginning. */ + switch (s->floatx80_rounding_precision) { + case floatx80_precision_x: + case floatx80_precision_d: + case floatx80_precision_s: + break; + default: + g_assert_not_reached(); + } + + if (unlikely(floatx80_invalid_encoding(f))) { + float_raise(float_flag_invalid, s); + return false; + } + + floatx80_unpack_raw(p, f); + + if (likely(p->exp !=3D floatx80_params[floatx80_precision_x].exp_max))= { + parts_canonicalize(p, s, &floatx80_params[floatx80_precision_x]); + } else { + /* The explicit integer bit is ignored, after invalid checks. */ + p->frac_hi &=3D MAKE_64BIT_MASK(0, 63); + p->cls =3D (p->frac_hi =3D=3D 0 ? float_class_inf + : parts_is_snan_frac(p->frac_hi, s) + ? float_class_snan : float_class_qnan); + } + return true; +} + +static floatx80 floatx80_round_pack_canonical(FloatParts128 *p, + float_status *s) +{ + const FloatFmt *fmt =3D &floatx80_params[s->floatx80_rounding_precisio= n]; + uint64_t frac; + int exp; + + switch (p->cls) { + case float_class_normal: + if (s->floatx80_rounding_precision =3D=3D floatx80_precision_x) { + parts_uncanon_normal(p, s, fmt); + frac =3D p->frac_hi; + exp =3D p->exp; + } else { + FloatParts64 p64; + + p64.sign =3D p->sign; + p64.exp =3D p->exp; + frac_truncjam(&p64, p); + parts_uncanon_normal(&p64, s, fmt); + frac =3D p64.frac; + exp =3D p64.exp; + } + if (exp !=3D fmt->exp_max) { + break; + } + /* rounded to inf -- fall through to set frac correctly */ + + case float_class_inf: + /* x86 and m68k differ in the setting of the integer bit. */ + frac =3D floatx80_infinity_low; + exp =3D fmt->exp_max; + break; + + case float_class_zero: + frac =3D 0; + exp =3D 0; + break; + + case float_class_snan: + case float_class_qnan: + /* NaNs have the integer bit set. */ + frac =3D p->frac_hi | (1ull << 63); + exp =3D fmt->exp_max; + break; + + default: + g_assert_not_reached(); + } + + return packFloatx80(p->sign, exp, frac); +} + /* * Addition and subtraction */ @@ -1724,6 +1832,30 @@ float128 float128_sub(float128 a, float128 b, float_= status *status) return float128_addsub(a, b, status, true); } =20 +static floatx80 QEMU_FLATTEN +floatx80_addsub(floatx80 a, floatx80 b, float_status *status, bool subtrac= t) +{ + FloatParts128 pa, pb, *pr; + + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + + pr =3D parts_addsub(&pa, &pb, status, subtract); + return floatx80_round_pack_canonical(pr, status); +} + +floatx80 floatx80_add(floatx80 a, floatx80 b, float_status *status) +{ + return floatx80_addsub(a, b, status, false); +} + +floatx80 floatx80_sub(floatx80 a, floatx80 b, float_status *status) +{ + return floatx80_addsub(a, b, status, true); +} + /* * Multiplication */ @@ -5733,205 +5865,6 @@ floatx80 floatx80_round_to_int(floatx80 a, float_st= atus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the absolute values of the extended double- -| precision floating-point values `a' and `b'. If `zSign' is 1, the sum is -| negated before being returned. `zSign' is ignored if the result is a Na= N. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static floatx80 addFloatx80Sigs(floatx80 a, floatx80 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - int32_t expDiff; - - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - bSig =3D extractFloatx80Frac( b ); - bExp =3D extractFloatx80Exp( b ); - expDiff =3D aExp - bExp; - if ( 0 < expDiff ) { - if ( aExp =3D=3D 0x7FFF ) { - if ((uint64_t)(aSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) --expDiff; - shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 ); - zExp =3D aExp; - } - else if ( expDiff < 0 ) { - if ( bExp =3D=3D 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return packFloatx80(zSign, - floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp =3D=3D 0 ) ++expDiff; - shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); - zExp =3D bExp; - } - else { - if ( aExp =3D=3D 0x7FFF ) { - if ( (uint64_t) ( ( aSig | bSig )<<1 ) ) { - return propagateFloatx80NaN(a, b, status); - } - return a; - } - zSig1 =3D 0; - zSig0 =3D aSig + bSig; - if ( aExp =3D=3D 0 ) { - if ((aSig | bSig) & UINT64_C(0x8000000000000000) && zSig0 < aS= ig) { - /* At least one of the values is a pseudo-denormal, - * and there is a carry out of the result. */ - zExp =3D 1; - goto shiftRight1; - } - if (zSig0 =3D=3D 0) { - return packFloatx80(zSign, 0, 0); - } - normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 ); - goto roundAndPack; - } - zExp =3D aExp; - goto shiftRight1; - } - zSig0 =3D aSig + bSig; - if ( (int64_t) zSig0 < 0 ) goto roundAndPack; - shiftRight1: - shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 ); - zSig0 |=3D UINT64_C(0x8000000000000000); - ++zExp; - roundAndPack: - return roundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the absolute values of the extended -| double-precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -static floatx80 subFloatx80Sigs(floatx80 a, floatx80 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - int32_t expDiff; - - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - bSig =3D extractFloatx80Frac( b ); - bExp =3D extractFloatx80Exp( b ); - expDiff =3D aExp - bExp; - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp =3D=3D 0x7FFF ) { - if ( (uint64_t) ( ( aSig | bSig )<<1 ) ) { - return propagateFloatx80NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - aExp =3D 1; - bExp =3D 1; - } - zSig1 =3D 0; - if ( bSig < aSig ) goto aBigger; - if ( aSig < bSig ) goto bBigger; - return packFloatx80(status->float_rounding_mode =3D=3D float_round_dow= n, 0, 0); - bExpBigger: - if ( bExp =3D=3D 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return packFloatx80(zSign ^ 1, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp =3D=3D 0 ) ++expDiff; - shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); - bBigger: - sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 ); - zExp =3D bExp; - zSign ^=3D 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp =3D=3D 0x7FFF ) { - if ((uint64_t)(aSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) --expDiff; - shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 ); - aBigger: - sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 ); - zExp =3D aExp; - normalizeRoundAndPack: - return normalizeRoundAndPackFloatx80(status->floatx80_rounding_precisi= on, - zSign, zExp, zSig0, zSig1, status= ); -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of adding the extended double-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_add(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSign =3D extractFloatx80Sign( a ); - bSign =3D extractFloatx80Sign( b ); - if ( aSign =3D=3D bSign ) { - return addFloatx80Sigs(a, b, aSign, status); - } - else { - return subFloatx80Sigs(a, b, aSign, status); - } - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of subtracting the extended double-precision floating- -| point values `a' and `b'. The operation is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_sub(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSign =3D extractFloatx80Sign( a ); - bSign =3D extractFloatx80Sign( b ); - if ( aSign =3D=3D bSign ) { - return subFloatx80Sigs(a, b, aSign, status); - } - else { - return addFloatx80Sigs(a, b, aSign, status); - } - -} - /*------------------------------------------------------------------------= ---- | Returns the result of multiplying the extended double-precision floating- | point values `a' and `b'. The operation is performed according to the --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441698; cv=none; d=zohomail.com; s=zohoarc; b=Msb/hI5t1XY4dMBeCwLekoNHyUOPtzxSc25FKyFYBSu7BJiQfACoMg7nTxPI7ejdNDJIMiEvi/WIaEgvpX3dFkSWkhkHZAKm+nQ146SmtKuI8iXFszfXx6oVKntBgzMq5q/F8bwA1N7BYzF5HuVp2haFyMeTlIEbOxtSYL66Vkw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441698; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jj12YuLJHh6Oh0IVnZb6UWCqmTi7ol2b4RGLMuxGRMs=; b=U/+H4fkbbMLSHSrO5y11uSjtltW2jAnBi97FdjlaJD6g2A8xYGsVKw/7BU6B9Dh0j+AiO5rsTIwuTvT0FSoX6qn3MfC+LzM3KLtD+sQHORS8esSoefxOdlPlaXK3gt/+zwaQeSfhxJ9wpYoBdBfPNOwhy/6WqFPOIAPbukbMXCM= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 76 +++++++++---------------------------------------- 1 file changed, 14 insertions(+), 62 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3c6751e4d0..4454219f8a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1943,6 +1943,20 @@ float128_mul(float128 a, float128 b, float_status *s= tatus) return float128_round_pack_canonical(pr, status); } =20 +floatx80 QEMU_FLATTEN +floatx80_mul(floatx80 a, floatx80 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + + pr =3D parts_mul(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); +} + /* * Fused multiply-add */ @@ -5865,68 +5879,6 @@ floatx80 floatx80_round_to_int(floatx80 a, float_sta= tus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of multiplying the extended double-precision floating- -| point values `a' and `b'. The operation is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_mul(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - bSig =3D extractFloatx80Frac( b ); - bExp =3D extractFloatx80Exp( b ); - bSign =3D extractFloatx80Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FFF ) { - if ( (uint64_t) ( aSig<<1 ) - || ( ( bExp =3D=3D 0x7FFF ) && (uint64_t) ( bSig<<1 ) ) ) { - return propagateFloatx80NaN(a, b, status); - } - if ( ( bExp | bSig ) =3D=3D 0 ) goto invalid; - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( bExp =3D=3D 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - if ( ( aExp | aSig ) =3D=3D 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloatx80( zSign, 0, 0 ); - normalizeFloatx80Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) return packFloatx80( zSign, 0, 0 ); - normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); - } - zExp =3D aExp + bExp - 0x3FFE; - mul64To128( aSig, bSig, &zSig0, &zSig1 ); - if ( 0 < (int64_t) zSig0 ) { - shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 ); - --zExp; - } - return roundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - /*------------------------------------------------------------------------= ---- | Returns the result of dividing the extended double-precision floating-po= int | value `a' by the corresponding value `b'. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 100 +++++++----------------------------------------- 1 file changed, 13 insertions(+), 87 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4454219f8a..352f359bc5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2293,6 +2293,19 @@ float128_div(float128 a, float128 b, float_status *s= tatus) return float128_round_pack_canonical(pr, status); } =20 +floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + + pr =3D parts_div(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); +} + /* * Float to Float conversions * @@ -5879,93 +5892,6 @@ floatx80 floatx80_round_to_int(floatx80 a, float_sta= tus *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of dividing the extended double-precision floating-po= int -| value `a' by the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - uint64_t rem0, rem1, rem2, term0, term1, term2; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - bSig =3D extractFloatx80Frac( b ); - bExp =3D extractFloatx80Exp( b ); - bSign =3D extractFloatx80Sign( b ); - zSign =3D aSign ^ bSign; - if ( aExp =3D=3D 0x7FFF ) { - if ((uint64_t)(aSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - if ( bExp =3D=3D 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - goto invalid; - } - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( bExp =3D=3D 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return packFloatx80( zSign, 0, 0 ); - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) { - if ( ( aExp | aSig ) =3D=3D 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - float_raise(float_flag_divbyzero, status); - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloatx80( zSign, 0, 0 ); - normalizeFloatx80Subnormal( aSig, &aExp, &aSig ); - } - zExp =3D aExp - bExp + 0x3FFE; - rem1 =3D 0; - if ( bSig <=3D aSig ) { - shift128Right( aSig, 0, 1, &aSig, &rem1 ); - ++zExp; - } - zSig0 =3D estimateDiv128To64( aSig, rem1, bSig ); - mul64To128( bSig, zSig0, &term0, &term1 ); - sub128( aSig, rem1, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - add128( rem0, rem1, 0, bSig, &rem0, &rem1 ); - } - zSig1 =3D estimateDiv128To64( rem1, 0, bSig ); - if ( (uint64_t) ( zSig1<<1 ) <=3D 8 ) { - mul64To128( bSig, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - add128( rem1, rem2, 0, bSig, &rem1, &rem2 ); - } - zSig1 |=3D ( ( rem1 | rem2 ) !=3D 0 ); - } - return roundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the extended double-precision floating-point va= lue | `a' with respect to the corresponding value `b'. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 82 +++++++------------------------------------------ 1 file changed, 11 insertions(+), 71 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 352f359bc5..7050d8f012 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3883,6 +3883,17 @@ float128 QEMU_FLATTEN float128_sqrt(float128 a, floa= t_status *status) return float128_round_pack_canonical(&p, status); } =20 +floatx80 floatx80_sqrt(floatx80 a, float_status *s) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, s)) { + return floatx80_default_nan(s); + } + parts_sqrt(&p, s, &floatx80_params[s->floatx80_rounding_precision]); + return floatx80_round_pack_canonical(&p, s); +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated NaN. *-------------------------------------------------------------------------= ---*/ @@ -6046,77 +6057,6 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_= status *status) return floatx80_modrem(a, b, true, "ient, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the square root of the extended double-precision floating-point -| value `a'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_sqrt(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp, zExp; - uint64_t aSig0, aSig1, zSig0, zSig1, doubleZSig0; - uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig0 =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ((uint64_t)(aSig0 << 1)) { - return propagateFloatx80NaN(a, a, status); - } - if ( ! aSign ) return a; - goto invalid; - } - if ( aSign ) { - if ( ( aExp | aSig0 ) =3D=3D 0 ) return a; - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - if ( aExp =3D=3D 0 ) { - if ( aSig0 =3D=3D 0 ) return packFloatx80( 0, 0, 0 ); - normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 ); - } - zExp =3D ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF; - zSig0 =3D estimateSqrt32( aExp, aSig0>>32 ); - shift128Right( aSig0, 0, 2 + ( aExp & 1 ), &aSig0, &aSig1 ); - zSig0 =3D estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 = ); - doubleZSig0 =3D zSig0<<1; - mul64To128( zSig0, zSig0, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - doubleZSig0 -=3D 2; - add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 ); - } - zSig1 =3D estimateDiv128To64( rem1, 0, doubleZSig0 ); - if ( ( zSig1 & UINT64_C(0x3FFFFFFFFFFFFFFF) ) <=3D 5 ) { - if ( zSig1 =3D=3D 0 ) zSig1 =3D 1; - mul64To128( doubleZSig0, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - mul64To128( zSig1, zSig1, &term2, &term3 ); - sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - shortShift128Left( 0, zSig1, 1, &term2, &term3 ); - term3 |=3D 1; - term2 |=3D doubleZSig0; - add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3= ); - } - zSig1 |=3D ( ( rem1 | rem2 | rem3 ) !=3D 0 ); - } - shortShift128Left( 0, zSig1, 1, &zSig0, &zSig1 ); - zSig0 |=3D doubleZSig0; - return roundAndPackFloatx80(status->floatx80_rounding_precision, - 0, zExp, zSig0, zSig1, status); -} - /*------------------------------------------------------------------------= ---- | Returns the result of converting the quadruple-precision floating-point | value `a' to the extended double-precision floating-point format. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 7050d8f012..faccc8df41 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5794,10 +5794,12 @@ float128 floatx80_to_float128(floatx80 a, float_sta= tus *status) =20 floatx80 floatx80_round(floatx80 a, float_status *status) { - return roundAndPackFloatx80(status->floatx80_rounding_precision, - extractFloatx80Sign(a), - extractFloatx80Exp(a), - extractFloatx80Frac(a), 0, status); + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, status)) { + return floatx80_default_nan(status); + } + return floatx80_round_pack_canonical(&p, status); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441485; cv=none; d=zohomail.com; s=zohoarc; b=L17KImyvn+5ZfpCZvjRquFMRRy5p7TLknRrRkAfX14nKXhl+4fP1czSedcVNIEaw1MrDqaTcOAYdUOlS5e14y64S229kf4bNnuppZm/YhcjtcvIflaHmnr+rLOcjQDle5OnxywwrATfvW0UYZxTlBPhTHOfcMAidHbA1+SbP2mo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441485; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 116 ++++++------------------------------------------ 1 file changed, 13 insertions(+), 103 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index faccc8df41..914cf2688c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2609,6 +2609,19 @@ float128 float128_round_to_int(float128 a, float_sta= tus *s) return float128_round_pack_canonical(&p, s); } =20 +floatx80 floatx80_round_to_int(floatx80 a, float_status *status) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, status)) { + return floatx80_default_nan(status); + } + + parts_round_to_int(&p, status->float_rounding_mode, 0, status, + &floatx80_params[status->floatx80_rounding_precisio= n]); + return floatx80_round_pack_canonical(&p, status); +} + /* * Floating-point to signed integer conversions */ @@ -5802,109 +5815,6 @@ floatx80 floatx80_round(floatx80 a, float_status *s= tatus) return floatx80_round_pack_canonical(&p, status); } =20 -/*------------------------------------------------------------------------= ---- -| Rounds the extended double-precision floating-point value `a' to an inte= ger, -| and returns the result as an extended quadruple-precision floating-point -| value. The operation is performed according to the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_round_to_int(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t lastBitMask, roundBitsMask; - floatx80 z; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aExp =3D extractFloatx80Exp( a ); - if ( 0x403E <=3D aExp ) { - if ( ( aExp =3D=3D 0x7FFF ) && (uint64_t) ( extractFloatx80Frac( a= )<<1 ) ) { - return propagateFloatx80NaN(a, a, status); - } - return a; - } - if ( aExp < 0x3FFF ) { - if ( ( aExp =3D=3D 0 ) - && ( (uint64_t) ( extractFloatx80Frac( a ) ) =3D=3D 0 ) ) { - return a; - } - float_raise(float_flag_inexact, status); - aSign =3D extractFloatx80Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp =3D=3D 0x3FFE ) && (uint64_t) ( extractFloatx80Fra= c( a )<<1 ) - ) { - return - packFloatx80( aSign, 0x3FFF, UINT64_C(0x80000000000000= 00)); - } - break; - case float_round_ties_away: - if (aExp =3D=3D 0x3FFE) { - return packFloatx80(aSign, 0x3FFF, UINT64_C(0x800000000000= 0000)); - } - break; - case float_round_down: - return - aSign ? - packFloatx80( 1, 0x3FFF, UINT64_C(0x8000000000000000= )) - : packFloatx80( 0, 0, 0 ); - case float_round_up: - return - aSign ? packFloatx80( 1, 0, 0 ) - : packFloatx80( 0, 0x3FFF, UINT64_C(0x8000000000000000)); - - case float_round_to_zero: - break; - default: - g_assert_not_reached(); - } - return packFloatx80( aSign, 0, 0 ); - } - lastBitMask =3D 1; - lastBitMask <<=3D 0x403E - aExp; - roundBitsMask =3D lastBitMask - 1; - z =3D a; - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z.low +=3D lastBitMask>>1; - if ((z.low & roundBitsMask) =3D=3D 0) { - z.low &=3D ~lastBitMask; - } - break; - case float_round_ties_away: - z.low +=3D lastBitMask >> 1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloatx80Sign(z)) { - z.low +=3D roundBitsMask; - } - break; - case float_round_down: - if (extractFloatx80Sign(z)) { - z.low +=3D roundBitsMask; - } - break; - default: - abort(); - } - z.low &=3D ~ roundBitsMask; - if ( z.low =3D=3D 0 ) { - ++z.high; - z.low =3D UINT64_C(0x8000000000000000); - } - if (z.low !=3D a.low) { - float_raise(float_flag_inexact, status); - } - return z; - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the extended double-precision floating-point va= lue | `a' with respect to the corresponding value `b'. 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j0n+VHMEDjMKtgDcOQxDeJHVUUgoF67rvW1U9FdzS+U=; b=fGZwim5aUac0MTIXPz96MLhgk1ibtxSBXexbPxnEXbbhrHs9u7SfZLpb+KXZWDGeAf Ryt3cpSdT3RX4TKIaFHoeXkwwyBndmKHDXAItZUMus3DnSSMaHRb1TzSzh6m8TxIDrkk GBtyY5VKTaXoiu0kgDQFAlEDPDWM8Pf4/TybxlZJnShl8gBfvAYyxVMr7VAbNYaETESB oj4X+rSfF48JFNtzvFxVFYDQ5W+paQKyw4EqmRdLF7tu75bRYqfNF69jiAbcldY7Egp8 xUI7LvJvMA0SwptaD7WKChDa4T3wHRvvBLEDn8NKFiC0Y1OK+NNIlL1+vSiIR9GGkDnn 27rw== X-Gm-Message-State: AOAM532YslYT8FtwyP+yGn3Wq0977s9AtaHWFLLvqx6SGWU2kQxgSKpW VkkEfIds/ZIl/+0FldfUBAoNypoZCW2olQ== X-Google-Smtp-Source: ABdhPJx7FQyCmrNe1XaL7vIo1a88tzP66fj7Ae2drZoiMzmNs/gA6tPGYDfbzGWK30753RjvwpcsYg== X-Received: by 2002:a17:90a:be10:: with SMTP id a16mr25054610pjs.112.1620438705955; Fri, 07 May 2021 18:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 65/72] softfloat: Convert integer to floatx80 to FloatParts Date: Fri, 7 May 2021 18:47:55 -0700 Message-Id: <20210508014802.892561-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 58 +++++++++++-------------------------------------- 1 file changed, 13 insertions(+), 45 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 914cf2688c..82f71896ac 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3344,6 +3344,19 @@ float128 int32_to_float128(int32_t a, float_status *= status) return int64_to_float128(a, status); } =20 +floatx80 int64_to_floatx80(int64_t a, float_status *status) +{ + FloatParts128 p; + + parts_sint_to_float(&p, a, 0, status); + return floatx80_round_pack_canonical(&p, status); +} + +floatx80 int32_to_floatx80(int32_t a, float_status *status) +{ + return int64_to_floatx80(a, status); +} + /* * Unsigned Integer to floating-point conversions */ @@ -5035,51 +5048,6 @@ static float128 normalizeRoundAndPackFloat128(bool z= Sign, int32_t zExp, =20 } =20 - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the 32-bit two's complement integer `a' -| to the extended double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 int32_to_floatx80(int32_t a, float_status *status) -{ - bool zSign; - uint32_t absA; - int8_t shiftCount; - uint64_t zSig; - - if ( a =3D=3D 0 ) return packFloatx80( 0, 0, 0 ); - zSign =3D ( a < 0 ); - absA =3D zSign ? - a : a; - shiftCount =3D clz32(absA) + 32; - zSig =3D absA; - return packFloatx80( zSign, 0x403E - shiftCount, zSig< (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1620441335748212.12644732920216; Fri, 7 May 2021 19:35:35 -0700 (PDT) Received: from localhost ([::1]:60586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCoY-0007b3-Kx for importer@patchew.org; Fri, 07 May 2021 22:35:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC8M-0003Wk-LM for qemu-devel@nongnu.org; Fri, 07 May 2021 21:52:00 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:33294) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC8B-0005Zs-UM for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:57 -0400 Received: by mail-pj1-x102a.google.com with SMTP id b14-20020a17090a6e0eb0290155c7f6a356so5542382pjk.0 for ; Fri, 07 May 2021 18:51:47 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=krbccElr6YBGv/dTDG8O6hv4U6UMSoNxQsDJQmD9EcE=; b=gYq0cjMvPMbh0vFKsUhAveW1xnYBWLRtdjRjiud7ZdJZdL44RKnXpE/+SSMCP7E+pL +g4t1a5avnqdtBfgrUtAli9YOl5KxF7CR5phwb/q/V6LhPBtJKM4fM6Nux78XQSLFq6p NKbFSnId+/zMPNMvjEMZML+aBsE6q0A9YTEzMERolaWYhaj5zYggovW1ydyKJtFogC20 SWDFP5aPEB6VB8+rGKu8284EmUQlkj2j6faTWbo1v7b+TAEKpVbzZgPqY7wgnewougB1 bFRgamlytLAUQ024d9dMQAo/n/VPqZ2w1w2PMmB8N9o4SVhec1t6dbZLnWwSya1K0BYc TOug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=krbccElr6YBGv/dTDG8O6hv4U6UMSoNxQsDJQmD9EcE=; b=N49FvzB0HL8/ZAbSMcMOrH6LlOFq+5DeOZ1zoCEroTl05aygGS8DnTi1XDFEX6KVYq gG8DE+vmGhhPzNVFQG/tn/oBQsWs9vuG/RRPt/VFx+ePjGBz9RnBpx2om6x1yXx1Tqjd Atu4KDFUGyDU9Fp3mD2DqdGe5ATBQa0nQEnqR4zCZ9D9fgzSNJ84iot8k4v6Yg9gNXZO m6vtMrgyEwYcEEGtGAIiKj9yiSVaFjs+zmVfbMFp42Pecx01sasOVSUyGasojoZvLC/f 2ph+zLIJXBaYqWhAqxq+XRBicJTQ6XvED46W2G1rpmsCHbybRWfmAmaCB/qBL9InWesI JAEw== X-Gm-Message-State: AOAM533eyRH1WFMjrtKBOifxF1rgzgMYLNF6CZdJY+e6g2ETsP5MQ2GZ Af5xAtjMJemnTPOpnfMfIRoGXHFokkDfaA== X-Google-Smtp-Source: ABdhPJxa8q+UyDvp8AdtKb5WRYjzUnstoPgZEc9A2mS9e7gc3OEObSQN0bE0sbd+bo4BnRD3acHrrw== X-Received: by 2002:a17:90a:744e:: with SMTP id o14mr1621318pjk.96.1620438706637; Fri, 07 May 2021 18:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 66/72] softfloat: Convert floatx80 float conversions to FloatParts Date: Fri, 7 May 2021 18:47:56 -0700 Message-Id: <20210508014802.892561-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This is the last use of commonNaNT and all of the routines that use it, so remove all of them for Werror. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 276 ++++++++------------------------- fpu/softfloat-specialize.c.inc | 175 --------------------- 2 files changed, 67 insertions(+), 384 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 82f71896ac..d7c6c37d99 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2560,6 +2560,73 @@ float128 float64_to_float128(float64 a, float_status= *s) return float128_round_pack_canonical(&p128, s); } =20 +float32 floatx80_to_float32(floatx80 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + if (floatx80_unpack_canonical(&p128, a, s)) { + parts_float_to_float_narrow(&p64, &p128, s); + } else { + parts_default_nan(&p64, s); + } + return float32_round_pack_canonical(&p64, s); +} + +float64 floatx80_to_float64(floatx80 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + if (floatx80_unpack_canonical(&p128, a, s)) { + parts_float_to_float_narrow(&p64, &p128, s); + } else { + parts_default_nan(&p64, s); + } + return float64_round_pack_canonical(&p64, s); +} + +float128 floatx80_to_float128(floatx80 a, float_status *s) +{ + FloatParts128 p; + + if (floatx80_unpack_canonical(&p, a, s)) { + parts_float_to_float(&p, s); + } else { + parts_default_nan(&p, s); + } + return float128_round_pack_canonical(&p, s); +} + +floatx80 float32_to_floatx80(float32 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float32_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return floatx80_round_pack_canonical(&p128, s); +} + +floatx80 float64_to_floatx80(float64 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float64_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return floatx80_round_pack_canonical(&p128, s); +} + +floatx80 float128_to_floatx80(float128 a, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return floatx80_round_pack_canonical(&p, s); +} + /* * Round to integral value */ @@ -5048,42 +5115,6 @@ static float128 normalizeRoundAndPackFloat128(bool z= Sign, int32_t zExp, =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point val= ue -| `a' to the extended double-precision floating-point format. The convers= ion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 float32_to_floatx80(float32 a, float_status *status) -{ - bool aSign; - int aExp; - uint32_t aSig; - - a =3D float32_squash_input_denormal(a, status); - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - floatx80 res =3D commonNaNToFloatx80(float32ToCommonNaN(a, sta= tus), - status); - return floatx80_silence_nan(res, status); - } - return packFloatx80(aSign, - floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloatx80( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - aSig |=3D 0x00800000; - return packFloatx80( aSign, aExp + 0x3F80, ( (uint64_t) aSig )<<40 ); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5320,43 +5351,6 @@ float32 float32_log2(float32 a, float_status *status) return normalizeRoundAndPackFloat32(zSign, 0x85, zSig, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point val= ue -| `a' to the extended double-precision floating-point format. The convers= ion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 float64_to_floatx80(float64 a, float_status *status) -{ - bool aSign; - int aExp; - uint64_t aSig; - - a =3D float64_squash_input_denormal(a, status); - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - floatx80 res =3D commonNaNToFloatx80(float64ToCommonNaN(a, sta= tus), - status); - return floatx80_silence_nan(res, status); - } - return packFloatx80(aSign, - floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloatx80( aSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - return - packFloatx80( - aSign, aExp + 0x3C00, (aSig | UINT64_C(0x0010000000000000)) <<= 11); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the double-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5667,104 +5661,6 @@ int64_t floatx80_to_int64_round_to_zero(floatx80 a,= float_status *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the single-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 floatx80_to_float32(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ( (uint64_t) ( aSig<<1 ) ) { - float32 res =3D commonNaNToFloat32(floatx80ToCommonNaN(a, stat= us), - status); - return float32_silence_nan(res, status); - } - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 33, &aSig ); - if ( aExp || aSig ) aExp -=3D 0x3F81; - return roundAndPackFloat32(aSign, aExp, aSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the double-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 floatx80_to_float64(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig, zSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ( (uint64_t) ( aSig<<1 ) ) { - float64 res =3D commonNaNToFloat64(floatx80ToCommonNaN(a, stat= us), - status); - return float64_silence_nan(res, status); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - shift64RightJamming( aSig, 1, &zSig ); - if ( aExp || aSig ) aExp -=3D 0x3C01; - return roundAndPackFloat64(aSign, aExp, zSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the quadruple-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 floatx80_to_float128(floatx80 a, float_status *status) -{ - bool aSign; - int aExp; - uint64_t aSig, zSig0, zSig1; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - if ( ( aExp =3D=3D 0x7FFF ) && (uint64_t) ( aSig<<1 ) ) { - float128 res =3D commonNaNToFloat128(floatx80ToCommonNaN(a, status= ), - status); - return float128_silence_nan(res, status); - } - shift128Right( aSig<<1, 0, 16, &zSig0, &zSig1 ); - return packFloat128( aSign, aExp, zSig0, zSig1 ); - -} - /*------------------------------------------------------------------------= ---- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the @@ -5937,44 +5833,6 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_= status *status) return floatx80_modrem(a, b, true, "ient, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the extended double-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 float128_to_floatx80(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig0 | aSig1 ) { - floatx80 res =3D commonNaNToFloatx80(float128ToCommonNaN(a, st= atus), - status); - return floatx80_silence_nan(res, status); - } - return packFloatx80(aSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp =3D=3D 0 ) { - if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return packFloatx80( aSign, 0, 0= ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - else { - aSig0 |=3D UINT64_C(0x0001000000000000); - } - shortShift128Left( aSig0, aSig1, 15, &aSig0, &aSig1 ); - return roundAndPackFloatx80(80, aSign, aExp, aSig0, aSig1, status); - -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the quadruple-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a0cf016b4f..88eab344df 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -257,14 +257,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity =3D make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); =20 -/*------------------------------------------------------------------------= ---- -| Internal canonical NaN format. -*-------------------------------------------------------------------------= ---*/ -typedef struct { - bool sign; - uint64_t high, low; -} commonNaNT; - /*------------------------------------------------------------------------= ---- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -380,46 +372,6 @@ bool float32_is_signaling_nan(float32 a_, float_status= *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the single-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static commonNaNT float32ToCommonNaN(float32 a, float_status *status) -{ - commonNaNT z; - - if (float32_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign =3D float32_val(a) >> 31; - z.low =3D 0; - z.high =3D ((uint64_t)float32_val(a)) << 41; - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the canonical NaN `a' to the single- -| precision floating-point format. -*-------------------------------------------------------------------------= ---*/ - -static float32 commonNaNToFloat32(commonNaNT a, float_status *status) -{ - uint32_t mantissa =3D a.high >> 41; - - if (status->default_nan_mode) { - return float32_default_nan(status); - } - - if (mantissa) { - return make_float32( - (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); - } else { - return float32_default_nan(status); - } -} - /*------------------------------------------------------------------------= ---- | Select which NaN to propagate for a two-input operation. | IEEE754 doesn't specify all the details of this, so the @@ -780,48 +732,6 @@ bool float64_is_signaling_nan(float64 a_, float_status= *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the double-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static commonNaNT float64ToCommonNaN(float64 a, float_status *status) -{ - commonNaNT z; - - if (float64_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign =3D float64_val(a) >> 63; - z.low =3D 0; - z.high =3D float64_val(a) << 12; - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the canonical NaN `a' to the double- -| precision floating-point format. -*-------------------------------------------------------------------------= ---*/ - -static float64 commonNaNToFloat64(commonNaNT a, float_status *status) -{ - uint64_t mantissa =3D a.high >> 12; - - if (status->default_nan_mode) { - return float64_default_nan(status); - } - - if (mantissa) { - return make_float64( - (((uint64_t) a.sign) << 63) - | UINT64_C(0x7FF0000000000000) - | (a.high >> 12)); - } else { - return float64_default_nan(status); - } -} - /*------------------------------------------------------------------------= ---- | Takes two double-precision floating-point values `a' and `b', one of whi= ch | is a NaN, and returns the appropriate NaN result. If either `a' or `b' = is a @@ -941,55 +851,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status= *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the extended double-precision floating- -| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, t= he -| invalid exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) -{ - floatx80 dflt; - commonNaNT z; - - if (floatx80_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - if (a.low >> 63) { - z.sign =3D a.high >> 15; - z.low =3D 0; - z.high =3D a.low << 1; - } else { - dflt =3D floatx80_default_nan(status); - z.sign =3D dflt.high >> 15; - z.low =3D 0; - z.high =3D dflt.low << 1; - } - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the canonical NaN `a' to the extended -| double-precision floating-point format. -*-------------------------------------------------------------------------= ---*/ - -static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) -{ - floatx80 z; - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.high >> 1) { - z.low =3D UINT64_C(0x8000000000000000) | a.high >> 1; - z.high =3D (((uint16_t)a.sign) << 15) | 0x7FFF; - } else { - z =3D floatx80_default_nan(status); - } - return z; -} - /*------------------------------------------------------------------------= ---- | Takes two extended double-precision floating-point values `a' and `b', o= ne | of which is a NaN, and returns the appropriate NaN result. If either `a= ' or @@ -1082,42 +943,6 @@ bool float128_is_signaling_nan(float128 a, float_stat= us *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the quadruple-precision floating-point = NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static commonNaNT float128ToCommonNaN(float128 a, float_status *status) -{ - commonNaNT z; - - if (float128_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign =3D a.high >> 63; - shortShift128Left(a.high, a.low, 16, &z.high, &z.low); - return z; -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the canonical NaN `a' to the quadruple- -| precision floating-point format. -*-------------------------------------------------------------------------= ---*/ - -static float128 commonNaNToFloat128(commonNaNT a, float_status *status) -{ - float128 z; - - if (status->default_nan_mode) { - return float128_default_nan(status); - } - - shift128Right(a.high, a.low, 16, &z.high, &z.low); - z.high |=3D (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); - return z; -} - /*------------------------------------------------------------------------= ---- | Takes two quadruple-precision floating-point values `a' and `b', one of | which is a NaN, and returns the appropriate NaN result. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 336 ++++++------------------------------------------ 1 file changed, 42 insertions(+), 294 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d7c6c37d99..9f28c5c058 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2828,6 +2828,28 @@ static int64_t float128_to_int64_scalbn(float128 a, = FloatRoundMode rmode, return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } =20 +static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, s)) { + parts_default_nan(&p, s); + } + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); +} + +static int64_t floatx80_to_int64_scalbn(floatx80 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, s)) { + parts_default_nan(&p, s); + } + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); +} + int8_t float16_to_int8(float16 a, float_status *s) { return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s); @@ -2888,6 +2910,16 @@ int64_t float128_to_int64(float128 a, float_status *= s) return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s); } =20 +int32_t floatx80_to_int32(floatx80 a, float_status *s) +{ + return floatx80_to_int32_scalbn(a, s->float_rounding_mode, 0, s); +} + +int64_t floatx80_to_int64(floatx80 a, float_status *s) +{ + return floatx80_to_int64_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16_round_to_zero(float16 a, float_status *s) { return float16_to_int16_scalbn(a, float_round_to_zero, 0, s); @@ -2943,6 +2975,16 @@ int64_t float128_to_int64_round_to_zero(float128 a, = float_status *s) return float128_to_int64_scalbn(a, float_round_to_zero, 0, s); } =20 +int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *s) +{ + return floatx80_to_int32_scalbn(a, float_round_to_zero, 0, s); +} + +int64_t floatx80_to_int64_round_to_zero(floatx80 a, float_status *s) +{ + return floatx80_to_int64_scalbn(a, float_round_to_zero, 0, s); +} + int16_t bfloat16_to_int16(bfloat16 a, float_status *s) { return bfloat16_to_int16_scalbn(a, s->float_rounding_mode, 0, s); @@ -4162,127 +4204,6 @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a,= float_status *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 -| and 7, and returns the properly rounded 32-bit integer corresponding to = the -| input. If `zSign' is 1, the input is negated before being converted to = an -| integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point in= put -| is simply rounded to an integer, with the inexact exception raised if the -| input cannot be represented exactly as an integer. However, if the fixe= d- -| point input is too large, the invalid exception is raised and the largest -| positive or negative integer is returned. -*-------------------------------------------------------------------------= ---*/ - -static int32_t roundAndPackInt32(bool zSign, uint64_t absZ, - float_status *status) -{ - int8_t roundingMode; - bool roundNearestEven; - int8_t roundIncrement, roundBits; - int32_t z; - - roundingMode =3D status->float_rounding_mode; - roundNearestEven =3D ( roundingMode =3D=3D float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - roundIncrement =3D 0x40; - break; - case float_round_to_zero: - roundIncrement =3D 0; - break; - case float_round_up: - roundIncrement =3D zSign ? 0 : 0x7f; - break; - case float_round_down: - roundIncrement =3D zSign ? 0x7f : 0; - break; - case float_round_to_odd: - roundIncrement =3D absZ & 0x80 ? 0 : 0x7f; - break; - default: - abort(); - } - roundBits =3D absZ & 0x7F; - absZ =3D ( absZ + roundIncrement )>>7; - if (!(roundBits ^ 0x40) && roundNearestEven) { - absZ &=3D ~1; - } - z =3D absZ; - if ( zSign ) z =3D - z; - if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) { - float_raise(float_flag_invalid, status); - return zSign ? INT32_MIN : INT32_MAX; - } - if (roundBits) { - float_raise(float_flag_inexact, status); - } - return z; - -} - -/*------------------------------------------------------------------------= ---- -| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and -| `absZ1', with binary point between bits 63 and 64 (between the input wor= ds), -| and returns the properly rounded 64-bit integer corresponding to the inp= ut. -| If `zSign' is 1, the input is negated before being converted to an integ= er. -| Ordinarily, the fixed-point input is simply rounded to an integer, with -| the inexact exception raised if the input cannot be represented exactly = as -| an integer. However, if the fixed-point input is too large, the invalid -| exception is raised and the largest positive or negative integer is -| returned. -*-------------------------------------------------------------------------= ---*/ - -static int64_t roundAndPackInt64(bool zSign, uint64_t absZ0, uint64_t absZ= 1, - float_status *status) -{ - int8_t roundingMode; - bool roundNearestEven, increment; - int64_t z; - - roundingMode =3D status->float_rounding_mode; - roundNearestEven =3D ( roundingMode =3D=3D float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment =3D ((int64_t) absZ1 < 0); - break; - case float_round_to_zero: - increment =3D 0; - break; - case float_round_up: - increment =3D !zSign && absZ1; - break; - case float_round_down: - increment =3D zSign && absZ1; - break; - case float_round_to_odd: - increment =3D !(absZ0 & 1) && absZ1; - break; - default: - abort(); - } - if ( increment ) { - ++absZ0; - if ( absZ0 =3D=3D 0 ) goto overflow; - if (!(absZ1 << 1) && roundNearestEven) { - absZ0 &=3D ~1; - } - } - z =3D absZ0; - if ( zSign ) z =3D - z; - if ( z && ( ( z < 0 ) ^ zSign ) ) { - overflow: - float_raise(float_flag_invalid, status); - return zSign ? INT64_MIN : INT64_MAX; - } - if (absZ1) { - float_raise(float_flag_inexact, status); - } - return z; - -} - /*------------------------------------------------------------------------= ---- | Normalizes the subnormal single-precision floating-point value represent= ed | by the denormalized significand `aSig'. The normalized exponent and @@ -5488,179 +5409,6 @@ float64 float64_log2(float64 a, float_status *statu= s) return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the 32-bit two's complement integer format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic---which means in particular that the conversion -| is rounded according to the current rounding mode. If `a' is a NaN, the -| largest positive integer is returned. Otherwise, if the conversion -| overflows, the largest integer with the same sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t floatx80_to_int32(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return 1 << 31; - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - if ( ( aExp =3D=3D 0x7FFF ) && (uint64_t) ( aSig<<1 ) ) aSign =3D 0; - shiftCount =3D 0x4037 - aExp; - if ( shiftCount <=3D 0 ) shiftCount =3D 1; - shift64RightJamming( aSig, shiftCount, &aSig ); - return roundAndPackInt32(aSign, aSig, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the 32-bit two's complement integer format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic, except that the conversion is always rounded -| toward zero. If `a' is a NaN, the largest positive integer is returned. -| Otherwise, if the conversion overflows, the largest integer with the same -| sign as `a' is returned. -*-------------------------------------------------------------------------= ---*/ - -int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig, savedASig; - int32_t z; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return 1 << 31; - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - if ( 0x401E < aExp ) { - if ( ( aExp =3D=3D 0x7FFF ) && (uint64_t) ( aSig<<1 ) ) aSign =3D = 0; - goto invalid; - } - else if ( aExp < 0x3FFF ) { - if (aExp || aSig) { - float_raise(float_flag_inexact, status); - } - return 0; - } - shiftCount =3D 0x403E - aExp; - savedASig =3D aSig; - aSig >>=3D shiftCount; - z =3D aSig; - if ( aSign ) z =3D - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise(float_flag_invalid, status); - return aSign ? (int32_t) 0x80000000 : 0x7FFFFFFF; - } - if ( ( aSig<>( - shiftCount ); - if ( (uint64_t) ( aSig<<( shiftCount & 63 ) ) ) { - float_raise(float_flag_inexact, status); - } - if ( aSign ) z =3D - z; - return z; - -} - /*------------------------------------------------------------------------= ---- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441338; cv=none; d=zohomail.com; s=zohoarc; b=MAfmbEdQ/TQiQomFlRT4m56bnsBbqNIuuLzklnWGXyXFjWOC9egqx+Z20FgDJNqPqUue8WIAkCp7W/3SNccQMDdVNR2Jk9bYSo8sk4R3T6+vwGiPpKkcdNVpnZh39owvA8S9cpseePnz7TGXLD4oXRILC/gis4NpasxF43L/dxY= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 68/72] softfloat: Convert floatx80_scalbn to FloatParts Date: Fri, 7 May 2021 18:47:58 -0700 Message-Id: <20210508014802.892561-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 50 +++++++++++-------------------------------------- 1 file changed, 11 insertions(+), 39 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9f28c5c058..81ff563dc0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3913,6 +3913,17 @@ float128 float128_scalbn(float128 a, int n, float_st= atus *status) return float128_round_pack_canonical(&p, status); } =20 +floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, status)) { + return floatx80_default_nan(status); + } + parts_scalbn(&p, n, status); + return floatx80_round_pack_canonical(&p, status); +} + /* * Square Root */ @@ -5747,45 +5758,6 @@ FloatRelation floatx80_compare_quiet(floatx80 a, flo= atx80 b, return floatx80_compare_internal(a, b, 1, status); } =20 -floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig =3D extractFloatx80Frac( a ); - aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - - if ( aExp =3D=3D 0x7FFF ) { - if ( aSig<<1 ) { - return propagateFloatx80NaN(a, a, status); - } - return a; - } - - if (aExp =3D=3D 0) { - if (aSig =3D=3D 0) { - return a; - } - aExp++; - } - - if (n > 0x10000) { - n =3D 0x10000; - } else if (n < -0x10000) { - n =3D -0x10000; - } - - aExp +=3D n; - return normalizeRoundAndPackFloatx80(status->floatx80_rounding_precisi= on, - aSign, aExp, aSig, 0, status); -} - static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 82 +++++++++++++------------------------------------ 1 file changed, 22 insertions(+), 60 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 81ff563dc0..b89ec4b832 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3864,6 +3864,28 @@ FloatRelation float128_compare_quiet(float128 a, flo= at128 b, float_status *s) return float128_do_compare(a, b, s, true); } =20 +static FloatRelation QEMU_FLATTEN +floatx80_do_compare(floatx80 a, floatx80 b, float_status *s, bool is_quiet) +{ + FloatParts128 pa, pb; + + if (!floatx80_unpack_canonical(&pa, a, s) || + !floatx80_unpack_canonical(&pb, b, s)) { + return float_relation_unordered; + } + return parts_compare(&pa, &pb, s, is_quiet); +} + +FloatRelation floatx80_compare(floatx80 a, floatx80 b, float_status *s) +{ + return floatx80_do_compare(a, b, s, false); +} + +FloatRelation floatx80_compare_quiet(floatx80 a, floatx80 b, float_status = *s) +{ + return floatx80_do_compare(a, b, s, true); +} + /* * Scale by 2**N */ @@ -5698,66 +5720,6 @@ float128 float128_rem(float128 a, float128 b, float_= status *status) return normalizeRoundAndPackFloat128(aSign ^ zSign, bExp - 4, aSig0, a= Sig1, status); } - -static inline FloatRelation -floatx80_compare_internal(floatx80 a, floatx80 b, bool is_quiet, - float_status *status) -{ - bool aSign, bSign; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return float_relation_unordered; - } - if (( ( extractFloatx80Exp( a ) =3D=3D 0x7fff ) && - ( extractFloatx80Frac( a )<<1 ) ) || - ( ( extractFloatx80Exp( b ) =3D=3D 0x7fff ) && - ( extractFloatx80Frac( b )<<1 ) )) { - if (!is_quiet || - floatx80_is_signaling_nan(a, status) || - floatx80_is_signaling_nan(b, status)) { - float_raise(float_flag_invalid, status); - } - return float_relation_unordered; - } - aSign =3D extractFloatx80Sign( a ); - bSign =3D extractFloatx80Sign( b ); - if ( aSign !=3D bSign ) { - - if ( ( ( (uint16_t) ( ( a.high | b.high ) << 1 ) ) =3D=3D 0) && - ( ( a.low | b.low ) =3D=3D 0 ) ) { - /* zero case */ - return float_relation_equal; - } else { - return 1 - (2 * aSign); - } - } else { - /* Normalize pseudo-denormals before comparison. */ - if ((a.high & 0x7fff) =3D=3D 0 && a.low & UINT64_C(0x8000000000000= 000)) { - ++a.high; - } - if ((b.high & 0x7fff) =3D=3D 0 && b.low & UINT64_C(0x8000000000000= 000)) { - ++b.high; - } - if (a.low =3D=3D b.low && a.high =3D=3D b.high) { - return float_relation_equal; - } else { - return 1 - 2 * (aSign ^ ( lt128( a.high, a.low, b.high, b.low = ) )); - } - } -} - -FloatRelation floatx80_compare(floatx80 a, floatx80 b, float_status *statu= s) -{ - return floatx80_compare_internal(a, b, 0, status); -} - -FloatRelation floatx80_compare_quiet(floatx80 a, floatx80 b, - float_status *status) -{ - return floatx80_compare_internal(a, b, 1, status); -} - static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441948; cv=none; d=zohomail.com; s=zohoarc; b=O31GwNGDGAfmi/yt3kqpgZ/2gkpqe5FVKsGB//R5SEy5hfeDmUDTWNizVkghim6PWy3AZ29wm4seUKV4Z7LQJYQoMVHOii+LuDXYeSthLxHLeIT+zCYJYbwJvAjQteeoTLZW/MumTxlM6hQB1u22XSLzAJBJSLv54NUww/ss0ZU= ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 70/72] softfloat: Convert float32_exp2 to FloatParts Date: Fri, 7 May 2021 18:48:00 -0700 Message-Id: <20210508014802.892561-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Keep the intermediate results in FloatParts instead of converting back and forth between float64. Use muladd instead of separate mul+add. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 53 +++++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 30 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b89ec4b832..906bb427ae 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5212,47 +5212,40 @@ static const float64 float32_exp2_coefficients[15] = =3D =20 float32 float32_exp2(float32 a, float_status *status) { - bool aSign; - int aExp; - uint32_t aSig; - float64 r, x, xn; + FloatParts64 xp, xnp, tp, rp; int i; - a =3D float32_squash_input_denormal(a, status); =20 - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - - if ( aExp =3D=3D 0xFF) { - if (aSig) { - return propagateFloat32NaN(a, float32_zero, status); + float32_unpack_canonical(&xp, a, status); + if (unlikely(xp.cls !=3D float_class_normal)) { + switch (xp.cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(&xp, status); + return float32_round_pack_canonical(&xp, status); + case float_class_inf: + return xp.sign ? float32_zero : a; + case float_class_zero: + return float32_one; + default: + break; } - return (aSign) ? float32_zero : a; - } - if (aExp =3D=3D 0) { - if (aSig =3D=3D 0) return float32_one; + g_assert_not_reached(); } =20 float_raise(float_flag_inexact, status); =20 - /* ******************************* */ - /* using float64 for approximation */ - /* ******************************* */ - x =3D float32_to_float64(a, status); - x =3D float64_mul(x, float64_ln2, status); + float64_unpack_canonical(&xnp, float64_ln2, status); + xp =3D *parts_mul(&xp, &tp, status); + xnp =3D xp; =20 - xn =3D x; - r =3D float64_one; + float64_unpack_canonical(&rp, float64_one, status); for (i =3D 0 ; i < 15 ; i++) { - float64 f; - - f =3D float64_mul(xn, float32_exp2_coefficients[i], status); - r =3D float64_add(r, f, status); - - xn =3D float64_mul(xn, x, status); + float64_unpack_canonical(&tp, float32_exp2_coefficients[i], status= ); + rp =3D *parts_muladd(&tp, &xp, &rp, 0, status); + xnp =3D *parts_mul(&xnp, &xp, status); } =20 - return float64_to_float32(r, status); + return float32_round_pack_canonical(&rp, status); } =20 /*------------------------------------------------------------------------= ---- --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620441662; cv=none; d=zohomail.com; s=zohoarc; b=HsX4SxxXaJ3Q7egIXSG25AXl9MP9ZdbdLrEIYKiHSxw/0uXK+TU+lTQzSyQvQvRtvHz67L48f17sDwuMuX/56DyJTS/magWIsJhM4cHUML/SYU/VCWEuTeA+/Ul+kPYdSAWgc7epX1t/HkttbrowNCiKNCxCXKw7Ce0j0kLJqJQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620441662; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HKpES++YzydctcZZ/K52SO5JvpywviZhDsWevoMxn68=; b=nQ85beENOLuH/cd4ZcCM1fOp2RD944UoEICnLKtZ0DKbgeQj3B/LsgmQ3iu9nXD37c 1wykb71krO5ePsguPpJTbqXe3iKYc27GtlTUmT1XOkZPYSX2pu8gDhDcN5svD58RtNii 00v6ICw8ZzvNuV6n2y7W39odeV0T3iUID/bbidFsTmqYtoj8RBv4OI3ZEzECtXohJo/j 0OJjqaKThcQ+NdaKgUlY86HccGmKE2fXfSYJYBtyRzoQNdDk6ReqfkakqWLWIW2vVm64 7mqn64n6+nImF6vZYMoiUy+RXIYKJYvUW5yoIFB6PhAtTeSv5RP9ILysi17/kDSZnCdx HpSQ== X-Gm-Message-State: AOAM531IRjAs9C7pJd+MHUjgegryjFFoYG3SLZOwOolW+qoXnhvq13SC HpztjtFulNYlscXT/HsE95ZniDH7VFDGQg== X-Google-Smtp-Source: ABdhPJw7wBdWh2ZfJoQBeKb+oQqsyqBLz3mgrY2wQGpFHSLPoGt0QzIq/06GAuqcyyKqMVIwvEwJ4Q== X-Received: by 2002:a63:e515:: with SMTP id r21mr13014531pgh.412.1620438709678; Fri, 07 May 2021 18:51:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 71/72] softfloat: Move floatN_log2 to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:48:01 -0700 Message-Id: <20210508014802.892561-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_log2. Though this is partly a ruse, since I do not believe the code will succeed for float128 without work. Which is ok for now, because we do not need this for more than float32 and float64. Since berkeley-testfloat-3 doesn't support log2, compare float64_log2 vs the system log2. Fix the errors for inputs near 1.0: test: 3ff00000000000b0 +0x1.00000000000b0p+0 sf: 3d2fa00000000000 +0x1.fa00000000000p-45 libm: 3d2fbd422b1bd36f +0x1.fbd422b1bd36fp-45 Error in fraction: 32170028290927 ulp test: 3feec24f6770b100 +0x1.ec24f6770b100p-1 sf: bfad3740d13c9ec0 -0x1.d3740d13c9ec0p-5 libm: bfad3740d13c9e98 -0x1.d3740d13c9e98p-5 Error in fraction: 40 ulp Signed-off-by: Richard Henderson --- fpu/softfloat.c | 126 ++++++++------------------------------ tests/fp/fp-test-log2.c | 118 +++++++++++++++++++++++++++++++++++ fpu/softfloat-parts.c.inc | 125 +++++++++++++++++++++++++++++++++++++ tests/fp/meson.build | 11 ++++ 4 files changed, 281 insertions(+), 99 deletions(-) create mode 100644 tests/fp/fp-test-log2.c diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 906bb427ae..3823a7ec6f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -926,6 +926,12 @@ static void parts128_scalbn(FloatParts128 *a, int n, f= loat_status *s); #define parts_scalbn(A, N, S) \ PARTS_GENERIC_64_128(scalbn, A)(A, N, S) =20 +static void parts64_log2(FloatParts64 *a, float_status *s, const FloatFmt = *f); +static void parts128_log2(FloatParts128 *a, float_status *s, const FloatFm= t *f); + +#define parts_log2(A, S, F) \ + PARTS_GENERIC_64_128(log2, A)(A, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -4062,6 +4068,27 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *s) return floatx80_round_pack_canonical(&p, s); } =20 +/* + * log2 + */ +float32 float32_log2(float32 a, float_status *status) +{ + FloatParts64 p; + + float32_unpack_canonical(&p, a, status); + parts_log2(&p, status, &float32_params); + return float32_round_pack_canonical(&p, status); +} + +float64 float64_log2(float64 a, float_status *status) +{ + FloatParts64 p; + + float64_unpack_canonical(&p, a, status); + parts_log2(&p, status, &float64_params); + return float64_round_pack_canonical(&p, status); +} + /*------------------------------------------------------------------------= ---- | The pattern for a default generated NaN. *-------------------------------------------------------------------------= ---*/ @@ -5248,56 +5275,6 @@ float32 float32_exp2(float32 a, float_status *status) return float32_round_pack_canonical(&rp, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the binary log of the single-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ -float32 float32_log2(float32 a, float_status *status) -{ - bool aSign, zSign; - int aExp; - uint32_t aSig, zSig, i; - - a =3D float32_squash_input_denormal(a, status); - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat32( 1, 0xFF, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - if ( aSign ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( aExp =3D=3D 0xFF ) { - if (aSig) { - return propagateFloat32NaN(a, float32_zero, status); - } - return a; - } - - aExp -=3D 0x7F; - aSig |=3D 0x00800000; - zSign =3D aExp < 0; - zSig =3D aExp << 23; - - for (i =3D 1 << 22; i > 0; i >>=3D 1) { - aSig =3D ( (uint64_t)aSig * aSig ) >> 23; - if ( aSig & 0x01000000 ) { - aSig >>=3D 1; - zSig |=3D i; - } - } - - if ( zSign ) - zSig =3D -zSig; - - return normalizeRoundAndPackFloat32(zSign, 0x85, zSig, status); -} - /*------------------------------------------------------------------------= ---- | Returns the remainder of the double-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5386,55 +5363,6 @@ float64 float64_rem(float64 a, float64 b, float_stat= us *status) =20 } =20 -/*------------------------------------------------------------------------= ---- -| Returns the binary log of the double-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ -float64 float64_log2(float64 a, float_status *status) -{ - bool aSign, zSign; - int aExp; - uint64_t aSig, aSig0, aSig1, zSig, i; - a =3D float64_squash_input_denormal(a, status); - - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return packFloat64( 1, 0x7FF, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - if ( aSign ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( aExp =3D=3D 0x7FF ) { - if (aSig) { - return propagateFloat64NaN(a, float64_zero, status); - } - return a; - } - - aExp -=3D 0x3FF; - aSig |=3D UINT64_C(0x0010000000000000); - zSign =3D aExp < 0; - zSig =3D (uint64_t)aExp << 52; - for (i =3D 1LL << 51; i > 0; i >>=3D 1) { - mul64To128( aSig, aSig, &aSig0, &aSig1 ); - aSig =3D ( aSig0 << 12 ) | ( aSig1 >> 52 ); - if ( aSig & UINT64_C(0x0020000000000000) ) { - aSig >>=3D 1; - zSig |=3D i; - } - } - - if ( zSign ) - zSig =3D -zSig; - return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status); -} - /*------------------------------------------------------------------------= ---- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c new file mode 100644 index 0000000000..8ad856509b --- /dev/null +++ b/tests/fp/fp-test-log2.c @@ -0,0 +1,118 @@ +/* + * fp-test-log2.c - test QEMU's softfloat log2 + * + * Copyright (C) 2020, Linaro, Ltd. + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef HW_POISON_H +#error Must define HW_POISON_H to work around TARGET_* poisoning +#endif + +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include +#include "fpu/softfloat.h" + +typedef union { + double d; + float64 i; +} ufloat64; + +static int errors; + +static void compare(ufloat64 test, ufloat64 real, ufloat64 soft, bool exac= t) +{ + int msb; + uint64_t ulp =3D UINT64_MAX; + + if (real.i =3D=3D soft.i) { + return; + } + msb =3D 63 - __builtin_clzll(real.i ^ soft.i); + + if (msb < 52) { + if (real.i > soft.i) { + ulp =3D real.i - soft.i; + } else { + ulp =3D soft.i - real.i; + } + } + + /* glibc allows 3 ulp error in its libm-test-ulps; allow 4 here */ + if (!exact && ulp <=3D 4) { + return; + } + =20 + printf("test: %016" PRIx64 " %+.13a\n" + " sf: %016" PRIx64 " %+.13a\n" + "libm: %016" PRIx64 " %+.13a\n", + test.i, test.d, soft.i, soft.d, real.i, real.d); + + if (msb =3D=3D 63) { + printf("Error in sign!\n\n"); + } else if (msb >=3D 52) { + printf("Error in exponent: %d\n\n", + (int)(soft.i >> 52) - (int)(real.i >> 52)); + } else { + printf("Error in fraction: %" PRIu64 " ulp\n\n", ulp); + } + + if (++errors =3D=3D 20) { + exit(1); + } +} + +int main(int ac, char **av) +{ + ufloat64 test, real, soft; + float_status qsf =3D {0}; + int i; + + set_float_rounding_mode(float_round_nearest_even, &qsf); + + test.d =3D 0.0; + real.d =3D -__builtin_inf(); + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d =3D 1.0; + real.d =3D 0.0; + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d =3D 2.0; + real.d =3D 1.0; + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d =3D 4.0; + real.d =3D 2.0; + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d =3D 0x1p64; + real.d =3D 64.0; + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d =3D __builtin_inf(); + real.d =3D __builtin_inf(); + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + for (i =3D 0; i < 10000; ++i) { + test.d =3D drand48() + 1.0; /* [1.0, 2.0) */ + real.d =3D log2(test.d); + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, false); + + test.d =3D drand48() * 100; /* [0.0, 100) */ + real.d =3D log2(test.d); + soft.i =3D float64_log2(test.i, &qsf); + compare(test, real, soft, false); + } + + return 0; +} diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index c18f77f2cf..3659c6a4c0 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1319,3 +1319,128 @@ static void partsN(scalbn)(FloatPartsN *a, int n, f= loat_status *s) g_assert_not_reached(); } } + +/* + * Return log2(A) + */ +static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *= fmt) +{ + uint64_t a0, a1, r, t, ign; + FloatPartsN f; + int i, n, a_exp, f_exp; + + if (unlikely(a->cls !=3D float_class_normal)) { + switch (a->cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(a, s); + return; + case float_class_zero: + /* log2(0) =3D -inf */ + a->cls =3D float_class_inf; + a->sign =3D 1; + return; + case float_class_inf: + if (unlikely(a->sign)) { + goto d_nan; + } + return; + default: + break; + } + g_assert_not_reached(); + } + if (unlikely(a->sign)) { + goto d_nan; + } + + /* TODO: This algorithm looses bits too quickly for float128. */ + g_assert(N =3D=3D 64); + + a_exp =3D a->exp; + f_exp =3D -1; + + r =3D 0; + t =3D DECOMPOSED_IMPLICIT_BIT; + a0 =3D a->frac_hi; + a1 =3D 0; + + n =3D fmt->frac_size + 2; + if (unlikely(a_exp =3D=3D -1)) { + /* + * When a_exp =3D=3D -1, we're computing the log2 of a value [0.5,= 1.0). + * When the value is very close to 1.0, there are lots of 1's in + * the msb parts of the fraction. At the end, when we subtract + * this value from -1.0, we can see a catastrophic loss of precisi= on, + * as 0x800..000 - 0x7ff..ffx becomes 0x000..00y, leaving only the + * bits of y in the final result. To minimize this, compute as ma= ny + * digits as we can. + * ??? This case needs another algorithm to avoid this. + */ + n =3D fmt->frac_size * 2 + 2; + /* Don't compute a value overlapping the sticky bit */ + n =3D MIN(n, 62); + } + + for (i =3D 0; i < n; i++) { + if (a1) { + mul128To256(a0, a1, a0, a1, &a0, &a1, &ign, &ign); + } else if (a0 & 0xffffffffull) { + mul64To128(a0, a0, &a0, &a1); + } else if (a0 & ~DECOMPOSED_IMPLICIT_BIT) { + a0 >>=3D 32; + a0 *=3D a0; + } else { + goto exact; + } + + if (a0 & DECOMPOSED_IMPLICIT_BIT) { + if (unlikely(a_exp =3D=3D 0 && r =3D=3D 0)) { + /* + * When a_exp =3D=3D 0, we're computing the log2 of a value + * [1.0,2.0). When the value is very close to 1.0, there + * are lots of 0's in the msb parts of the fraction. + * We need to compute more digits to produce a correct + * result -- restart at the top of the fraction. + * ??? This is likely to lose precision quickly, as for + * float128; we may need another method. + */ + f_exp -=3D i; + t =3D r =3D DECOMPOSED_IMPLICIT_BIT; + i =3D 0; + } else { + r |=3D t; + } + } else { + add128(a0, a1, a0, a1, &a0, &a1); + } + t >>=3D 1; + } + + /* Set sticky for inexact. */ + r |=3D (a1 || a0 & ~DECOMPOSED_IMPLICIT_BIT); + + exact: + parts_sint_to_float(a, a_exp, 0, s); + if (r =3D=3D 0) { + return; + } + + memset(&f, 0, sizeof(f)); + f.cls =3D float_class_normal; + f.frac_hi =3D r; + f.exp =3D f_exp - frac_normalize(&f); + + if (a_exp < 0) { + parts_sub_normal(a, &f); + } else if (a_exp > 0) { + parts_add_normal(a, &f); + } else { + *a =3D f; + } + return; + + d_nan: + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); +} diff --git a/tests/fp/meson.build b/tests/fp/meson.build index 1c3eee9955..9218bfd3b0 100644 --- a/tests/fp/meson.build +++ b/tests/fp/meson.build @@ -634,3 +634,14 @@ fpbench =3D executable( include_directories: [sfinc, include_directories(tfdir)], c_args: fpcflags, ) + +fptestlog2 =3D executable( + 'fp-test-log2', + ['fp-test-log2.c', '../../fpu/softfloat.c'], + link_with: [libsoftfloat], + dependencies: [qemuutil], + include_directories: [sfinc], + c_args: fpcflags, +) +test('fp-test-log2', fptestlog2, + suite: ['softfloat', 'softfloat-ops']) --=20 2.25.1 From nobody Fri Apr 19 13:53:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename to parts$N_modrem. This was the last use of a lot of the legacy infrastructure, so remove it as required. Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 34 + fpu/softfloat.c | 1339 +++++++------------------------- fpu/softfloat-parts.c.inc | 34 + fpu/softfloat-specialize.c.inc | 165 ---- 4 files changed, 329 insertions(+), 1243 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index ec4e27a595..81c3fe8256 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -745,4 +745,38 @@ static inline bool ne128(uint64_t a0, uint64_t a1, uin= t64_t b0, uint64_t b1) return a0 !=3D b0 || a1 !=3D b1; } =20 +/* + * Similarly, comparisons of 192-bit values. + */ + +static inline bool eq192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2) +{ + return ((a0 ^ b0) | (a1 ^ b1) | (a2 ^ b2)) =3D=3D 0; +} + +static inline bool le192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2) +{ + if (a0 !=3D b0) { + return a0 < b0; + } + if (a1 !=3D b1) { + return a1 < b1; + } + return a2 <=3D b2; +} + +static inline bool lt192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2) +{ + if (a0 !=3D b0) { + return a0 < b0; + } + if (a1 !=3D b1) { + return a1 < b1; + } + return a2 < b2; +} + #endif diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3823a7ec6f..7376b3470c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -401,60 +401,6 @@ float64_gen2(float64 xa, float64 xb, float_status *s, return soft(ua.s, ub.s, s); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the fraction bits of the single-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline uint32_t extractFloat32Frac(float32 a) -{ - return float32_val(a) & 0x007FFFFF; -} - -/*------------------------------------------------------------------------= ---- -| Returns the exponent bits of the single-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline int extractFloat32Exp(float32 a) -{ - return (float32_val(a) >> 23) & 0xFF; -} - -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the single-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline bool extractFloat32Sign(float32 a) -{ - return float32_val(a) >> 31; -} - -/*------------------------------------------------------------------------= ---- -| Returns the fraction bits of the double-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline uint64_t extractFloat64Frac(float64 a) -{ - return float64_val(a) & UINT64_C(0x000FFFFFFFFFFFFF); -} - -/*------------------------------------------------------------------------= ---- -| Returns the exponent bits of the double-precision floating-point value `= a'. -*-------------------------------------------------------------------------= ---*/ - -static inline int extractFloat64Exp(float64 a) -{ - return (float64_val(a) >> 52) & 0x7FF; -} - -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the double-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline bool extractFloat64Sign(float64 a) -{ - return float64_val(a) >> 63; -} - /* * Classify a floating point number. Everything above float_class_qnan * is a NaN so cls >=3D float_class_qnan is any NaN. @@ -844,6 +790,14 @@ static FloatParts128 *parts128_div(FloatParts128 *a, F= loatParts128 *b, #define parts_div(A, B, S) \ PARTS_GENERIC_64_128(div, A)(A, B, S) =20 +static FloatParts64 *parts64_modrem(FloatParts64 *a, FloatParts64 *b, + uint64_t *mod_quot, float_status *s); +static FloatParts128 *parts128_modrem(FloatParts128 *a, FloatParts128 *b, + uint64_t *mod_quot, float_status *s); + +#define parts_modrem(A, B, Q, S) \ + PARTS_GENERIC_64_128(modrem, A)(A, B, Q, S) + static void parts64_sqrt(FloatParts64 *a, float_status *s, const FloatFmt = *f); static void parts128_sqrt(FloatParts128 *a, float_status *s, const FloatFm= t *f); =20 @@ -1228,6 +1182,186 @@ static int frac256_normalize(FloatParts256 *a) =20 #define frac_normalize(A) FRAC_GENERIC_64_128_256(normalize, A)(A) =20 +static void frac64_modrem(FloatParts64 *a, FloatParts64 *b, uint64_t *mod_= quot) +{ + uint64_t a0, a1, b0, t0, t1, q, quot; + int exp_diff =3D a->exp - b->exp; + int shift; + + a0 =3D a->frac; + a1 =3D 0; + + if (exp_diff < -1) { + if (mod_quot) { + *mod_quot =3D 0; + } + return; + } + if (exp_diff =3D=3D -1) { + a0 >>=3D 1; + exp_diff =3D 0; + } + + b0 =3D b->frac; + quot =3D q =3D b0 <=3D a0; + if (q) { + a0 -=3D b0; + } + + exp_diff -=3D 64; + while (exp_diff > 0) { + q =3D estimateDiv128To64(a0, a1, b0); + q =3D q > 2 ? q - 2 : 0; + mul64To128(b0, q, &t0, &t1); + sub128(a0, a1, t0, t1, &a0, &a1); + shortShift128Left(a0, a1, 62, &a0, &a1); + exp_diff -=3D 62; + quot =3D (quot << 62) + q; + } + + exp_diff +=3D 64; + if (exp_diff > 0) { + q =3D estimateDiv128To64(a0, a1, b0); + q =3D q > 2 ? (q - 2) >> (64 - exp_diff) : 0; + mul64To128(b0, q << (64 - exp_diff), &t0, &t1); + sub128(a0, a1, t0, t1, &a0, &a1); + shortShift128Left(0, b0, 64 - exp_diff, &t0, &t1); + while (le128(t0, t1, a0, a1)) { + ++q; + sub128(a0, a1, t0, t1, &a0, &a1); + } + quot =3D (exp_diff < 64 ? quot << exp_diff : 0) + q; + } else { + t0 =3D b0; + t1 =3D 0; + } + + if (mod_quot) { + *mod_quot =3D quot; + } else { + sub128(t0, t1, a0, a1, &t0, &t1); + if (lt128(t0, t1, a0, a1) || + (eq128(t0, t1, a0, a1) && (q & 1))) { + a0 =3D t0; + a1 =3D t1; + a->sign =3D !a->sign; + } + } + + if (likely(a0)) { + shift =3D clz64(a0); + shortShift128Left(a0, a1, shift, &a0, &a1); + } else if (likely(a1)) { + shift =3D clz64(a1); + a0 =3D a1 << shift; + a1 =3D 0; + shift +=3D 64; + } else { + a->cls =3D float_class_zero; + return; + } + + a->exp =3D b->exp + exp_diff - shift; + a->frac =3D a0 | (a1 !=3D 0); +} + +static void frac128_modrem(FloatParts128 *a, FloatParts128 *b, + uint64_t *mod_quot) +{ + uint64_t a0, a1, a2, b0, b1, t0, t1, t2, q, quot; + int exp_diff =3D a->exp - b->exp; + int shift; + + a0 =3D a->frac_hi; + a1 =3D a->frac_lo; + a2 =3D 0; + + if (exp_diff < -1) { + if (mod_quot) { + *mod_quot =3D 0; + } + return; + } + if (exp_diff =3D=3D -1) { + shift128Right(a0, a1, 1, &a0, &a1); + exp_diff =3D 0; + } + + b0 =3D b->frac_hi; + b1 =3D b->frac_lo; + + quot =3D q =3D le128(b0, b1, a0, a1); + if (q) { + sub128(a0, a1, b0, b1, &a0, &a1); + } + + exp_diff -=3D 64; + while (exp_diff > 0) { + q =3D estimateDiv128To64(a0, a1, b0); + q =3D q > 4 ? q - 4 : 0; + mul128By64To192(b0, b1, q, &t0, &t1, &t2); + sub192(a0, a1, a2, t0, t1, t2, &a0, &a1, &a2); + shortShift192Left(a0, a1, a2, 61, &a0, &a1, &a2); + exp_diff -=3D 61; + quot =3D (quot << 61) + q; + } + + exp_diff +=3D 64; + if (exp_diff > 0) { + q =3D estimateDiv128To64(a0, a1, b0); + q =3D q > 4 ? (q - 4) >> (64 - exp_diff) : 0; + mul128By64To192(b0, b1, q << (64 - exp_diff), &t0, &t1, &t2); + sub192(a0, a1, a2, t0, t1, t2, &a0, &a1, &a2); + shortShift192Left(0, b0, b1, 64 - exp_diff, &t0, &t1, &t2); + while (le192(t0, t1, t2, a0, a1, a2)) { + ++q; + sub192(a0, a1, a2, t0, t1, t2, &a0, &a1, &a2); + } + quot =3D (exp_diff < 64 ? quot << exp_diff : 0) + q; + } else { + t0 =3D b0; + t1 =3D b1; + t2 =3D 0; + } + + if (mod_quot) { + *mod_quot =3D quot; + } else { + sub192(t0, t1, t2, a0, a1, a2, &t0, &t1, &t2); + if (lt192(t0, t1, t2, a0, a1, a2) || + (eq192(t0, t1, t2, a0, a1, a2) && (q & 1))) { + a0 =3D t0; + a1 =3D t1; + a2 =3D t2; + a->sign =3D !a->sign; + } + } + + if (likely(a0)) { + shift =3D clz64(a0); + shortShift192Left(a0, a1, a2, shift, &a0, &a1, &a2); + } else if (likely(a1)) { + shift =3D clz64(a1); + shortShift128Left(a1, a2, shift, &a0, &a1); + a2 =3D 0; + shift +=3D 64; + } else if (likely(a2)) { + shift =3D clz64(a2); + a0 =3D a2 << shift; + a1 =3D a2 =3D 0; + shift +=3D 128; + } else { + a->cls =3D float_class_zero; + return; + } + + a->exp =3D b->exp + exp_diff - shift; + a->frac_hi =3D a0; + a->frac_lo =3D a1 | (a2 !=3D 0); +} + +#define frac_modrem(A, B, Q) FRAC_GENERIC_64_128(modrem, A)(A, B, Q) + static void frac64_shl(FloatParts64 *a, int c) { a->frac <<=3D c; @@ -2312,6 +2446,79 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_= status *status) return floatx80_round_pack_canonical(pr, status); } =20 +/* + * Remainder + */ + +float32 float32_rem(float32 a, float32 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr =3D parts_modrem(&pa, &pb, NULL, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 float64_rem(float64 a, float64 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr =3D parts_modrem(&pa, &pb, NULL, status); + + return float64_round_pack_canonical(pr, status); +} + +float128 float128_rem(float128 a, float128 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr =3D parts_modrem(&pa, &pb, NULL, status); + + return float128_round_pack_canonical(pr, status); +} + +/* + * Returns the remainder of the extended double-precision floating-point v= alue + * `a' with respect to the corresponding value `b'. + * If 'mod' is false, the operation is performed according to the IEC/IEEE + * Standard for Binary Floating-Point Arithmetic. If 'mod' is true, return + * the remainder based on truncating the quotient toward zero instead and + * *quotient is set to the low 64 bits of the absolute value of the integer + * quotient. + */ +floatx80 floatx80_modrem(floatx80 a, floatx80 b, bool mod, + uint64_t *quotient, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + *quotient =3D 0; + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + pr =3D parts_modrem(&pa, &pb, mod ? quotient : NULL, status); + + return floatx80_round_pack_canonical(pr, status); +} + +floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status) +{ + uint64_t quotient; + return floatx80_modrem(a, b, false, "ient, status); +} + +floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) +{ + uint64_t quotient; + return floatx80_modrem(a, b, true, "ient, status); +} + /* * Float to Float conversions * @@ -4264,300 +4471,6 @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a,= float_status *status) return a; } =20 -/*------------------------------------------------------------------------= ---- -| Normalizes the subnormal single-precision floating-point value represent= ed -| by the denormalized significand `aSig'. The normalized exponent and -| significand are stored at the locations pointed to by `zExpPtr' and -| `zSigPtr', respectively. -*-------------------------------------------------------------------------= ---*/ - -static void - normalizeFloat32Subnormal(uint32_t aSig, int *zExpPtr, uint32_t *zSigPtr) -{ - int8_t shiftCount; - - shiftCount =3D clz32(aSig) - 8; - *zSigPtr =3D aSig<float_rounding_mode; - roundNearestEven =3D ( roundingMode =3D=3D float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - roundIncrement =3D 0x40; - break; - case float_round_to_zero: - roundIncrement =3D 0; - break; - case float_round_up: - roundIncrement =3D zSign ? 0 : 0x7f; - break; - case float_round_down: - roundIncrement =3D zSign ? 0x7f : 0; - break; - case float_round_to_odd: - roundIncrement =3D zSig & 0x80 ? 0 : 0x7f; - break; - default: - abort(); - break; - } - roundBits =3D zSig & 0x7F; - if ( 0xFD <=3D (uint16_t) zExp ) { - if ( ( 0xFD < zExp ) - || ( ( zExp =3D=3D 0xFD ) - && ( (int32_t) ( zSig + roundIncrement ) < 0 ) ) - ) { - bool overflow_to_inf =3D roundingMode !=3D float_round_to_odd = && - roundIncrement !=3D 0; - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat32(zSign, 0xFF, -!overflow_to_inf); - } - if ( zExp < 0 ) { - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat32(zSign, 0, 0); - } - isTiny =3D status->tininess_before_rounding - || (zExp < -1) - || (zSig + roundIncrement < 0x80000000); - shift32RightJamming( zSig, - zExp, &zSig ); - zExp =3D 0; - roundBits =3D zSig & 0x7F; - if (isTiny && roundBits) { - float_raise(float_flag_underflow, status); - } - if (roundingMode =3D=3D float_round_to_odd) { - /* - * For round-to-odd case, the roundIncrement depends on - * zSig which just changed. - */ - roundIncrement =3D zSig & 0x80 ? 0 : 0x7f; - } - } - } - if (roundBits) { - float_raise(float_flag_inexact, status); - } - zSig =3D ( zSig + roundIncrement )>>7; - if (!(roundBits ^ 0x40) && roundNearestEven) { - zSig &=3D ~1; - } - if ( zSig =3D=3D 0 ) zExp =3D 0; - return packFloat32( zSign, zExp, zSig ); - -} - -/*------------------------------------------------------------------------= ---- -| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', -| and significand `zSig', and returns the proper single-precision floating- -| point value corresponding to the abstract input. This routine is just l= ike -| `roundAndPackFloat32' except that `zSig' does not have to be normalized. -| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true= '' -| floating-point exponent. -*-------------------------------------------------------------------------= ---*/ - -static float32 - normalizeRoundAndPackFloat32(bool zSign, int zExp, uint32_t zSig, - float_status *status) -{ - int8_t shiftCount; - - shiftCount =3D clz32(zSig) - 1; - return roundAndPackFloat32(zSign, zExp - shiftCount, zSig<float_rounding_mode; - roundNearestEven =3D ( roundingMode =3D=3D float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - roundIncrement =3D 0x200; - break; - case float_round_to_zero: - roundIncrement =3D 0; - break; - case float_round_up: - roundIncrement =3D zSign ? 0 : 0x3ff; - break; - case float_round_down: - roundIncrement =3D zSign ? 0x3ff : 0; - break; - case float_round_to_odd: - roundIncrement =3D (zSig & 0x400) ? 0 : 0x3ff; - break; - default: - abort(); - } - roundBits =3D zSig & 0x3FF; - if ( 0x7FD <=3D (uint16_t) zExp ) { - if ( ( 0x7FD < zExp ) - || ( ( zExp =3D=3D 0x7FD ) - && ( (int64_t) ( zSig + roundIncrement ) < 0 ) ) - ) { - bool overflow_to_inf =3D roundingMode !=3D float_round_to_odd = && - roundIncrement !=3D 0; - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat64(zSign, 0x7FF, -(!overflow_to_inf)); - } - if ( zExp < 0 ) { - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat64(zSign, 0, 0); - } - isTiny =3D status->tininess_before_rounding - || (zExp < -1) - || (zSig + roundIncrement < UINT64_C(0x8000000000000000)= ); - shift64RightJamming( zSig, - zExp, &zSig ); - zExp =3D 0; - roundBits =3D zSig & 0x3FF; - if (isTiny && roundBits) { - float_raise(float_flag_underflow, status); - } - if (roundingMode =3D=3D float_round_to_odd) { - /* - * For round-to-odd case, the roundIncrement depends on - * zSig which just changed. - */ - roundIncrement =3D (zSig & 0x400) ? 0 : 0x3ff; - } - } - } - if (roundBits) { - float_raise(float_flag_inexact, status); - } - zSig =3D ( zSig + roundIncrement )>>10; - if (!(roundBits ^ 0x200) && roundNearestEven) { - zSig &=3D ~1; - } - if ( zSig =3D=3D 0 ) zExp =3D 0; - return packFloat64( zSign, zExp, zSig ); - -} - -/*------------------------------------------------------------------------= ---- -| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', -| and significand `zSig', and returns the proper double-precision floating- -| point value corresponding to the abstract input. This routine is just l= ike -| `roundAndPackFloat64' except that `zSig' does not have to be normalized. -| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true= '' -| floating-point exponent. -*-------------------------------------------------------------------------= ---*/ - -static float64 - normalizeRoundAndPackFloat64(bool zSign, int zExp, uint64_t zSig, - float_status *status) -{ - int8_t shiftCount; - - shiftCount =3D clz64(zSig) - 1; - return roundAndPackFloat64(zSign, zExp - shiftCount, zSig<>48 ) & 0x7FFF; - -} - -/*------------------------------------------------------------------------= ---- -| Returns the sign bit of the quadruple-precision floating-point value `a'. -*-------------------------------------------------------------------------= ---*/ - -static inline bool extractFloat128Sign(float128 a) -{ - return a.high >> 63; -} - -/*------------------------------------------------------------------------= ---- -| Normalizes the subnormal quadruple-precision floating-point value -| represented by the denormalized significand formed by the concatenation = of -| `aSig0' and `aSig1'. The normalized exponent is stored at the location -| pointed to by `zExpPtr'. The most significant 49 bits of the normalized -| significand are stored at the location pointed to by `zSig0Ptr', and the -| least significant 64 bits of the normalized significand are stored at the -| location pointed to by `zSig1Ptr'. -*-------------------------------------------------------------------------= ---*/ - -static void - normalizeFloat128Subnormal( - uint64_t aSig0, - uint64_t aSig1, - int32_t *zExpPtr, - uint64_t *zSig0Ptr, - uint64_t *zSig1Ptr - ) -{ - int8_t shiftCount; - - if ( aSig0 =3D=3D 0 ) { - shiftCount =3D clz64(aSig1) - 15; - if ( shiftCount < 0 ) { - *zSig0Ptr =3D aSig1>>( - shiftCount ); - *zSig1Ptr =3D aSig1<<( shiftCount & 63 ); - } - else { - *zSig0Ptr =3D aSig1<float_rounding_mode; - roundNearestEven =3D ( roundingMode =3D=3D float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment =3D ((int64_t)zSig2 < 0); - break; - case float_round_to_zero: - increment =3D 0; - break; - case float_round_up: - increment =3D !zSign && zSig2; - break; - case float_round_down: - increment =3D zSign && zSig2; - break; - case float_round_to_odd: - increment =3D !(zSig1 & 0x1) && zSig2; - break; - default: - abort(); - } - if ( 0x7FFD <=3D (uint32_t) zExp ) { - if ( ( 0x7FFD < zExp ) - || ( ( zExp =3D=3D 0x7FFD ) - && eq128( - UINT64_C(0x0001FFFFFFFFFFFF), - UINT64_C(0xFFFFFFFFFFFFFFFF), - zSig0, - zSig1 - ) - && increment - ) - ) { - float_raise(float_flag_overflow | float_flag_inexact, status); - if ( ( roundingMode =3D=3D float_round_to_zero ) - || ( zSign && ( roundingMode =3D=3D float_round_up ) ) - || ( ! zSign && ( roundingMode =3D=3D float_round_down ) ) - || (roundingMode =3D=3D float_round_to_odd) - ) { - return - packFloat128( - zSign, - 0x7FFE, - UINT64_C(0x0000FFFFFFFFFFFF), - UINT64_C(0xFFFFFFFFFFFFFFFF) - ); - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( zExp < 0 ) { - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat128(zSign, 0, 0, 0); - } - isTiny =3D status->tininess_before_rounding - || (zExp < -1) - || !increment - || lt128(zSig0, zSig1, - UINT64_C(0x0001FFFFFFFFFFFF), - UINT64_C(0xFFFFFFFFFFFFFFFF)); - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 ); - zExp =3D 0; - if (isTiny && zSig2) { - float_raise(float_flag_underflow, status); - } - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment =3D ((int64_t)zSig2 < 0); - break; - case float_round_to_zero: - increment =3D 0; - break; - case float_round_up: - increment =3D !zSign && zSig2; - break; - case float_round_down: - increment =3D zSign && zSig2; - break; - case float_round_to_odd: - increment =3D !(zSig1 & 0x1) && zSig2; - break; - default: - abort(); - } - } - } - if (zSig2) { - float_raise(float_flag_inexact, status); - } - if ( increment ) { - add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 ); - if ((zSig2 + zSig2 =3D=3D 0) && roundNearestEven) { - zSig1 &=3D ~1; - } - } - else { - if ( ( zSig0 | zSig1 ) =3D=3D 0 ) zExp =3D 0; - } - return packFloat128( zSign, zExp, zSig0, zSig1 ); - -} - -/*------------------------------------------------------------------------= ---- -| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', -| and significand formed by the concatenation of `zSig0' and `zSig1', and -| returns the proper quadruple-precision floating-point value corresponding -| to the abstract input. This routine is just like `roundAndPackFloat128' -| except that the input significand has fewer bits and does not have to be -| normalized. In all cases, `zExp' must be 1 less than the ``true'' float= ing- -| point exponent. -*-------------------------------------------------------------------------= ---*/ - -static float128 normalizeRoundAndPackFloat128(bool zSign, int32_t zExp, - uint64_t zSig0, uint64_t zSi= g1, - float_status *status) -{ - int8_t shiftCount; - uint64_t zSig2; - - if ( zSig0 =3D=3D 0 ) { - zSig0 =3D zSig1; - zSig1 =3D 0; - zExp -=3D 64; - } - shiftCount =3D clz64(zSig0) - 15; - if ( 0 <=3D shiftCount ) { - zSig2 =3D 0; - shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 ); - } - else { - shift128ExtraRightJamming( - zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 ); - } - zExp -=3D shiftCount; - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the remainder of the single-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float32 float32_rem(float32 a, float32 b, float_status *status) -{ - bool aSign, zSign; - int aExp, bExp, expDiff; - uint32_t aSig, bSig; - uint32_t q; - uint64_t aSig64, bSig64, q64; - uint32_t alternateASig; - int32_t sigMean; - a =3D float32_squash_input_denormal(a, status); - b =3D float32_squash_input_denormal(b, status); - - aSig =3D extractFloat32Frac( a ); - aExp =3D extractFloat32Exp( a ); - aSign =3D extractFloat32Sign( a ); - bSig =3D extractFloat32Frac( b ); - bExp =3D extractFloat32Exp( b ); - if ( aExp =3D=3D 0xFF ) { - if ( aSig || ( ( bExp =3D=3D 0xFF ) && bSig ) ) { - return propagateFloat32NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( bExp =3D=3D 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return a; - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - expDiff =3D aExp - bExp; - aSig |=3D 0x00800000; - bSig |=3D 0x00800000; - if ( expDiff < 32 ) { - aSig <<=3D 8; - bSig <<=3D 8; - if ( expDiff < 0 ) { - if ( expDiff < -1 ) return a; - aSig >>=3D 1; - } - q =3D ( bSig <=3D aSig ); - if ( q ) aSig -=3D bSig; - if ( 0 < expDiff ) { - q =3D ( ( (uint64_t) aSig )<<32 ) / bSig; - q >>=3D 32 - expDiff; - bSig >>=3D 2; - aSig =3D ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; - } - else { - aSig >>=3D 2; - bSig >>=3D 2; - } - } - else { - if ( bSig <=3D aSig ) aSig -=3D bSig; - aSig64 =3D ( (uint64_t) aSig )<<40; - bSig64 =3D ( (uint64_t) bSig )<<40; - expDiff -=3D 64; - while ( 0 < expDiff ) { - q64 =3D estimateDiv128To64( aSig64, 0, bSig64 ); - q64 =3D ( 2 < q64 ) ? q64 - 2 : 0; - aSig64 =3D - ( ( bSig * q64 )<<38 ); - expDiff -=3D 62; - } - expDiff +=3D 64; - q64 =3D estimateDiv128To64( aSig64, 0, bSig64 ); - q64 =3D ( 2 < q64 ) ? q64 - 2 : 0; - q =3D q64>>( 64 - expDiff ); - bSig <<=3D 6; - aSig =3D ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q; - } - do { - alternateASig =3D aSig; - ++q; - aSig -=3D bSig; - } while ( 0 <=3D (int32_t) aSig ); - sigMean =3D aSig + alternateASig; - if ( ( sigMean < 0 ) || ( ( sigMean =3D=3D 0 ) && ( q & 1 ) ) ) { - aSig =3D alternateASig; - } - zSign =3D ( (int32_t) aSig < 0 ); - if ( zSign ) aSig =3D - aSig; - return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status); -} - - - /*------------------------------------------------------------------------= ---- | Returns the binary exponential of the single-precision floating-point va= lue | `a'. The operation is performed according to the IEC/IEEE Standard for @@ -5275,94 +4806,6 @@ float32 float32_exp2(float32 a, float_status *status) return float32_round_pack_canonical(&rp, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the remainder of the double-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float64 float64_rem(float64 a, float64 b, float_status *status) -{ - bool aSign, zSign; - int aExp, bExp, expDiff; - uint64_t aSig, bSig; - uint64_t q, alternateASig; - int64_t sigMean; - - a =3D float64_squash_input_denormal(a, status); - b =3D float64_squash_input_denormal(b, status); - aSig =3D extractFloat64Frac( a ); - aExp =3D extractFloat64Exp( a ); - aSign =3D extractFloat64Sign( a ); - bSig =3D extractFloat64Frac( b ); - bExp =3D extractFloat64Exp( b ); - if ( aExp =3D=3D 0x7FF ) { - if ( aSig || ( ( bExp =3D=3D 0x7FF ) && bSig ) ) { - return propagateFloat64NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( bExp =3D=3D 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig =3D=3D 0 ) return a; - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - expDiff =3D aExp - bExp; - aSig =3D (aSig | UINT64_C(0x0010000000000000)) << 11; - bSig =3D (bSig | UINT64_C(0x0010000000000000)) << 11; - if ( expDiff < 0 ) { - if ( expDiff < -1 ) return a; - aSig >>=3D 1; - } - q =3D ( bSig <=3D aSig ); - if ( q ) aSig -=3D bSig; - expDiff -=3D 64; - while ( 0 < expDiff ) { - q =3D estimateDiv128To64( aSig, 0, bSig ); - q =3D ( 2 < q ) ? q - 2 : 0; - aSig =3D - ( ( bSig>>2 ) * q ); - expDiff -=3D 62; - } - expDiff +=3D 64; - if ( 0 < expDiff ) { - q =3D estimateDiv128To64( aSig, 0, bSig ); - q =3D ( 2 < q ) ? q - 2 : 0; - q >>=3D 64 - expDiff; - bSig >>=3D 2; - aSig =3D ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; - } - else { - aSig >>=3D 2; - bSig >>=3D 2; - } - do { - alternateASig =3D aSig; - ++q; - aSig -=3D bSig; - } while ( 0 <=3D (int64_t) aSig ); - sigMean =3D aSig + alternateASig; - if ( ( sigMean < 0 ) || ( ( sigMean =3D=3D 0 ) && ( q & 1 ) ) ) { - aSig =3D alternateASig; - } - zSign =3D ( (int64_t) aSig < 0 ); - if ( zSign ) aSig =3D - aSig; - return normalizeRoundAndPackFloat64(aSign ^ zSign, bExp, aSig, status); - -} - /*------------------------------------------------------------------------= ---- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the @@ -5381,266 +4824,6 @@ floatx80 floatx80_round(floatx80 a, float_status *s= tatus) return floatx80_round_pack_canonical(&p, status); } =20 -/*------------------------------------------------------------------------= ---- -| Returns the remainder of the extended double-precision floating-point va= lue -| `a' with respect to the corresponding value `b'. The operation is perfo= rmed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic, -| if 'mod' is false; if 'mod' is true, return the remainder based on trunc= ating -| the quotient toward zero instead. '*quotient' is set to the low 64 bits= of -| the absolute value of the integer quotient. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_modrem(floatx80 a, floatx80 b, bool mod, uint64_t *quoti= ent, - float_status *status) -{ - bool aSign, zSign; - int32_t aExp, bExp, expDiff, aExpOrig; - uint64_t aSig0, aSig1, bSig; - uint64_t q, term0, term1, alternateASig0, alternateASig1; - - *quotient =3D 0; - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig0 =3D extractFloatx80Frac( a ); - aExpOrig =3D aExp =3D extractFloatx80Exp( a ); - aSign =3D extractFloatx80Sign( a ); - bSig =3D extractFloatx80Frac( b ); - bExp =3D extractFloatx80Exp( b ); - if ( aExp =3D=3D 0x7FFF ) { - if ( (uint64_t) ( aSig0<<1 ) - || ( ( bExp =3D=3D 0x7FFF ) && (uint64_t) ( bSig<<1 ) ) ) { - return propagateFloatx80NaN(a, b, status); - } - goto invalid; - } - if ( bExp =3D=3D 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - if (aExp =3D=3D 0 && aSig0 >> 63) { - /* - * Pseudo-denormal argument must be returned in normalized - * form. - */ - return packFloatx80(aSign, 1, aSig0); - } - return a; - } - if ( bExp =3D=3D 0 ) { - if ( bSig =3D=3D 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp =3D=3D 0 ) { - if ( aSig0 =3D=3D 0 ) return a; - normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 ); - } - zSign =3D aSign; - expDiff =3D aExp - bExp; - aSig1 =3D 0; - if ( expDiff < 0 ) { - if ( mod || expDiff < -1 ) { - if (aExp =3D=3D 1 && aExpOrig =3D=3D 0) { - /* - * Pseudo-denormal argument must be returned in - * normalized form. - */ - return packFloatx80(aSign, aExp, aSig0); - } - return a; - } - shift128Right( aSig0, 0, 1, &aSig0, &aSig1 ); - expDiff =3D 0; - } - *quotient =3D q =3D ( bSig <=3D aSig0 ); - if ( q ) aSig0 -=3D bSig; - expDiff -=3D 64; - while ( 0 < expDiff ) { - q =3D estimateDiv128To64( aSig0, aSig1, bSig ); - q =3D ( 2 < q ) ? q - 2 : 0; - mul64To128( bSig, q, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 ); - shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 ); - expDiff -=3D 62; - *quotient <<=3D 62; - *quotient +=3D q; - } - expDiff +=3D 64; - if ( 0 < expDiff ) { - q =3D estimateDiv128To64( aSig0, aSig1, bSig ); - q =3D ( 2 < q ) ? q - 2 : 0; - q >>=3D 64 - expDiff; - mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 ); - shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 ); - while ( le128( term0, term1, aSig0, aSig1 ) ) { - ++q; - sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 ); - } - if (expDiff < 64) { - *quotient <<=3D expDiff; - } else { - *quotient =3D 0; - } - *quotient +=3D q; - } - else { - term1 =3D 0; - term0 =3D bSig; - } - if (!mod) { - sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASi= g1 ); - if ( lt128( alternateASig0, alternateASig1, aSig0, aSig1 ) - || ( eq128( alternateASig0, alternateASig1, aSig0, aSig= 1 ) - && ( q & 1 ) ) - ) { - aSig0 =3D alternateASig0; - aSig1 =3D alternateASig1; - zSign =3D ! zSign; - ++*quotient; - } - } - return - normalizeRoundAndPackFloatx80( - floatx80_precision_x, zSign, bExp + expDiff, aSig0, aSig1, sta= tus); - -} - -/*------------------------------------------------------------------------= ---- -| Returns the remainder of the extended double-precision floating-point va= lue -| `a' with respect to the corresponding value `b'. The operation is perfo= rmed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status) -{ - uint64_t quotient; - return floatx80_modrem(a, b, false, "ient, status); -} - -/*------------------------------------------------------------------------= ---- -| Returns the remainder of the extended double-precision floating-point va= lue -| `a' with respect to the corresponding value `b', with the quotient trunc= ated -| toward zero. -*-------------------------------------------------------------------------= ---*/ - -floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) -{ - uint64_t quotient; - return floatx80_modrem(a, b, true, "ient, status); -} - -/*------------------------------------------------------------------------= ---- -| Returns the remainder of the quadruple-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*-------------------------------------------------------------------------= ---*/ - -float128 float128_rem(float128 a, float128 b, float_status *status) -{ - bool aSign, zSign; - int32_t aExp, bExp, expDiff; - uint64_t aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2; - uint64_t allZero, alternateASig0, alternateASig1, sigMean1; - int64_t sigMean0; - - aSig1 =3D extractFloat128Frac1( a ); - aSig0 =3D extractFloat128Frac0( a ); - aExp =3D extractFloat128Exp( a ); - aSign =3D extractFloat128Sign( a ); - bSig1 =3D extractFloat128Frac1( b ); - bSig0 =3D extractFloat128Frac0( b ); - bExp =3D extractFloat128Exp( b ); - if ( aExp =3D=3D 0x7FFF ) { - if ( ( aSig0 | aSig1 ) - || ( ( bExp =3D=3D 0x7FFF ) && ( bSig0 | bSig1 ) ) ) { - return propagateFloat128NaN(a, b, status); - } - goto invalid; - } - if ( bExp =3D=3D 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - if ( bExp =3D=3D 0 ) { - if ( ( bSig0 | bSig1 ) =3D=3D 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - if ( aExp =3D=3D 0 ) { - if ( ( aSig0 | aSig1 ) =3D=3D 0 ) return a; - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - expDiff =3D aExp - bExp; - if ( expDiff < -1 ) return a; - shortShift128Left( - aSig0 | UINT64_C(0x0001000000000000), - aSig1, - 15 - ( expDiff < 0 ), - &aSig0, - &aSig1 - ); - shortShift128Left( - bSig0 | UINT64_C(0x0001000000000000), bSig1, 15, &bSig0, &bSig1 ); - q =3D le128( bSig0, bSig1, aSig0, aSig1 ); - if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 ); - expDiff -=3D 64; - while ( 0 < expDiff ) { - q =3D estimateDiv128To64( aSig0, aSig1, bSig0 ); - q =3D ( 4 < q ) ? q - 4 : 0; - mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 ); - shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZe= ro ); - shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero ); - sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 ); - expDiff -=3D 61; - } - if ( -64 < expDiff ) { - q =3D estimateDiv128To64( aSig0, aSig1, bSig0 ); - q =3D ( 4 < q ) ? q - 4 : 0; - q >>=3D - expDiff; - shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 ); - expDiff +=3D 52; - if ( expDiff < 0 ) { - shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 ); - } - else { - shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 ); - } - mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 ); - sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 ); - } - else { - shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 ); - shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 ); - } - do { - alternateASig0 =3D aSig0; - alternateASig1 =3D aSig1; - ++q; - sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 ); - } while ( 0 <=3D (int64_t) aSig0 ); - add128( - aSig0, aSig1, alternateASig0, alternateASig1, (uint64_t *)&sigMean= 0, &sigMean1 ); - if ( ( sigMean0 < 0 ) - || ( ( ( sigMean0 | sigMean1 ) =3D=3D 0 ) && ( q & 1 ) ) ) { - aSig0 =3D alternateASig0; - aSig1 =3D alternateASig1; - } - zSign =3D ( (int64_t) aSig0 < 0 ); - if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 ); - return normalizeRoundAndPackFloat128(aSign ^ zSign, bExp - 4, aSig0, a= Sig1, - status); -} static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3659c6a4c0..1bc8db4cf1 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -625,6 +625,40 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatP= artsN *b, return a; } =20 +/* + * Floating point remainder, per IEC/IEEE, or modulus. + */ +static FloatPartsN *partsN(modrem)(FloatPartsN *a, FloatPartsN *b, + uint64_t *mod_quot, float_status *s) +{ + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + + if (likely(ab_mask =3D=3D float_cmask_normal)) { + frac_modrem(a, b, mod_quot); + return a; + } + + if (mod_quot) { + *mod_quot =3D 0; + } + + /* All the NaN cases */ + if (unlikely(ab_mask & float_cmask_anynan)) { + return parts_pick_nan(a, b, s); + } + + /* Inf % N; N % 0 */ + if (a->cls =3D=3D float_class_inf || b->cls =3D=3D float_class_zero) { + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + + /* N % Inf; 0 % N */ + g_assert(b->cls =3D=3D float_class_inf || a->cls =3D=3D float_class_ze= ro); + return a; +} + /* * Square Root * diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 88eab344df..6754a94afc 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -636,62 +636,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass = b_cls, FloatClass c_cls, #endif } =20 -/*------------------------------------------------------------------------= ---- -| Takes two single-precision floating-point values `a' and `b', one of whi= ch -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' = is a -| signaling NaN, the invalid exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static float32 propagateFloat32NaN(float32 a, float32 b, float_status *sta= tus) -{ - bool aIsLargerSignificand; - uint32_t av, bv; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls =3D (!float32_is_any_nan(a) - ? float_class_normal - : float32_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls =3D (!float32_is_any_nan(b) - ? float_class_normal - : float32_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - av =3D float32_val(a); - bv =3D float32_val(b); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float32_default_nan(status); - } - - if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { - aIsLargerSignificand =3D 0; - } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { - aIsLargerSignificand =3D 1; - } else { - aIsLargerSignificand =3D (av < bv) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return float32_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float32_silence_nan(a, status); - } - return a; - } -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -732,62 +676,6 @@ bool float64_is_signaling_nan(float64 a_, float_status= *status) } } =20 -/*------------------------------------------------------------------------= ---- -| Takes two double-precision floating-point values `a' and `b', one of whi= ch -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' = is a -| signaling NaN, the invalid exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static float64 propagateFloat64NaN(float64 a, float64 b, float_status *sta= tus) -{ - bool aIsLargerSignificand; - uint64_t av, bv; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls =3D (!float64_is_any_nan(a) - ? float_class_normal - : float64_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls =3D (!float64_is_any_nan(b) - ? float_class_normal - : float64_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - av =3D float64_val(a); - bv =3D float64_val(b); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float64_default_nan(status); - } - - if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { - aIsLargerSignificand =3D 0; - } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { - aIsLargerSignificand =3D 1; - } else { - aIsLargerSignificand =3D (av < bv) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return float64_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float64_silence_nan(a, status); - } - return a; - } -} - /*------------------------------------------------------------------------= ---- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -942,56 +830,3 @@ bool float128_is_signaling_nan(float128 a, float_statu= s *status) } } } - -/*------------------------------------------------------------------------= ---- -| Takes two quadruple-precision floating-point values `a' and `b', one of -| which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*-------------------------------------------------------------------------= ---*/ - -static float128 propagateFloat128NaN(float128 a, float128 b, - float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls =3D (!float128_is_any_nan(a) - ? float_class_normal - : float128_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls =3D (!float128_is_any_nan(b) - ? float_class_normal - : float128_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float128_default_nan(status); - } - - if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { - aIsLargerSignificand =3D 0; - } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { - aIsLargerSignificand =3D 1; - } else { - aIsLargerSignificand =3D (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return float128_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float128_silence_nan(a, status); - } - return a; - } -} --=20 2.25.1