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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id a63sm12270550qkf.132.2021.05.04.20.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 20:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jlgETGbZuRzHBHvHlcUoL6xtFf9QKaaxdVGn5r8yTJA=; b=Gka7U2VPWD7XS/ZTppMHp81DH3AVgFEmnJCSPQkWFJCKmxh9Vsh69KLMcI25e3alRW MSe9PP2ACvY5t+1SPF/6ihyzK+wrmacoa3Cj1upylzQjaESfFe5Rm1fWY6yEgw42UyC0 /7W/OuM6vr3GC4KPa+C/ZGHstGQhPgeeMY5YoJ8cb6XbLWsSldgSwx91aHcBReEHiVxt copkclDr260xff6T2HsdjhC2VZFncKqlCilbPB3wlTuJJ8dH+gIFPrObSv/efE/D1fBa yzmEPH4qB1qnlX3zFGp3SGEOia14R+E2pNtjVzXJn3nbZfb51iISFnnSj9kS3DZmxs7V oxxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jlgETGbZuRzHBHvHlcUoL6xtFf9QKaaxdVGn5r8yTJA=; b=TZSX29EmvkSA+Ii6X2faqYoujwfXJUthSMAxYoHi0e5ycnstQB0XAe1Wf3nzSOZUJQ vMq3P+dbGVxlMIT3cU7t1axvKoN/h/QCenIQKBzGVGmDufR0dYebK/5n4iaKNXsGB4N/ vtpJDZl3M0VI4Cm8eh1lr9sK8kxxi6ceu6BkgFHxsdGmt2rV1A0zERIJdURXlielbQJ8 VUdHJ+6MjVYlJqrPnTjRsWbBOmkcatadFbHqXu7jFgNP8o0x4x2DBMB+dgFtMkYJvhHF ZLEmX9zmzlsn+ZkUALcZI4oD2iFz1xhuWoVnSNvuzGrBcacFkOgCCLfcGiVJKHo9Stis hncw== X-Gm-Message-State: AOAM533dehjLf09Vai/1pVhcTpNCNYEncE6H6TgjHi0DhmTEsPw9Bu2y aw3ue+wbS+r408vWZk01IncoBw== X-Google-Smtp-Source: ABdhPJzCWqD6tc2CSmRF7TepIODm8BL0oIFfd5GgZG8jCkXy0LGjNVy5ru3Xb7nQVf0nFYP5KsYQIg== X-Received: by 2002:a0c:ca8c:: with SMTP id a12mr28588897qvk.14.1620183905802; Tue, 04 May 2021 20:05:05 -0700 (PDT) From: Rebecca Cran To: Richard Henderson , Peter Maydell Subject: [PATCH v8 2/4] target/arm: Add support for FEAT_TLBIRANGE Date: Tue, 4 May 2021 21:04:41 -0600 Message-Id: <20210505030443.25310-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210505030443.25310-1-rebecca@nuviainc.com> References: <20210505030443.25310-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=rebecca@nuviainc.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 + target/arm/helper.c | 296 ++++++++++++++++++++ 2 files changed, 301 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b39325347..5802798c3069 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4071,6 +4071,11 @@ static inline bool isar_feature_aa64_pauth_arch(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; } =20 +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b1b98705f91..cb10851efda8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4759,6 +4759,219 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } =20 +#ifdef TARGET_AARCH64 +static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, + uint64_t value) +{ + unsigned int page_shift; + unsigned int page_size_granule; + uint64_t num; + uint64_t scale; + uint64_t exponent; + uint64_t length; + + num =3D extract64(value, 39, 4); + scale =3D extract64(value, 44, 2); + page_size_granule =3D extract64(value, 46, 2); + + page_shift =3D page_size_granule * 2 + 10; + + if (page_size_granule =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + return 0; + } + + exponent =3D (5 * scale) + 1; + length =3D (num + 1) << (exponent + page_shift); + + return length; +} + +static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMMMUIdx mmu_idx; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + mask =3D vae1_tlbmask(env); + mmu_idx =3D ARM_MMU_IDX_A | ctz32(mask); + if (regime_has_2_ranges(mmu_idx)) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, mmu_idx, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + ARMMMUIdx mmu_idx; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + mask =3D vae1_tlbmask(env); + mmu_idx =3D ARM_MMU_IDX_A | ctz32(mask); + if (regime_has_2_ranges(mmu_idx)) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, mmu_idx, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + bool secure; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + secure =3D arm_is_secure_below_el3(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, + * since we don't support flush-for-specific-ASID-only, + * flush-last-level-only or inner/outer shareable specific flushes. + */ + bool secure; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + secure =3D arm_is_secure_below_el3(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_S= E3, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, + ARMMMUIdxBit_SE3, + bits); + } +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, + * since we don't support flush-for-specific-ASID-only, + * flush-last-level-only or inner/outer specific flushes. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_SE3, + bits); +} +#endif + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { @@ -6920,6 +7133,86 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbirange_reginfo[] =3D { + { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8289,6 +8582,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_tlbirange, cpu)) { + define_arm_cp_regs(cpu, tlbirange_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2