From nobody Tue Apr 23 17:59:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620130917; cv=none; d=zohomail.com; s=zohoarc; b=ZLBBzqlf/9FU5akMS/eGJqnRE/eOuQr9bvopjo42FNzJ8FJ/VAk5hT9SosUdRV5ZamU0YUrUHVts4vMq1/yeyyr4eaqdkAS3vcv8qxaD1vtS9kmelAzLl2+OKfPsRtH0DjgcELO3owZOdZKC0NVIlxobsrNA6gMfZadRkBQ/jTA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620130917; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L/Ak9T5/Ybf7tAcf0Rd3JQPpQ3KguyaRrNYfpLxJyhc=; b=mDLTqRBEz0YABLQlIy6MsdXtXZYvyPrIs18xQmvlY4+ZLCV2vv447AbaM6EUCFlQ0Db0wRkFSRKXn2uYc5GWM6GHIGaZ/9CkeQ00KshFwM3pQuNg8kgGewOPiDAc8VFQrgYebwbUgyfKhlGd9B/m02gCoHZKP4T+Na0AR8JynH4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1620130917624172.61370617596015; Tue, 4 May 2021 05:21:57 -0700 (PDT) Received: from localhost ([::1]:33294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldu3m-0003Vl-8j for importer@patchew.org; Tue, 04 May 2021 08:21:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldtrg-0005l1-Qy for qemu-devel@nongnu.org; Tue, 04 May 2021 08:09:24 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:36550) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ldtrb-0007aD-0s for qemu-devel@nongnu.org; Tue, 04 May 2021 08:09:24 -0400 Received: by mail-wr1-x433.google.com with SMTP id m9so9154524wrx.3 for ; Tue, 04 May 2021 05:09:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g12sm2331937wmh.24.2021.05.04.05.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 05:09:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L/Ak9T5/Ybf7tAcf0Rd3JQPpQ3KguyaRrNYfpLxJyhc=; b=X9a0KimzEiDF3OWSqeIMc03RSURCRfRj96ARQ0oqSTjh0+kTfOpkLRGEyasdANTc2A YaHwuot6plpdZeVaVd0RvfzKx8BzjzrYk2CL6xVM3ALJyvSRKGqqpgLC3fm/WG6F7ewH DnyzZ6xUK6eBznRvFFKnf4J7IZFz5mcyaRgnVkNWPbyGztUlPgbyNy+0dNvNqWQXz87J ALClj4ua/Yl4VnhlCdz1cpyGL0r0wagqpm9ZGs32BLfVo+ds8cfRqguiGMWhNVHCTwsD KfXlRqJRsW0Yu16q+dUqp+AtYi2FA4m8y0zsJ09DMdmKgJHLsvEs9IRm8a4sA0L/pfF1 uevw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L/Ak9T5/Ybf7tAcf0Rd3JQPpQ3KguyaRrNYfpLxJyhc=; b=en7dO7FPpOjNY4/73eOUmy/Oul2Qtau+gBB1Emo0tplT3rItRFXFkkq9T+9COA+NlN ufcHfs9Z4UVJzG2TP9bMhTYL1I6BtqDMTITQlZ0HX3T9D55S9KU9RRC88dOvVN7Gh3L/ v4ZjaSdYirKRmQQ0TxVkYUH7LEGMq2LH274UistG13IxBEIa6+FrC833VSSFJvqANrKt vSwlJGsObUKpCaIGlrETiJpe3KxddmLRlDQefjONAksOIONNYz2KvX4IsWtQefXeXtg/ u+mJHFJdO46V/5VIvsVd9yc967EqMy+fedFm3Su9LaTb43vsRel7fSTCTcm0pAQ0bhcj 65FA== X-Gm-Message-State: AOAM530I/OV2TQdk3pm6AVbcROuE1+b97s2LGcZ4hVv6vz/f9280TcMH s/qyKxYQArQs9jTZA6L1ZtbG8g== X-Google-Smtp-Source: ABdhPJzQeDAQfH8QV+2L9Je9VOhmV9uGnuF2rKt46i3pCLFsq2jm9VRo1Urzjp2R2GODdeW1n9m//g== X-Received: by 2002:a5d:554a:: with SMTP id g10mr29205593wrw.174.1620130155687; Tue, 04 May 2021 05:09:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/3] hw/misc/mps2-scc: Add "QEMU interface" comment Date: Tue, 4 May 2021 13:09:10 +0100 Message-Id: <20210504120912.23094-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210504120912.23094-1-peter.maydell@linaro.org> References: <20210504120912.23094-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The MPS2 SCC device doesn't have any documentation of its properties; add a "QEMU interface" format comment describing them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/mps2-scc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index 49d070616aa..ea261ea30d6 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -9,6 +9,18 @@ * (at your option) any later version. */ =20 +/* + * This is a model of the Serial Communication Controller (SCC) + * block found in most MPS FPGA images. + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + * + QOM property "scc-cfg4": value of the read-only CFG4 register + * + QOM property "scc-aid": value of the read-only SCC_AID register + * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property array "oscclk": reset values of the OSCCLK registers + * (which are accessed via the SYS_CFG channel provided by this device) + */ #ifndef MPS2_SCC_H #define MPS2_SCC_H =20 --=20 2.20.1 From nobody Tue Apr 23 17:59:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620130623; cv=none; d=zohomail.com; s=zohoarc; b=eXfI6FVivl73DnMl7k6YxXUCg/+eAIfCaDoVsm5Pq12rVKtE/q8PG0WJsrfYtiFG3b9IjlPfnwnJXG316rg2D7G8LtlUQg2Kcm4AT9zxUvgETMxlaeTR4t6sxskBx/T40BdY3NRBEQuiN5I85Z1g7Gr7qUTWbc9C09iDYJmSCto= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620130623; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KuiIpEF0YJllksN7WscZeUdPX+/jT9Kso4l8u6ZSxUM=; b=UVxDgVQnXEKn7zxwiE3to+BwTjaYOpTCl3IkoLli67r2VzJdFaBZJKMnhZK+ZvZ9Y0NXsp+n6JJ+68IhySWwYMQGFYb45emn/wAnDkURtrU+EX332pIIsI0zn0WL1jvTULqFZv6PIsJQs2lfVuK+LRF3fM6CxtywBsbIobAC0WI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1620130623915570.6943300653082; Tue, 4 May 2021 05:17:03 -0700 (PDT) Received: from localhost ([::1]:55072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldtz4-0000jn-TE for importer@patchew.org; Tue, 04 May 2021 08:17:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldtrf-0005j9-WC for qemu-devel@nongnu.org; Tue, 04 May 2021 08:09:24 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:42543) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ldtrb-0007aQ-0s for qemu-devel@nongnu.org; Tue, 04 May 2021 08:09:23 -0400 Received: by mail-wr1-x433.google.com with SMTP id l2so9130302wrm.9 for ; Tue, 04 May 2021 05:09:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g12sm2331937wmh.24.2021.05.04.05.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 05:09:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KuiIpEF0YJllksN7WscZeUdPX+/jT9Kso4l8u6ZSxUM=; b=s3hoVzHddgKpKV+oQPoR/xnIkJ2iFugm/Wnd4yaoEiaWvpu0ug9Yz9/zGpPmG8h576 /gOYhKvzR+bID2qduYICF8NjUN5mA6KCn+KZJtC7s0UaRIMEnZamg4Ww+cFJLV95eDbl IpyNghBuawtVeLcWmuEbH61rD8yDJDZFPBJTkpeEd3QPQB70IEdoqB4AN/v9bU/yzftU JJpq71bAt1PXcyzw686AE8AlWuw+tSADLJb11YtnU4o7y1W9i1HeWsbkzt+tuUgOPXmP oLJtjsdJ/a7DXwMybctH+yXgvJ+T5Mw1ZRfDqcLZKyWAio9S65humGK0iBbhZdNCWqsQ y/eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KuiIpEF0YJllksN7WscZeUdPX+/jT9Kso4l8u6ZSxUM=; b=HU6Rx52LIPczUBLVB0FZmoBhpVp0y1ESPav5Jic+LjckqGkgy1vagJ8udBTg4sZRAK 80WWVF9QaUOGZ+94zrbMZfgt4CwO0w3IoIhKN5Fr9PHHHXdoXS/U/4k7ITND+C9e3NTB vHu8zgwz9fbGFiCapM92GL1QryiGhjqdL5kqwSvK0S2hQlT9apTrc9wznSZxhk/DLiw8 im4M7IKmUgdGpMjcbf00MuFJ47yZh4kb9tQMeu6dqFQN5OxW/lRHRp5/lsGPDqMFGYSj ZiNXOQ3JVVWVy9bRcaJkXbsBGkQpBoS6ysOmN0wS8eQfUZiIxLWLXwWVbQ1UkB9Vv2aC pxTA== X-Gm-Message-State: AOAM533k+uieYzss5z3me4+pGvixHWXcqTIlPZub5El/tkF/m6xQsZzi +eC1z5lgeecwROIiVJBH1+W09w== X-Google-Smtp-Source: ABdhPJy/kWvK9XRSVZ6pCVbFyQHk2LQh/fjIv9TBraQ3kejg25GVwrPUPd1sGg52QZDUdqRhc7W2uA== X-Received: by 2002:adf:ec4a:: with SMTP id w10mr598958wrn.388.1620130156450; Tue, 04 May 2021 05:09:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/3] hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping Date: Tue, 4 May 2021 13:09:11 +0100 Message-Id: <20210504120912.23094-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210504120912.23094-1-peter.maydell@linaro.org> References: <20210504120912.23094-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) On some boards, SCC config register CFG0 bit 0 controls whether parts of the board memory map are remapped. Support this with: * a device property scc-cfg0 so the board can specify the initial value of the CFG0 register * an outbound GPIO line which tracks bit 0 and which the board can wire up to provide the remapping Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/mps2-scc.h | 9 +++++++++ hw/misc/mps2-scc.c | 13 ++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index ea261ea30d6..3b2d13ac9c3 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -18,8 +18,14 @@ * + QOM property "scc-cfg4": value of the read-only CFG4 register * + QOM property "scc-aid": value of the read-only SCC_AID register * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property "scc-cfg0": reset value of the CFG0 register * + QOM property array "oscclk": reset values of the OSCCLK registers * (which are accessed via the SYS_CFG channel provided by this device) + * + named GPIO output "remap": this tracks the value of CFG0 register + * bit 0. Boards where this bit controls memory remapping should + * connect this GPIO line to a function performing that mapping. + * Boards where bit 0 has no special function should leave the GPIO + * output disconnected. */ #ifndef MPS2_SCC_H #define MPS2_SCC_H @@ -55,6 +61,9 @@ struct MPS2SCC { uint32_t num_oscclk; uint32_t *oscclk; uint32_t *oscclk_reset; + uint32_t cfg0_reset; + + qemu_irq remap; }; =20 #endif diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index c56aca86ad5..b3b42a792cd 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -23,6 +23,7 @@ #include "qemu/bitops.h" #include "trace.h" #include "hw/sysbus.h" +#include "hw/irq.h" #include "migration/vmstate.h" #include "hw/registerfields.h" #include "hw/misc/mps2-scc.h" @@ -186,10 +187,13 @@ static void mps2_scc_write(void *opaque, hwaddr offse= t, uint64_t value, switch (offset) { case A_CFG0: /* - * TODO on some boards bit 0 controls RAM remapping; - * on others bit 1 is CPU_WAIT. + * On some boards bit 0 controls board-specific remapping; + * we always reflect bit 0 in the 'remap' GPIO output line, + * and let the board wire it up or not as it chooses. + * TODO on some boards bit 1 is CPU_WAIT. */ s->cfg0 =3D value; + qemu_set_irq(s->remap, s->cfg0 & 1); break; case A_CFG1: s->cfg1 =3D value; @@ -283,7 +287,7 @@ static void mps2_scc_reset(DeviceState *dev) int i; =20 trace_mps2_scc_reset(); - s->cfg0 =3D 0; + s->cfg0 =3D s->cfg0_reset; s->cfg1 =3D 0; s->cfg2 =3D 0; s->cfg5 =3D 0; @@ -308,6 +312,7 @@ static void mps2_scc_init(Object *obj) =20 memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x= 1000); sysbus_init_mmio(sbd, &s->iomem); + qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1); } =20 static void mps2_scc_realize(DeviceState *dev, Error **errp) @@ -353,6 +358,8 @@ static Property mps2_scc_properties[] =3D { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), + /* Reset value for CFG0 register */ + DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0), /* * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the --=20 2.20.1 From nobody Tue Apr 23 17:59:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1620130723; cv=none; d=zohomail.com; s=zohoarc; b=XimQAvTwOLKLdvS24EZHStIWf+iXgrAsVIAqtDzzxTZiRBY4yDYUnuwAL+JLX+xcXnfztoJu2S578dfyKhBxnEPKQBMyCHxbijAbebJ6a1OG8y15s0RoSWuncHFLH0fUuF2f+MJSdsObMk2XenNimeyKQC6GgTxUeu3KxONkCmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620130723; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xtnjRpH/M1p4kG/EfjsDmpeMdCMMHQQ4OMa75O4RxaA=; b=hDhrpaLgKgDnrMKGxAMh3won7pB/seD3wo4/mZk5E0ebKN46QFXkSFboFp0trlsRq4aMQgVrhJvd0N4BbrxPCPLZS9q4gpPRDffEJraw+Q9yaYXdKr4ZVwEsB7yHzcHKhBKViuLDDb+HmXIOQmDtCmy7T9bPDx2gEN+Ku34/CSc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162013072346153.8986531189189; Tue, 4 May 2021 05:18:43 -0700 (PDT) Received: from localhost ([::1]:57118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldu0f-0001Zn-87 for importer@patchew.org; Tue, 04 May 2021 08:18:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldtre-0005gx-FF for qemu-devel@nongnu.org; Tue, 04 May 2021 08:09:22 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ldtrb-0007ab-02 for qemu-devel@nongnu.org; Tue, 04 May 2021 08:09:22 -0400 Received: by mail-wr1-x42c.google.com with SMTP id m9so9154640wrx.3 for ; Tue, 04 May 2021 05:09:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g12sm2331937wmh.24.2021.05.04.05.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 05:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xtnjRpH/M1p4kG/EfjsDmpeMdCMMHQQ4OMa75O4RxaA=; b=c2jSyHzeFhabIOAXxQrQg6TaE0SzwuD/dkeHYKUMyPGX+GijSNfA9vVB7LRfo5mFtk XCmqc3/Cdm9KeQXG2WWoFGrlANSMZhSIueUBLBGGZ1pMxjGpLfulkVx+UVQLIGvr+ltf jGLcpYIzm3caB0YNIdGx3+/F+oVjxpO2AXpmylwAETEbPD91AvDE4U4vOmBkgY23tmH7 URTv3WPUNd8VuRP1P3G893X2e16ghBlqqRjEdVspyPzJ4zJ865aNMT0X5mFNJGU8j2RJ A+YAEfE5LOBN8D9J6mil+6vgNrsIZjNmO5AmU9jHT0qDCzXGczofaLTb5h/8Y2ixWrq+ 5Psw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xtnjRpH/M1p4kG/EfjsDmpeMdCMMHQQ4OMa75O4RxaA=; b=kwaKBEi59jFYiRYzHinF+8Dx4a5bwzPXaq0HVbZZZ1Pmkc+HC58tsDkN9FrSdCu+CR 4SJGQgaboTAvEnf6QK7Follg1ovsMYa+LTtpkzDwxt706wHFnxvc461L+wkrbgkkvSPs X0uCtW1hQMrldlrn5Zq/uBh3cw1/kON9MI++9oudI1l7kXjC03sukTPs6YkEaVKGwpsl vHAjO0Nkb26AcP/afH97sMaMO8rcBc/E8qwe8ZiQtzfkNG0NxgbMTA3e3sjFMiV7fnJK w8Qp1PpYoYhUF6x0HSm+O+81Aaer3lUa0pfksZ+8OZgwpFi/GayXcdXzQaOLOBGBv16C 0bWA== X-Gm-Message-State: AOAM530Xn7mQz8oXiGxsVpAPGHydbHjgkZ2/Ys9GVzb1qf4zXqahfb8f QO1Jahg6zI+aamdi72jLqLkVOkgbx4nkpQ== X-Google-Smtp-Source: ABdhPJzxkQjS0CNXmCELy+QLqvcotk9JlTd46DIs8TSSvCbv5y11SgfCkyUo0qoAyTJGMJD38zxyTA== X-Received: by 2002:adf:f94c:: with SMTP id q12mr30519071wrr.283.1620130157454; Tue, 04 May 2021 05:09:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/3] hw/arm/mps2-tz: Implement AN524 memory remapping via machine property Date: Tue, 4 May 2021 13:09:12 +0100 Message-Id: <20210504120912.23094-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210504120912.23094-1-peter.maydell@linaro.org> References: <20210504120912.23094-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The AN524 FPGA image supports two memory maps, which differ in where the QSPI and BRAM are. In the default map, the BRAM is at 0x0000_0000, and the QSPI at 0x2800_0000. In the second map, they are the other way around. In hardware, the initial mapping can be selected by the user by writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the board configuration file. The board config file is acted on by the "Motherboard Configuration Controller", which is an entirely separate microcontroller on the dev board but outside the FPGA. The guest can also dynamically change the mapping via the SCC CFG_REG0 register. Implement this functionality for QEMU, using a machine property "remap" with valid values "BRAM" and "QSPI" to allow the user to set the initial mapping, in the same way they can on the FPGA, and wiring up the bit from the SCC register to also switch the mapping. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v2: * tweaked commit message to clarify that the MCC is external * use memory_region_transaction_begin/commit * make remap be bool rather than int --- docs/system/arm/mps2.rst | 10 ++++ hw/arm/mps2-tz.c | 108 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 117 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index f83b1517871..8a75beb3a08 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -45,3 +45,13 @@ Differences between QEMU and real hardware: flash, but only as simple ROM, so attempting to rewrite the flash from the guest will fail - QEMU does not model the USB controller in MPS3 boards + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +remap + Supported for ``mps3-an524`` only. + Set ``BRAM``/``QSPI`` to select the initial memory mapping. The + default is ``BRAM``. diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 25016e464d9..70aa31a7f6c 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -55,6 +55,7 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "sysemu/reset.h" #include "hw/misc/unimp.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/timer/cmsdk-apb-timer.h" @@ -72,6 +73,7 @@ #include "hw/core/split-irq.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/irq.h" =20 #define MPS2TZ_NUMIRQ_MAX 96 #define MPS2TZ_RAM_MAX 5 @@ -153,6 +155,9 @@ struct MPS2TZMachineState { SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; + + bool remap; + qemu_irq remap_irq; }; =20 #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -228,6 +233,10 @@ static const RAMInfo an505_raminfo[] =3D { { }, }; =20 +/* + * Note that the addresses and MPC numbering here should match up + * with those used in remap_memory(), which can swap the BRAM and QSPI. + */ static const RAMInfo an524_raminfo[] =3D { { .name =3D "bram", .base =3D 0x00000000, @@ -457,6 +466,7 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, = void *opaque, =20 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev =3D DEVICE(scc); + qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); @@ -573,6 +583,52 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms,= void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } =20 +static hwaddr boot_mem_base(MPS2TZMachineState *mms) +{ + /* + * Return the canonical address of the block which will be mapped + * at address 0x0 (i.e. where the vector table is). + * This is usually 0, but if the AN524 alternate memory map is + * enabled it will be the base address of the QSPI block. + */ + return mms->remap ? 0x28000000 : 0; +} + +static void remap_memory(MPS2TZMachineState *mms, int map) +{ + /* + * Remap the memory for the AN524. 'map' is the value of + * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 + * for the "option 1" mapping where QSPI is at address 0. + * + * Effectively we need to swap around the "upstream" ends of + * MPC 0 and MPC 1. + */ + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + int i; + + if (mmc->fpga_type !=3D FPGA_AN524) { + return; + } + + memory_region_transaction_begin(); + for (i =3D 0; i < 2; i++) { + TZMPC *mpc =3D &mms->mpc[i]; + MemoryRegion *upstream =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(m= pc), 1); + hwaddr addr =3D (i ^ map) ? 0x28000000 : 0; + + memory_region_set_address(upstream, addr); + } + memory_region_transaction_commit(); +} + +static void remap_irq_fn(void *opaque, int n, int level) +{ + MPS2TZMachineState *mms =3D opaque; + + remap_memory(mms, level); +} + static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -711,7 +767,7 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); =20 for (p =3D mmc->raminfo; p->name; p++) { - if (p->base =3D=3D 0) { + if (p->base =3D=3D boot_mem_base(mms)) { return p->size; } } @@ -1095,6 +1151,16 @@ static void mps2tz_common_init(MachineState *machine) =20 create_non_mpc_ram(mms); =20 + if (mmc->fpga_type =3D=3D FPGA_AN524) { + /* + * Connect the line from the SCC so that we can remap when the + * guest updates that register. + */ + mms->remap_irq =3D qemu_allocate_irq(remap_irq_fn, mms, 0); + qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, + mms->remap_irq); + } + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, boot_ram_size(mms)); } @@ -1117,12 +1183,47 @@ static void mps2_tz_idau_check(IDAUInterface *ii, u= int32_t address, *iregion =3D region; } =20 +static char *mps2_get_remap(Object *obj, Error **errp) +{ + MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(obj); + const char *val =3D mms->remap ? "QSPI" : "BRAM"; + return g_strdup(val); +} + +static void mps2_set_remap(Object *obj, const char *value, Error **errp) +{ + MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(obj); + + if (!strcmp(value, "BRAM")) { + mms->remap =3D false; + } else if (!strcmp(value, "QSPI")) { + mms->remap =3D true; + } else { + error_setg(errp, "Invalid remap value"); + error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); + } +} + +static void mps2_machine_reset(MachineState *machine) +{ + MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); + + /* + * Set the initial memory mapping before triggering the reset of + * the rest of the system, so that the guest image loader and CPU + * reset see the correct mapping. + */ + remap_memory(mms, mms->remap); + qemu_devices_reset(); +} + static void mps2tz_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(oc); =20 mc->init =3D mps2tz_common_init; + mc->reset =3D mps2_machine_reset; iic->check =3D mps2_tz_idau_check; } =20 @@ -1225,6 +1326,11 @@ static void mps3tz_an524_class_init(ObjectClass *oc,= void *data) mmc->raminfo =3D an524_raminfo; mmc->armsse_type =3D TYPE_SSE200; mps2tz_set_default_ram_info(mmc); + + object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_re= map); + object_class_property_set_description(oc, "remap", + "Set memory mapping. Valid value= s " + "are BRAM (default) and QSPI."); } =20 static void mps3tz_an547_class_init(ObjectClass *oc, void *data) --=20 2.20.1