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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id i14sm19973067wmq.1.2021.05.02.09.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x19cjSTQwIq79xCZBtZq0kMD0w0hQS1PLNYgzSi3WfA=; b=A4ttA+zHp2WsueJxPjCtFWT5UHVmP4jc3UV3g3fFL5an21X4DZflQ4F76PDYnmVG8T XmdZxEhARPCihriOsAP2Kzc2Zom8npIcePCIV5sLF7zWhnjIfkUWvkYH6zyD82D9BYCy tHchhNbnN/aTbtZBs7lFyEqvSAe9SyW3AF8yBP/ZEzkE9Uo5Vd5UVcs3yULGYvpOTSuw UVydqkuX6zIFdwnOwOc7wInXMkPJK6xIfctARC5uwoZClGgJd114ZFbJH9IxvBmJ3C8P UjSIQKIUf4byEQVDELeXuFMi1Tav/PvmqF0QqnSxO1ThWCjQrpVZCbv74qGGsJRnGv2F 3PUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=x19cjSTQwIq79xCZBtZq0kMD0w0hQS1PLNYgzSi3WfA=; b=uleIR+rX0maJsS7i+1gDiXRMXTlbRUcjTZrfWidlUiU50+xaqtdm2Gd9/zJb/ciMFz VBDxT+vFjUfrjEVOKW5p0OQzVBfHiHm6yj1aJBXFAmVJ0BERT8ad7r1mD+ntooYvavub diC6s8+B5a62Ikv303lOs6tEyY9u/wkByKTwsdJKxFIgTu63Ub+aezayzN9gpV9rxTsF I5LeLfZXalQf/sML7rOYyZaDmYu7oQaiWrfGHmudMX8lWKCr/sJeMqXX+lKCQTKImHtb VFWyQT8uXjJBIobuDqnJqxRd5ck2JgPJdCmFVZYVFRjIQghRVgVYglzAGmns6F3siwHx gdCA== X-Gm-Message-State: AOAM5301+ScmrdzYS+0dwOds2u7nfxlLsOrBdSzErL1n0mMPFAdKT344 CyLTWX2sozgKDPockR22eWU= X-Google-Smtp-Source: ABdhPJxRcyAKZZLkHM4YGYD8RxiYjSDkFA6wiDQW6loOS1BsPKyAolVX/XjLWmUhRMZ7pA+LapdweA== X-Received: by 2002:a5d:4707:: with SMTP id y7mr20149320wrq.137.1619972291271; Sun, 02 May 2021 09:18:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 29/36] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Date: Sun, 2 May 2021 18:15:31 +0200 Message-Id: <20210502161538.534038-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-24-f4bug@amsat.org> --- target/mips/helper.h | 5 - target/mips/tcg/tcg-internal.h | 3 + target/mips/tcg/sysemu_helper.h.inc | 7 ++ target/mips/cpu.c | 17 --- target/mips/op_helper.c | 100 ----------------- target/mips/tcg/sysemu/special_helper.c | 140 ++++++++++++++++++++++++ target/mips/tcg/sysemu/meson.build | 1 + 7 files changed, 151 insertions(+), 122 deletions(-) create mode 100644 target/mips/tcg/sysemu/special_helper.c diff --git a/target/mips/helper.h b/target/mips/helper.h index bc308e5db13..4ee7916d8b2 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env) DEF_HELPER_1(tlbr, void, env) DEF_HELPER_1(tlbinv, void, env) DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_1(di, tl, env) -DEF_HELPER_1(ei, tl, env) -DEF_HELPER_1(eret, void, env) -DEF_HELPER_1(eretnc, void, env) -DEF_HELPER_1(deret, void, env) DEF_HELPER_3(ginvt, void, env, tl, i32) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index a39ff45d58f..73667b35778 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -10,6 +10,7 @@ #ifndef MIPS_TCG_INTERNAL_H #define MIPS_TCG_INTERNAL_H =20 +#include "tcg/tcg.h" #include "hw/core/cpu.h" #include "cpu.h" =20 @@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1= , int32_t *pagemask); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb); + hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index d136c4160a7..38e55cbf118 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env) /* R6 Multi-threading */ DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) + +/* Special */ +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(eretnc, void, env) +DEF_HELPER_1(deret, void, env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c3159e3d7f3..a33e3b6c202 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -342,23 +342,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } - -# ifndef CONFIG_USER_ONLY -static bool mips_io_recompile_replay_branch(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { - env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - env->hflags &=3D ~MIPS_HFLAG_BMASK; - return true; - } - return false; -} -# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 static bool mips_cpu_has_work(CPUState *cs) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 7a7369bc8a6..a077535194b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -655,106 +655,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg= , uint32_t type) } } =20 -/* Specials */ -target_ulong helper_di(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 & ~(1 << CP0St_IE); - return t0; -} - -target_ulong helper_ei(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 | (1 << CP0St_IE); - return t0; -} - -static void debug_pre_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - qemu_log("\n"); - } -} - -static void debug_post_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -static inline void exception_return(CPUMIPSState *env) -{ - debug_pre_eret(env); - if (env->CP0_Status & (1 << CP0St_ERL)) { - mips_env_set_pc(env, env->CP0_ErrorEPC); - env->CP0_Status &=3D ~(1 << CP0St_ERL); - } else { - mips_env_set_pc(env, env->CP0_EPC); - env->CP0_Status &=3D ~(1 << CP0St_EXL); - } - compute_hflags(env); - debug_post_eret(env); -} - -void helper_eret(CPUMIPSState *env) -{ - exception_return(env); - env->CP0_LLAddr =3D 1; - env->lladdr =3D 1; -} - -void helper_eretnc(CPUMIPSState *env) -{ - exception_return(env); -} - -void helper_deret(CPUMIPSState *env) -{ - debug_pre_eret(env); - - env->hflags &=3D ~MIPS_HFLAG_DM; - compute_hflags(env); - - mips_env_set_pc(env, env->CP0_DEPC); - - debug_post_eret(env); -} #endif /* !CONFIG_USER_ONLY */ =20 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c new file mode 100644 index 00000000000..971883fa385 --- /dev/null +++ b/target/mips/tcg/sysemu/special_helper.c @@ -0,0 +1,140 @@ +/* + * QEMU MIPS emulation: Special opcode helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "internal.h" + +/* Specials */ +target_ulong helper_di(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + qemu_log("\n"); + } +} + +static void debug_post_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 + && env->active_tc.PC !=3D tb->pc) { + env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &=3D ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} + +static inline void exception_return(CPUMIPSState *env) +{ + debug_pre_eret(env); + if (env->CP0_Status & (1 << CP0St_ERL)) { + mips_env_set_pc(env, env->CP0_ErrorEPC); + env->CP0_Status &=3D ~(1 << CP0St_ERL); + } else { + mips_env_set_pc(env, env->CP0_EPC); + env->CP0_Status &=3D ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(env); +} + +void helper_eret(CPUMIPSState *env) +{ + exception_return(env); + env->CP0_LLAddr =3D 1; + env->lladdr =3D 1; +} + +void helper_eretnc(CPUMIPSState *env) +{ + exception_return(env); +} + +void helper_deret(CPUMIPSState *env) +{ + debug_pre_eret(env); + + env->hflags &=3D ~MIPS_HFLAG_DM; + compute_hflags(env); + + mips_env_set_pc(env, env->CP0_DEPC); + + debug_post_eret(env); +} diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 73ab9571ba6..4da2c577b20 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'special_helper.c', 'tlb_helper.c', )) --=20 2.26.3