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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id 61sm9880095wrm.52.2021.05.02.09.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/fMkH6Q98B3JkGJr/ySJUTql2HNV5/mMZqqV/6nG+Ag=; b=CPS1nV3CNHVwuG1Br3ug1CYOtSfQ1JkVvaNt7Mc+Pazkd/pJQn/t3PqiwyMj5uM5Ot nVRS6qhfeWpejwT56I/Dr0Jn51yWh7UUzPnKLPA/AfNPoxyva5ief5kZvd5qNkX2Ir3C oqIbXGyNTcACUn/zCU8rXknnL2xQ4oNBSawMJlf6H9BCCPS+dKJm+2PbJSNzrglI9/dm 4WAEvxwzfNlS53Dur1x0hDDxuBRCeZMd1HEHvY/QoEW5YTWsT3gV4vRBPHRqja5Zl1W+ 3pyKFBYXu1jU/VSIWHVxc5t2TRoY4/fGNiGZmV4njummbS/eokY+bvjdzq3K9hjiWCdw K1Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/fMkH6Q98B3JkGJr/ySJUTql2HNV5/mMZqqV/6nG+Ag=; b=ijlM2iY4TwxNz6wxjFSPgRLU7tZpY7APE0MzPBWsF44tmP5jA5/wmG/IqA4udEhOPD o4+zmhKpCoUIWe9ZF56SGiJNQQmj86yq09qQmIpWl8nKYK5M/ohEMoKr4osovTo9SbTT C1VxO4EKivZRLPuIkUTNXsXM9ydRBKX/8790OfpT8OrJOkXHaa98BVEDGUuDXYk/W69u v56S3YPzUGoL9g7xzj5ChXutMco6B8DUzSokZwJmrmgOxJ5FYbHdzpaNa8TksxonStHq RsJYnRm9M/sUsx8qetMaiadxFQ3ix5luMfjI5+WmjYXmNwwu+xynn0D+3ixU3/WU80Gl rMHA== X-Gm-Message-State: AOAM5321CrC9saeXDQAhbnYlnLR4SlFYkPT0KjDZwPhC4ZED6SJEkqAe qwA7TU0UROR/wuNOzFRPP5Q= X-Google-Smtp-Source: ABdhPJymbjOlwS51uImZYhTyzujVaJflRv7l0kfzh4iHMM8eO/7RCoGgJ6I8x4VaNQcRCA4UVX1oPA== X-Received: by 2002:a1c:4382:: with SMTP id q124mr16900765wma.63.1619972245140; Sun, 02 May 2021 09:17:25 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 20/36] target/mips: Add simple user-mode mips_cpu_tlb_fill() Date: Sun, 2 May 2021 18:15:22 +0200 Message-Id: <20210502161538.534038-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-15-f4bug@amsat.org> --- target/mips/tcg/user/tlb_helper.c | 36 +++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 10 --------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index 453b9e9b930..b835144b820 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -22,6 +22,42 @@ #include "exec/exec-all.h" #include "internal.h" =20 +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs =3D env_cpu(env); + + env->error_code =3D 0; + if (access_type =3D=3D MMU_INST_FETCH) { + env->error_code |=3D EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCP_AdES; + } else { + cs->exception_index =3D EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + void mips_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D EXCP_NONE; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 78720c4d20a..afc019c80dd 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, env->error_code =3D error_code; } =20 -#if !defined(CONFIG_USER_ONLY) - hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -833,7 +829,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret =3D TLBRET_BADADDR; =20 /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (probe) { return false; } -#endif =20 raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr) { --=20 2.26.3