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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Taylor Simpson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Taylor Simpson Rdd32 =3D add(Rss32, Rtt32, Px4):carry Add with carry Rdd32 =3D sub(Rss32, Rtt32, Px4):carry Sub with carry Test cases in tests/tcg/hexagon/multi_result.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <1617930474-31979-22-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson --- target/hexagon/gen_tcg.h | 37 ++++++++++++ target/hexagon/genptr.c | 11 ++++ tests/tcg/hexagon/multi_result.c | 82 +++++++++++++++++++++++++++ target/hexagon/imported/alu.idef | 15 +++++ target/hexagon/imported/encode_pp.def | 2 + 5 files changed, 147 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index aea0c55564..6bc578dfda 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -237,6 +237,43 @@ tcg_temp_free_i64(tmp); \ } while (0) =20 +/* + * Add or subtract with carry. + * Predicate register is used as an extra input and output. + * r5:4 =3D add(r1:0, r3:2, p1):carry + */ +#define fGEN_TCG_A4_addp_c(SHORTCODE) \ + do { \ + TCGv_i64 carry =3D tcg_temp_new_i64(); \ + TCGv_i64 zero =3D tcg_const_i64(0); \ + tcg_gen_extu_i32_i64(carry, PxV); \ + tcg_gen_andi_i64(carry, carry, 1); \ + tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ + tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \ + tcg_gen_extrl_i64_i32(PxV, carry); \ + gen_8bitsof(PxV, PxV); \ + tcg_temp_free_i64(carry); \ + tcg_temp_free_i64(zero); \ + } while (0) + +/* r5:4 =3D sub(r1:0, r3:2, p1):carry */ +#define fGEN_TCG_A4_subp_c(SHORTCODE) \ + do { \ + TCGv_i64 carry =3D tcg_temp_new_i64(); \ + TCGv_i64 zero =3D tcg_const_i64(0); \ + TCGv_i64 not_RttV =3D tcg_temp_new_i64(); \ + tcg_gen_extu_i32_i64(carry, PxV); \ + tcg_gen_andi_i64(carry, carry, 1); \ + tcg_gen_not_i64(not_RttV, RttV); \ + tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ + tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \ + tcg_gen_extrl_i64_i32(PxV, carry); \ + gen_8bitsof(PxV, PxV); \ + tcg_temp_free_i64(carry); \ + tcg_temp_free_i64(zero); \ + tcg_temp_free_i64(not_RttV); \ + } while (0) + /* * Compare each of the 8 unsigned bytes * The minimum is placed in each byte of the destination. diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9dbebc64b5..333f7d74bf 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -361,5 +361,16 @@ static inline void gen_store_conditional8(CPUHexagonSt= ate *env, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 +static TCGv gen_8bitsof(TCGv result, TCGv value) +{ + TCGv zero =3D tcg_const_tl(0); + TCGv ones =3D tcg_const_tl(0xff); + tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero); + tcg_temp_free(zero); + tcg_temp_free(ones); + + return result; +} + #include "tcg_funcs_generated.c.inc" #include "tcg_func_table_generated.c.inc" diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_res= ult.c index 95d99a0c90..52997b3128 100644 --- a/tests/tcg/hexagon/multi_result.c +++ b/tests/tcg/hexagon/multi_result.c @@ -85,6 +85,38 @@ static long long vminub(long long Rtt, long long Rss, return result; } =20 +static long long add_carry(long long Rss, long long Rtt, + int pred_in, int *pred_result) +{ + long long result; + int predval =3D pred_in; + + asm volatile("p0 =3D %1\n\t" + "%0 =3D add(%2, %3, p0):carry\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(result), "+r"(predval) + : "r"(Rss), "r"(Rtt) + : "p0"); + *pred_result =3D predval; + return result; +} + +static long long sub_carry(long long Rss, long long Rtt, + int pred_in, int *pred_result) +{ + long long result; + int predval =3D pred_in; + + asm volatile("p0 =3D !cmp.eq(%1, #0)\n\t" + "%0 =3D sub(%2, %3, p0):carry\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(result), "+r"(predval) + : "r"(Rss), "r"(Rtt) + : "p0"); + *pred_result =3D predval; + return result; +} + int err; =20 static void check_ll(long long val, long long expect) @@ -188,12 +220,62 @@ static void test_vminub() check_p(pred_result, 0xaa); } =20 +static void test_add_carry() +{ + long long res64; + int pred_result; + + res64 =3D add_carry(0x0000000000000000LL, + 0xffffffffffffffffLL, + 1, &pred_result); + check_ll(res64, 0x0000000000000000LL); + check_p(pred_result, 0xff); + + res64 =3D add_carry(0x0000000100000000LL, + 0xffffffffffffffffLL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); + + res64 =3D add_carry(0x0000000100000000LL, + 0xffffffffffffffffLL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); +} + +static void test_sub_carry() +{ + long long res64; + int pred_result; + + res64 =3D sub_carry(0x0000000000000000LL, + 0x0000000000000000LL, + 1, &pred_result); + check_ll(res64, 0x0000000000000000LL); + check_p(pred_result, 0xff); + + res64 =3D sub_carry(0x0000000100000000LL, + 0x0000000000000000LL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); + + res64 =3D sub_carry(0x0000000100000000LL, + 0x0000000000000000LL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); +} + int main() { test_sfrecipa(); test_sfinvsqrta(); test_vacsh(); test_vminub(); + test_add_carry(); + test_sub_carry(); =20 puts(err ? "FAIL" : "PASS"); return err; diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu= .idef index f0c9bb47ec..58477ae40a 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -153,6 +153,21 @@ Q6INSN(A2_subp,"Rdd32=3Dsub(Rtt32,Rss32)",ATTRIBS(), "Sub", { RddV=3DRttV-RssV;}) =20 +/* 64-bit with carry */ + +Q6INSN(A4_addp_c,"Rdd32=3Dadd(Rss32,Rtt32,Px4):carry",ATTRIBS(),"Add with = Carry", +{ + RddV =3D RssV + RttV + fLSBOLD(PxV); + PxV =3D f8BITSOF(fCARRY_FROM_ADD(RssV,RttV,fLSBOLD(PxV))); +}) + +Q6INSN(A4_subp_c,"Rdd32=3Dsub(Rss32,Rtt32,Px4):carry",ATTRIBS(),"Sub with = Carry", +{ + RddV =3D RssV + ~RttV + fLSBOLD(PxV); + PxV =3D f8BITSOF(fCARRY_FROM_ADD(RssV,~RttV,fLSBOLD(PxV))); +}) + + /* NEG and ABS */ =20 Q6INSN(A2_negsat,"Rd32=3Dneg(Rs32):sat",ATTRIBS(), diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index 46193984c5..514c2404ce 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -1749,6 +1749,8 @@ SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-= ","ddddd") DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rd= d=3D(Rss,Rtt,Pu)") SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd") SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd") +SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd") +SH_RRR_ENC(A4_subp_c, "0010","111","-","-xx","ddddd") =20 =20 DEF_FIELDROW_DESC32(ICLASS_S3op" 0011 -------- PP------ --------","[#3] Rd= d=3D(Rss,Rt)") --=20 2.25.1