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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Taylor Simpson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Taylor Simpson Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <1617930474-31979-11-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson --- target/hexagon/cpu.c | 5 ++++ target/hexagon/op_helper.c | 47 ---------------------------------- fpu/softfloat-specialize.c.inc | 3 +++ 3 files changed, 8 insertions(+), 47 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f044506d0f..ff44fd6637 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "qapi/error.h" #include "hw/qdev-properties.h" +#include "fpu/softfloat-helpers.h" =20 static void hexagon_v67_cpu_init(Object *obj) { @@ -205,8 +206,12 @@ static void hexagon_cpu_reset(DeviceState *dev) CPUState *cs =3D CPU(dev); HexagonCPU *cpu =3D HEXAGON_CPU(cs); HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(cpu); + CPUHexagonState *env =3D &cpu->env; =20 mcc->parent_reset(dev); + + set_default_nan_mode(1, &env->fp_status); + set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); } =20 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 1d91fa2743..478421d147 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -296,26 +296,6 @@ int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, = int32_t M, int32_t CS) return new_ptr; } =20 -/* - * Hexagon FP operations return ~0 instead of NaN - * The hex_check_sfnan/hex_check_dfnan functions perform this check - */ -static float32 hex_check_sfnan(float32 x) -{ - if (float32_is_any_nan(x)) { - return make_float32(0xFFFFFFFFU); - } - return x; -} - -static float64 hex_check_dfnan(float64 x) -{ - if (float64_is_any_nan(x)) { - return make_float64(0xFFFFFFFFFFFFFFFFULL); - } - return x; -} - /* * mem_noshuf * Section 5.5 of the Hexagon V67 Programmer's Reference Manual @@ -373,7 +353,6 @@ float64 HELPER(conv_sf2df)(CPUHexagonState *env, float3= 2 RsV) float64 out_f64; arch_fpop_start(env); out_f64 =3D float32_to_float64(RsV, &env->fp_status); - out_f64 =3D hex_check_dfnan(out_f64); arch_fpop_end(env); return out_f64; } @@ -383,7 +362,6 @@ float32 HELPER(conv_df2sf)(CPUHexagonState *env, float6= 4 RssV) float32 out_f32; arch_fpop_start(env); out_f32 =3D float64_to_float32(RssV, &env->fp_status); - out_f32 =3D hex_check_sfnan(out_f32); arch_fpop_end(env); return out_f32; } @@ -393,7 +371,6 @@ float32 HELPER(conv_uw2sf)(CPUHexagonState *env, int32_= t RsV) float32 RdV; arch_fpop_start(env); RdV =3D uint32_to_float32(RsV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -403,7 +380,6 @@ float64 HELPER(conv_uw2df)(CPUHexagonState *env, int32_= t RsV) float64 RddV; arch_fpop_start(env); RddV =3D uint32_to_float64(RsV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -413,7 +389,6 @@ float32 HELPER(conv_w2sf)(CPUHexagonState *env, int32_t= RsV) float32 RdV; arch_fpop_start(env); RdV =3D int32_to_float32(RsV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -423,7 +398,6 @@ float64 HELPER(conv_w2df)(CPUHexagonState *env, int32_t= RsV) float64 RddV; arch_fpop_start(env); RddV =3D int32_to_float64(RsV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -433,7 +407,6 @@ float32 HELPER(conv_ud2sf)(CPUHexagonState *env, int64_= t RssV) float32 RdV; arch_fpop_start(env); RdV =3D uint64_to_float32(RssV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -443,7 +416,6 @@ float64 HELPER(conv_ud2df)(CPUHexagonState *env, int64_= t RssV) float64 RddV; arch_fpop_start(env); RddV =3D uint64_to_float64(RssV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -453,7 +425,6 @@ float32 HELPER(conv_d2sf)(CPUHexagonState *env, int64_t= RssV) float32 RdV; arch_fpop_start(env); RdV =3D int64_to_float32(RssV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -463,7 +434,6 @@ float64 HELPER(conv_d2df)(CPUHexagonState *env, int64_t= RssV) float64 RddV; arch_fpop_start(env); RddV =3D int64_to_float64(RssV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -625,7 +595,6 @@ float32 HELPER(sfadd)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_add(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -635,7 +604,6 @@ float32 HELPER(sfsub)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_sub(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -687,7 +655,6 @@ float32 HELPER(sfmax)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_maxnum(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -697,7 +664,6 @@ float32 HELPER(sfmin)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_minnum(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -764,7 +730,6 @@ float64 HELPER(dfadd)(CPUHexagonState *env, float64 Rss= V, float64 RttV) float64 RddV; arch_fpop_start(env); RddV =3D float64_add(RssV, RttV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -774,7 +739,6 @@ float64 HELPER(dfsub)(CPUHexagonState *env, float64 Rss= V, float64 RttV) float64 RddV; arch_fpop_start(env); RddV =3D float64_sub(RssV, RttV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -787,7 +751,6 @@ float64 HELPER(dfmax)(CPUHexagonState *env, float64 Rss= V, float64 RttV) if (float64_is_any_nan(RssV) || float64_is_any_nan(RttV)) { float_raise(float_flag_invalid, &env->fp_status); } - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -800,7 +763,6 @@ float64 HELPER(dfmin)(CPUHexagonState *env, float64 Rss= V, float64 RttV) if (float64_is_any_nan(RssV) || float64_is_any_nan(RttV)) { float_raise(float_flag_invalid, &env->fp_status); } - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -876,7 +838,6 @@ float32 HELPER(sfmpy)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D internal_mpyf(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -886,7 +847,6 @@ float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV, { arch_fpop_start(env); RxV =3D internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); - RxV =3D hex_check_sfnan(RxV); arch_fpop_end(env); return RxV; } @@ -918,7 +878,6 @@ float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 = RxV, RxV =3D check_nan(RxV, RsV, &env->fp_status); RxV =3D check_nan(RxV, RtV, &env->fp_status); tmp =3D internal_fmafx(RsV, RtV, RxV, fSXTN(8, 64, PuV), &env->fp_stat= us); - tmp =3D hex_check_sfnan(tmp); if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { RxV =3D tmp; } @@ -933,7 +892,6 @@ float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, arch_fpop_start(env); neg_RsV =3D float32_sub(float32_zero, RsV, &env->fp_status); RxV =3D internal_fmafx(neg_RsV, RtV, RxV, 0, &env->fp_status); - RxV =3D hex_check_sfnan(RxV); arch_fpop_end(env); return RxV; } @@ -964,7 +922,6 @@ float32 HELPER(sffma_lib)(CPUHexagonState *env, float32= RxV, RxV =3D check_nan(RxV, RsV, &env->fp_status); RxV =3D check_nan(RxV, RtV, &env->fp_status); tmp =3D internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); - tmp =3D hex_check_sfnan(tmp); if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { RxV =3D tmp; } @@ -999,7 +956,6 @@ float32 HELPER(sffms_lib)(CPUHexagonState *env, float32= RxV, RxV =3D check_nan(RxV, RtV, &env->fp_status); float32 minus_RsV =3D float32_sub(float32_zero, RsV, &env->fp_status); tmp =3D internal_fmafx(minus_RsV, RtV, RxV, 0, &env->fp_status); - tmp =3D hex_check_sfnan(tmp); if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { RxV =3D tmp; } @@ -1023,13 +979,11 @@ float64 HELPER(dfmpyfix)(CPUHexagonState *env, float= 64 RssV, float64 RttV) float64_is_normal(RttV)) { RddV =3D float64_mul(RssV, make_float64(0x4330000000000000), &env->fp_status); - RddV =3D hex_check_dfnan(RddV); } else if (float64_is_denormal(RttV) && (float64_getexp(RssV) >=3D 512) && float64_is_normal(RssV)) { RddV =3D float64_mul(RssV, make_float64(0x3cb0000000000000), &env->fp_status); - RddV =3D hex_check_dfnan(RddV); } else { RddV =3D RssV; } @@ -1042,7 +996,6 @@ float64 HELPER(dfmpyhh)(CPUHexagonState *env, float64 = RxxV, { arch_fpop_start(env); RxxV =3D internal_mpyhh(RssV, RttV, RxxV, &env->fp_status); - RxxV =3D hex_check_dfnan(RxxV); arch_fpop_end(env); return RxxV; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c2f87addb2..9ea318f3e2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -145,6 +145,9 @@ static FloatParts parts_default_nan(float_status *statu= s) #elif defined(TARGET_HPPA) /* snan_bit_is_one, set msb-1. */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#elif defined(TARGET_HEXAGON) + sign =3D 1; + frac =3D ~0ULL; #else /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. I cannot find documentation --=20 2.25.1