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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" On Windows with glib <2.50, g_poll is redefined to use the variant defined in util/oslib-win32.c. Use the same name in the declaration and definition for ease of grepping. Signed-off-by: Paolo Bonzini --- util/oslib-win32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/oslib-win32.c b/util/oslib-win32.c index f68b8012bb..13418f68c0 100644 --- a/util/oslib-win32.c +++ b/util/oslib-win32.c @@ -472,7 +472,7 @@ static int poll_rest(gboolean poll_msgs, HANDLE *handle= s, gint nhandles, return 0; } =20 -gint g_poll(GPollFD *fds, guint nfds, gint timeout) +gint g_poll_fixed(GPollFD *fds, guint nfds, gint timeout) { HANDLE handles[MAXIMUM_WAIT_OBJECTS]; gboolean poll_msgs =3D FALSE; --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1619861570; cv=none; d=zohomail.com; s=zohoarc; b=iYcIbO81tkgua0M/ATntPu76jVezpR6Kvnfi0TtrsHyWywH/JgCQjEMAEhZFUXxkQbBZL+sJ9EU3T1AIYh7Kc4iR0qV+36TlVkoRN99dwBxx2J+rbwG5bXz6q7UWxzQ2NuMJ/L2KAh52VnwEa8ZE20OVjE23lVhGk2+AyMVZYUk= ARC-Message-Signature: i=1; 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Sat, 01 May 2021 02:30:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 02/10] Add NVMM accelerator: configure and build logic Date: Sat, 1 May 2021 11:30:18 +0200 Message-Id: <20210501093026.189429-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210501093026.189429-1-pbonzini@redhat.com> References: <20210501093026.189429-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=paolo.bonzini@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kamil Rytarowski , Reinoud Zandijk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Reinoud Zandijk Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk Message-Id: <20210402202535.11550-2-reinoud@NetBSD.org> Signed-off-by: Paolo Bonzini --- accel/Kconfig | 3 +++ configure | 8 +++++++- meson.build | 14 ++++++++++++++ meson_options.txt | 2 ++ qemu-options.hx | 8 ++++---- 5 files changed, 30 insertions(+), 5 deletions(-) diff --git a/accel/Kconfig b/accel/Kconfig index 461104c771..8bdedb7d15 100644 --- a/accel/Kconfig +++ b/accel/Kconfig @@ -1,6 +1,9 @@ config WHPX bool =20 +config NVMM + bool + config HAX bool =20 diff --git a/configure b/configure index 4f374b4889..268460d63d 100755 --- a/configure +++ b/configure @@ -352,6 +352,7 @@ kvm=3D"auto" hax=3D"auto" hvf=3D"auto" whpx=3D"auto" +nvmm=3D"auto" rdma=3D"$default_feature" pvrdma=3D"$default_feature" gprof=3D"no" @@ -1107,6 +1108,10 @@ for opt do ;; --enable-hvf) hvf=3D"enabled" ;; + --disable-nvmm) nvmm=3D"disabled" + ;; + --enable-nvmm) nvmm=3D"enabled" + ;; --disable-whpx) whpx=3D"disabled" ;; --enable-whpx) whpx=3D"enabled" @@ -1848,6 +1853,7 @@ disabled with --disable-FEATURE, default is enabled i= f available kvm KVM acceleration support hax HAX acceleration support hvf Hypervisor.framework acceleration support + nvmm NVMM acceleration support whpx Windows Hypervisor Platform acceleration support rdma Enable RDMA-based migration pvrdma Enable PVRDMA support @@ -6410,7 +6416,7 @@ NINJA=3D$ninja $meson setup \ -Db_coverage=3D$(if test "$gcov" =3D yes; then echo true; else ech= o false; fi) \ -Db_lto=3D$lto -Dcfi=3D$cfi -Dcfi_debug=3D$cfi_debug \ -Dmalloc=3D$malloc -Dmalloc_trim=3D$malloc_trim -Dsparse=3D$sparse= \ - -Dkvm=3D$kvm -Dhax=3D$hax -Dwhpx=3D$whpx -Dhvf=3D$hvf \ + -Dkvm=3D$kvm -Dhax=3D$hax -Dwhpx=3D$whpx -Dhvf=3D$hvf -Dnvmm=3D$nv= mm \ -Dxen=3D$xen -Dxen_pci_passthrough=3D$xen_pci_passthrough -Dtcg=3D= $tcg \ -Dcocoa=3D$cocoa -Dgtk=3D$gtk -Dmpath=3D$mpath -Dsdl=3D$sdl -Dsdl_= image=3D$sdl_image \ -Dvnc=3D$vnc -Dvnc_sasl=3D$vnc_sasl -Dvnc_jpeg=3D$vnc_jpeg -Dvnc_p= ng=3D$vnc_png \ diff --git a/meson.build b/meson.build index c6f4b0cf5e..14dd3fe068 100644 --- a/meson.build +++ b/meson.build @@ -87,6 +87,7 @@ if cpu in ['x86', 'x86_64'] accelerator_targets +=3D { 'CONFIG_HAX': ['i386-softmmu', 'x86_64-softmmu'], 'CONFIG_HVF': ['x86_64-softmmu'], + 'CONFIG_NVMM': ['i386-softmmu', 'x86_64-softmmu'], 'CONFIG_WHPX': ['i386-softmmu', 'x86_64-softmmu'], } endif @@ -170,6 +171,7 @@ version_res =3D [] coref =3D [] iokit =3D [] emulator_link_args =3D [] +nvmm =3Dnot_found hvf =3D not_found if targetos =3D=3D 'windows' socket =3D cc.find_library('ws2_32') @@ -227,6 +229,14 @@ if not get_option('hax').disabled() accelerators +=3D 'CONFIG_HAX' endif endif +if targetos =3D=3D 'netbsd' + if cc.has_header('nvmm.h', required: get_option('nvmm')) + nvmm =3D cc.find_library('nvmm', required: get_option('nvmm')) + endif + if nvmm.found() + accelerators +=3D 'CONFIG_NVMM' + endif +endif =20 tcg_arch =3D config_host['ARCH'] if not get_option('tcg').disabled() @@ -271,6 +281,9 @@ endif if 'CONFIG_HVF' not in accelerators and get_option('hvf').enabled() error('HVF not available on this platform') endif +if 'CONFIG_NVMM' not in accelerators and get_option('nvmm').enabled() + error('NVMM not available on this platform') +endif if 'CONFIG_WHPX' not in accelerators and get_option('whpx').enabled() error('WHPX not available on this platform') endif @@ -2576,6 +2589,7 @@ if have_system summary_info +=3D {'HAX support': config_all.has_key('CONFIG_HAX')} summary_info +=3D {'HVF support': config_all.has_key('CONFIG_HVF')} summary_info +=3D {'WHPX support': config_all.has_key('CONFIG_WHPX'= )} + summary_info +=3D {'NVMM support': config_all.has_key('CONFIG_NVMM'= )} summary_info +=3D {'Xen support': config_host.has_key('CONFIG_XEN_= BACKEND')} if config_host.has_key('CONFIG_XEN_BACKEND') summary_info +=3D {'xen ctrl version': config_host['CONFIG_XEN_CTRL_I= NTERFACE_VERSION']} diff --git a/meson_options.txt b/meson_options.txt index 9734019995..91034420a1 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -33,6 +33,8 @@ option('whpx', type: 'feature', value: 'auto', description: 'WHPX acceleration support') option('hvf', type: 'feature', value: 'auto', description: 'HVF acceleration support') +option('nvmm', type: 'feature', value: 'auto', + description: 'NVMM acceleration support') option('xen', type: 'feature', value: 'auto', description: 'Xen backend support') option('xen_pci_passthrough', type: 'feature', value: 'auto', diff --git a/qemu-options.hx b/qemu-options.hx index fd21002bd6..dadf11fae9 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -26,7 +26,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ "-machine [type=3D]name[,prop[=3Dvalue][,...]]\n" " selects emulated machine ('-machine help' for list)\n" " property accel=3Daccel1[:accel2[:...]] selects accele= rator\n" - " supported accelerators are kvm, xen, hax, hvf, whpx o= r tcg (default: tcg)\n" + " supported accelerators are kvm, xen, hax, hvf, nvmm, = whpx or tcg (default: tcg)\n" " vmport=3Don|off|auto controls emulation of vmport (de= fault: auto)\n" " dump-guest-core=3Don|off include guest memory in a co= re dump (default=3Don)\n" " mem-merge=3Don|off controls memory merge support (def= ault: on)\n" @@ -58,7 +58,7 @@ SRST =20 ``accel=3Daccels1[:accels2[:...]]`` This is used to enable an accelerator. Depending on the target - architecture, kvm, xen, hax, hvf, whpx or tcg can be available. + architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be availab= le. By default, tcg is used. If there is more than one accelerator specified, the next one is used if the previous one fails to initialize. @@ -135,7 +135,7 @@ ERST =20 DEF("accel", HAS_ARG, QEMU_OPTION_accel, "-accel [accel=3D]accelerator[,prop[=3Dvalue][,...]]\n" - " select accelerator (kvm, xen, hax, hvf, whpx or tcg; = use 'help' for a list)\n" + " select accelerator (kvm, xen, hax, hvf, nvmm, whpx or= tcg; use 'help' for a list)\n" " igd-passthru=3Don|off (enable Xen integrated Intel gr= aphics passthrough, default=3Doff)\n" " kernel-irqchip=3Don|off|split controls accelerated ir= qchip support (default=3Don)\n" " kvm-shadow-mem=3Dsize of KVM shadow MMU in bytes\n" @@ -145,7 +145,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, SRST ``-accel name[,prop=3Dvalue[,...]]`` This is used to enable an accelerator. Depending on the target - architecture, kvm, xen, hax, hvf, whpx or tcg can be available. By + architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available. = By default, tcg is used. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kamil Rytarowski , Reinoud Zandijk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Reinoud Zandijk Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk Message-Id: <20210402202535.11550-3-reinoud@NetBSD.org> Signed-off-by: Paolo Bonzini --- target/i386/meson.build | 1 + target/i386/nvmm/meson.build | 8 + target/i386/nvmm/nvmm-accel-ops.c | 111 +++ target/i386/nvmm/nvmm-accel-ops.h | 24 + target/i386/nvmm/nvmm-all.c | 1226 +++++++++++++++++++++++++++++ 5 files changed, 1370 insertions(+) create mode 100644 target/i386/nvmm/meson.build create mode 100644 target/i386/nvmm/nvmm-accel-ops.c create mode 100644 target/i386/nvmm/nvmm-accel-ops.h create mode 100644 target/i386/nvmm/nvmm-all.c diff --git a/target/i386/meson.build b/target/i386/meson.build index c4bf20b319..b0c04f3d89 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -19,6 +19,7 @@ i386_softmmu_ss.add(files( subdir('kvm') subdir('hax') subdir('whpx') +subdir('nvmm') subdir('hvf') subdir('tcg') =20 diff --git a/target/i386/nvmm/meson.build b/target/i386/nvmm/meson.build new file mode 100644 index 0000000000..733e334083 --- /dev/null +++ b/target/i386/nvmm/meson.build @@ -0,0 +1,8 @@ +i386_softmmu_ss.add(when: 'CONFIG_NVMM', if_true: + files( + 'nvmm-all.c', + 'nvmm-accel-ops.c', + ) +) + +i386_softmmu_ss.add(when: 'CONFIG_NVMM', if_true: nvmm) diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-acce= l-ops.c new file mode 100644 index 0000000000..f788f75289 --- /dev/null +++ b/target/i386/nvmm/nvmm-accel-ops.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2018-2019 Maxime Villard, All rights reserved. + * + * NetBSD Virtual Machine Monitor (NVMM) accelerator for QEMU. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "sysemu/kvm_int.h" +#include "qemu/main-loop.h" +#include "sysemu/cpus.h" +#include "qemu/guest-random.h" + +#include "sysemu/nvmm.h" +#include "nvmm-accel-ops.h" + +static void *qemu_nvmm_cpu_thread_fn(void *arg) +{ + CPUState *cpu =3D arg; + int r; + + assert(nvmm_enabled()); + + rcu_register_thread(); + + qemu_mutex_lock_iothread(); + qemu_thread_get_self(cpu->thread); + cpu->thread_id =3D qemu_get_thread_id(); + current_cpu =3D cpu; + + r =3D nvmm_init_vcpu(cpu); + if (r < 0) { + fprintf(stderr, "nvmm_init_vcpu failed: %s\n", strerror(-r)); + exit(1); + } + + /* signal CPU creation */ + cpu_thread_signal_created(cpu); + qemu_guest_random_seed_thread_part2(cpu->random_seed); + + do { + if (cpu_can_run(cpu)) { + r =3D nvmm_vcpu_exec(cpu); + if (r =3D=3D EXCP_DEBUG) { + cpu_handle_guest_debug(cpu); + } + } + while (cpu_thread_is_idle(cpu)) { + qemu_cond_wait_iothread(cpu->halt_cond); + } + qemu_wait_io_event_common(cpu); + } while (!cpu->unplug || cpu_can_run(cpu)); + + nvmm_destroy_vcpu(cpu); + cpu_thread_signal_destroyed(cpu); + qemu_mutex_unlock_iothread(); + rcu_unregister_thread(); + return NULL; +} + +static void nvmm_start_vcpu_thread(CPUState *cpu) +{ + char thread_name[VCPU_THREAD_NAME_SIZE]; + + cpu->thread =3D g_malloc0(sizeof(QemuThread)); + cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/NVMM", + cpu->cpu_index); + qemu_thread_create(cpu->thread, thread_name, qemu_nvmm_cpu_thread_fn, + cpu, QEMU_THREAD_JOINABLE); +} + +/* + * Abort the call to run the virtual processor by another thread, and to + * return the control to that thread. + */ +static void nvmm_kick_vcpu_thread(CPUState *cpu) +{ + cpu->exit_request =3D 1; + cpus_kick_thread(cpu); +} + +static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D nvmm_start_vcpu_thread; + ops->kick_vcpu_thread =3D nvmm_kick_vcpu_thread; + + ops->synchronize_post_reset =3D nvmm_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D nvmm_cpu_synchronize_post_init; + ops->synchronize_state =3D nvmm_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D nvmm_cpu_synchronize_pre_loadvm; +} + +static const TypeInfo nvmm_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("nvmm"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D nvmm_accel_ops_class_init, + .abstract =3D true, +}; + +static void nvmm_accel_ops_register_types(void) +{ + type_register_static(&nvmm_accel_ops_type); +} +type_init(nvmm_accel_ops_register_types); diff --git a/target/i386/nvmm/nvmm-accel-ops.h b/target/i386/nvmm/nvmm-acce= l-ops.h new file mode 100644 index 0000000000..43e24adcaf --- /dev/null +++ b/target/i386/nvmm/nvmm-accel-ops.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018-2019 Maxime Villard, All rights reserved. + * + * NetBSD Virtual Machine Monitor (NVMM) accelerator for QEMU. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef NVMM_CPUS_H +#define NVMM_CPUS_H + +#include "sysemu/cpus.h" + +int nvmm_init_vcpu(CPUState *cpu); +int nvmm_vcpu_exec(CPUState *cpu); +void nvmm_destroy_vcpu(CPUState *cpu); + +void nvmm_cpu_synchronize_state(CPUState *cpu); +void nvmm_cpu_synchronize_post_reset(CPUState *cpu); +void nvmm_cpu_synchronize_post_init(CPUState *cpu); +void nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu); + +#endif /* NVMM_CPUS_H */ diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c new file mode 100644 index 0000000000..dfa690d65d --- /dev/null +++ b/target/i386/nvmm/nvmm-all.c @@ -0,0 +1,1226 @@ +/* + * Copyright (c) 2018-2019 Maxime Villard, All rights reserved. + * + * NetBSD Virtual Machine Monitor (NVMM) accelerator for QEMU. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/address-spaces.h" +#include "exec/ioport.h" +#include "qemu-common.h" +#include "qemu/accel.h" +#include "sysemu/nvmm.h" +#include "sysemu/cpus.h" +#include "sysemu/runstate.h" +#include "qemu/main-loop.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qemu/queue.h" +#include "migration/blocker.h" +#include "strings.h" + +#include "nvmm-accel-ops.h" + +#include + +struct qemu_vcpu { + struct nvmm_vcpu vcpu; + uint8_t tpr; + bool stop; + + /* Window-exiting for INTs/NMIs. */ + bool int_window_exit; + bool nmi_window_exit; + + /* The guest is in an interrupt shadow (POP SS, etc). */ + bool int_shadow; +}; + +struct qemu_machine { + struct nvmm_capability cap; + struct nvmm_machine mach; +}; + +/* -----------------------------------------------------------------------= --- */ + +static bool nvmm_allowed; +static struct qemu_machine qemu_mach; + +static struct qemu_vcpu * +get_qemu_vcpu(CPUState *cpu) +{ + return (struct qemu_vcpu *)cpu->hax_vcpu; +} + +static struct nvmm_machine * +get_nvmm_mach(void) +{ + return &qemu_mach.mach; +} + +/* -----------------------------------------------------------------------= --- */ + +static void +nvmm_set_segment(struct nvmm_x64_state_seg *nseg, const SegmentCache *qseg) +{ + uint32_t attrib =3D qseg->flags; + + nseg->selector =3D qseg->selector; + nseg->limit =3D qseg->limit; + nseg->base =3D qseg->base; + nseg->attrib.type =3D __SHIFTOUT(attrib, DESC_TYPE_MASK); + nseg->attrib.s =3D __SHIFTOUT(attrib, DESC_S_MASK); + nseg->attrib.dpl =3D __SHIFTOUT(attrib, DESC_DPL_MASK); + nseg->attrib.p =3D __SHIFTOUT(attrib, DESC_P_MASK); + nseg->attrib.avl =3D __SHIFTOUT(attrib, DESC_AVL_MASK); + nseg->attrib.l =3D __SHIFTOUT(attrib, DESC_L_MASK); + nseg->attrib.def =3D __SHIFTOUT(attrib, DESC_B_MASK); + nseg->attrib.g =3D __SHIFTOUT(attrib, DESC_G_MASK); +} + +static void +nvmm_set_registers(CPUState *cpu) +{ + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + struct nvmm_machine *mach =3D get_nvmm_mach(); + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + struct nvmm_x64_state *state =3D vcpu->state; + uint64_t bitmap; + size_t i; + int ret; + + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + + /* GPRs. */ + state->gprs[NVMM_X64_GPR_RAX] =3D env->regs[R_EAX]; + state->gprs[NVMM_X64_GPR_RCX] =3D env->regs[R_ECX]; + state->gprs[NVMM_X64_GPR_RDX] =3D env->regs[R_EDX]; + state->gprs[NVMM_X64_GPR_RBX] =3D env->regs[R_EBX]; + state->gprs[NVMM_X64_GPR_RSP] =3D env->regs[R_ESP]; + state->gprs[NVMM_X64_GPR_RBP] =3D env->regs[R_EBP]; + state->gprs[NVMM_X64_GPR_RSI] =3D env->regs[R_ESI]; + state->gprs[NVMM_X64_GPR_RDI] =3D env->regs[R_EDI]; +#ifdef TARGET_X86_64 + state->gprs[NVMM_X64_GPR_R8] =3D env->regs[R_R8]; + state->gprs[NVMM_X64_GPR_R9] =3D env->regs[R_R9]; + state->gprs[NVMM_X64_GPR_R10] =3D env->regs[R_R10]; + state->gprs[NVMM_X64_GPR_R11] =3D env->regs[R_R11]; + state->gprs[NVMM_X64_GPR_R12] =3D env->regs[R_R12]; + state->gprs[NVMM_X64_GPR_R13] =3D env->regs[R_R13]; + state->gprs[NVMM_X64_GPR_R14] =3D env->regs[R_R14]; + state->gprs[NVMM_X64_GPR_R15] =3D env->regs[R_R15]; +#endif + + /* RIP and RFLAGS. */ + state->gprs[NVMM_X64_GPR_RIP] =3D env->eip; + state->gprs[NVMM_X64_GPR_RFLAGS] =3D env->eflags; + + /* Segments. */ + nvmm_set_segment(&state->segs[NVMM_X64_SEG_CS], &env->segs[R_CS]); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_DS], &env->segs[R_DS]); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_ES], &env->segs[R_ES]); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_FS], &env->segs[R_FS]); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_GS], &env->segs[R_GS]); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_SS], &env->segs[R_SS]); + + /* Special segments. */ + nvmm_set_segment(&state->segs[NVMM_X64_SEG_GDT], &env->gdt); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_LDT], &env->ldt); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_TR], &env->tr); + nvmm_set_segment(&state->segs[NVMM_X64_SEG_IDT], &env->idt); + + /* Control registers. */ + state->crs[NVMM_X64_CR_CR0] =3D env->cr[0]; + state->crs[NVMM_X64_CR_CR2] =3D env->cr[2]; + state->crs[NVMM_X64_CR_CR3] =3D env->cr[3]; + state->crs[NVMM_X64_CR_CR4] =3D env->cr[4]; + state->crs[NVMM_X64_CR_CR8] =3D qcpu->tpr; + state->crs[NVMM_X64_CR_XCR0] =3D env->xcr0; + + /* Debug registers. */ + state->drs[NVMM_X64_DR_DR0] =3D env->dr[0]; + state->drs[NVMM_X64_DR_DR1] =3D env->dr[1]; + state->drs[NVMM_X64_DR_DR2] =3D env->dr[2]; + state->drs[NVMM_X64_DR_DR3] =3D env->dr[3]; + state->drs[NVMM_X64_DR_DR6] =3D env->dr[6]; + state->drs[NVMM_X64_DR_DR7] =3D env->dr[7]; + + /* FPU. */ + state->fpu.fx_cw =3D env->fpuc; + state->fpu.fx_sw =3D (env->fpus & ~0x3800) | ((env->fpstt & 0x7) << 11= ); + state->fpu.fx_tw =3D 0; + for (i =3D 0; i < 8; i++) { + state->fpu.fx_tw |=3D (!env->fptags[i]) << i; + } + state->fpu.fx_opcode =3D env->fpop; + state->fpu.fx_ip.fa_64 =3D env->fpip; + state->fpu.fx_dp.fa_64 =3D env->fpdp; + state->fpu.fx_mxcsr =3D env->mxcsr; + state->fpu.fx_mxcsr_mask =3D 0x0000FFFF; + assert(sizeof(state->fpu.fx_87_ac) =3D=3D sizeof(env->fpregs)); + memcpy(state->fpu.fx_87_ac, env->fpregs, sizeof(env->fpregs)); + for (i =3D 0; i < CPU_NB_REGS; i++) { + memcpy(&state->fpu.fx_xmm[i].xmm_bytes[0], + &env->xmm_regs[i].ZMM_Q(0), 8); + memcpy(&state->fpu.fx_xmm[i].xmm_bytes[8], + &env->xmm_regs[i].ZMM_Q(1), 8); + } + + /* MSRs. */ + state->msrs[NVMM_X64_MSR_EFER] =3D env->efer; + state->msrs[NVMM_X64_MSR_STAR] =3D env->star; +#ifdef TARGET_X86_64 + state->msrs[NVMM_X64_MSR_LSTAR] =3D env->lstar; + state->msrs[NVMM_X64_MSR_CSTAR] =3D env->cstar; + state->msrs[NVMM_X64_MSR_SFMASK] =3D env->fmask; + state->msrs[NVMM_X64_MSR_KERNELGSBASE] =3D env->kernelgsbase; +#endif + state->msrs[NVMM_X64_MSR_SYSENTER_CS] =3D env->sysenter_cs; + state->msrs[NVMM_X64_MSR_SYSENTER_ESP] =3D env->sysenter_esp; + state->msrs[NVMM_X64_MSR_SYSENTER_EIP] =3D env->sysenter_eip; + state->msrs[NVMM_X64_MSR_PAT] =3D env->pat; + state->msrs[NVMM_X64_MSR_TSC] =3D env->tsc; + + bitmap =3D + NVMM_X64_STATE_SEGS | + NVMM_X64_STATE_GPRS | + NVMM_X64_STATE_CRS | + NVMM_X64_STATE_DRS | + NVMM_X64_STATE_MSRS | + NVMM_X64_STATE_FPU; + + ret =3D nvmm_vcpu_setstate(mach, vcpu, bitmap); + if (ret =3D=3D -1) { + error_report("NVMM: Failed to set virtual processor context," + " error=3D%d", errno); + } +} + +static void +nvmm_get_segment(SegmentCache *qseg, const struct nvmm_x64_state_seg *nseg) +{ + qseg->selector =3D nseg->selector; + qseg->limit =3D nseg->limit; + qseg->base =3D nseg->base; + + qseg->flags =3D + __SHIFTIN((uint32_t)nseg->attrib.type, DESC_TYPE_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.s, DESC_S_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.dpl, DESC_DPL_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.p, DESC_P_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.avl, DESC_AVL_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.l, DESC_L_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.def, DESC_B_MASK) | + __SHIFTIN((uint32_t)nseg->attrib.g, DESC_G_MASK); +} + +static void +nvmm_get_registers(CPUState *cpu) +{ + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + struct nvmm_machine *mach =3D get_nvmm_mach(); + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + X86CPU *x86_cpu =3D X86_CPU(cpu); + struct nvmm_x64_state *state =3D vcpu->state; + uint64_t bitmap, tpr; + size_t i; + int ret; + + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + + bitmap =3D + NVMM_X64_STATE_SEGS | + NVMM_X64_STATE_GPRS | + NVMM_X64_STATE_CRS | + NVMM_X64_STATE_DRS | + NVMM_X64_STATE_MSRS | + NVMM_X64_STATE_FPU; + + ret =3D nvmm_vcpu_getstate(mach, vcpu, bitmap); + if (ret =3D=3D -1) { + error_report("NVMM: Failed to get virtual processor context," + " error=3D%d", errno); + } + + /* GPRs. */ + env->regs[R_EAX] =3D state->gprs[NVMM_X64_GPR_RAX]; + env->regs[R_ECX] =3D state->gprs[NVMM_X64_GPR_RCX]; + env->regs[R_EDX] =3D state->gprs[NVMM_X64_GPR_RDX]; + env->regs[R_EBX] =3D state->gprs[NVMM_X64_GPR_RBX]; + env->regs[R_ESP] =3D state->gprs[NVMM_X64_GPR_RSP]; + env->regs[R_EBP] =3D state->gprs[NVMM_X64_GPR_RBP]; + env->regs[R_ESI] =3D state->gprs[NVMM_X64_GPR_RSI]; + env->regs[R_EDI] =3D state->gprs[NVMM_X64_GPR_RDI]; +#ifdef TARGET_X86_64 + env->regs[R_R8] =3D state->gprs[NVMM_X64_GPR_R8]; + env->regs[R_R9] =3D state->gprs[NVMM_X64_GPR_R9]; + env->regs[R_R10] =3D state->gprs[NVMM_X64_GPR_R10]; + env->regs[R_R11] =3D state->gprs[NVMM_X64_GPR_R11]; + env->regs[R_R12] =3D state->gprs[NVMM_X64_GPR_R12]; + env->regs[R_R13] =3D state->gprs[NVMM_X64_GPR_R13]; + env->regs[R_R14] =3D state->gprs[NVMM_X64_GPR_R14]; + env->regs[R_R15] =3D state->gprs[NVMM_X64_GPR_R15]; +#endif + + /* RIP and RFLAGS. */ + env->eip =3D state->gprs[NVMM_X64_GPR_RIP]; + env->eflags =3D state->gprs[NVMM_X64_GPR_RFLAGS]; + + /* Segments. */ + nvmm_get_segment(&env->segs[R_ES], &state->segs[NVMM_X64_SEG_ES]); + nvmm_get_segment(&env->segs[R_CS], &state->segs[NVMM_X64_SEG_CS]); + nvmm_get_segment(&env->segs[R_SS], &state->segs[NVMM_X64_SEG_SS]); + nvmm_get_segment(&env->segs[R_DS], &state->segs[NVMM_X64_SEG_DS]); + nvmm_get_segment(&env->segs[R_FS], &state->segs[NVMM_X64_SEG_FS]); + nvmm_get_segment(&env->segs[R_GS], &state->segs[NVMM_X64_SEG_GS]); + + /* Special segments. */ + nvmm_get_segment(&env->gdt, &state->segs[NVMM_X64_SEG_GDT]); + nvmm_get_segment(&env->ldt, &state->segs[NVMM_X64_SEG_LDT]); + nvmm_get_segment(&env->tr, &state->segs[NVMM_X64_SEG_TR]); + nvmm_get_segment(&env->idt, &state->segs[NVMM_X64_SEG_IDT]); + + /* Control registers. */ + env->cr[0] =3D state->crs[NVMM_X64_CR_CR0]; + env->cr[2] =3D state->crs[NVMM_X64_CR_CR2]; + env->cr[3] =3D state->crs[NVMM_X64_CR_CR3]; + env->cr[4] =3D state->crs[NVMM_X64_CR_CR4]; + tpr =3D state->crs[NVMM_X64_CR_CR8]; + if (tpr !=3D qcpu->tpr) { + qcpu->tpr =3D tpr; + cpu_set_apic_tpr(x86_cpu->apic_state, tpr); + } + env->xcr0 =3D state->crs[NVMM_X64_CR_XCR0]; + + /* Debug registers. */ + env->dr[0] =3D state->drs[NVMM_X64_DR_DR0]; + env->dr[1] =3D state->drs[NVMM_X64_DR_DR1]; + env->dr[2] =3D state->drs[NVMM_X64_DR_DR2]; + env->dr[3] =3D state->drs[NVMM_X64_DR_DR3]; + env->dr[6] =3D state->drs[NVMM_X64_DR_DR6]; + env->dr[7] =3D state->drs[NVMM_X64_DR_DR7]; + + /* FPU. */ + env->fpuc =3D state->fpu.fx_cw; + env->fpstt =3D (state->fpu.fx_sw >> 11) & 0x7; + env->fpus =3D state->fpu.fx_sw & ~0x3800; + for (i =3D 0; i < 8; i++) { + env->fptags[i] =3D !((state->fpu.fx_tw >> i) & 1); + } + env->fpop =3D state->fpu.fx_opcode; + env->fpip =3D state->fpu.fx_ip.fa_64; + env->fpdp =3D state->fpu.fx_dp.fa_64; + env->mxcsr =3D state->fpu.fx_mxcsr; + assert(sizeof(state->fpu.fx_87_ac) =3D=3D sizeof(env->fpregs)); + memcpy(env->fpregs, state->fpu.fx_87_ac, sizeof(env->fpregs)); + for (i =3D 0; i < CPU_NB_REGS; i++) { + memcpy(&env->xmm_regs[i].ZMM_Q(0), + &state->fpu.fx_xmm[i].xmm_bytes[0], 8); + memcpy(&env->xmm_regs[i].ZMM_Q(1), + &state->fpu.fx_xmm[i].xmm_bytes[8], 8); + } + + /* MSRs. */ + env->efer =3D state->msrs[NVMM_X64_MSR_EFER]; + env->star =3D state->msrs[NVMM_X64_MSR_STAR]; +#ifdef TARGET_X86_64 + env->lstar =3D state->msrs[NVMM_X64_MSR_LSTAR]; + env->cstar =3D state->msrs[NVMM_X64_MSR_CSTAR]; + env->fmask =3D state->msrs[NVMM_X64_MSR_SFMASK]; + env->kernelgsbase =3D state->msrs[NVMM_X64_MSR_KERNELGSBASE]; +#endif + env->sysenter_cs =3D state->msrs[NVMM_X64_MSR_SYSENTER_CS]; + env->sysenter_esp =3D state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; + env->sysenter_eip =3D state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; + env->pat =3D state->msrs[NVMM_X64_MSR_PAT]; + env->tsc =3D state->msrs[NVMM_X64_MSR_TSC]; + + x86_update_hflags(env); +} + +static bool +nvmm_can_take_int(CPUState *cpu) +{ + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + struct nvmm_machine *mach =3D get_nvmm_mach(); + + if (qcpu->int_window_exit) { + return false; + } + + if (qcpu->int_shadow || !(env->eflags & IF_MASK)) { + struct nvmm_x64_state *state =3D vcpu->state; + + /* Exit on interrupt window. */ + nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_INTR); + state->intr.int_window_exiting =3D 1; + nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_INTR); + + return false; + } + + return true; +} + +static bool +nvmm_can_take_nmi(CPUState *cpu) +{ + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + + /* + * Contrary to INTs, NMIs always schedule an exit when they are + * completed. Therefore, if window-exiting is enabled, it means + * NMIs are blocked. + */ + if (qcpu->nmi_window_exit) { + return false; + } + + return true; +} + +/* + * Called before the VCPU is run. We inject events generated by the I/O + * thread, and synchronize the guest TPR. + */ +static void +nvmm_vcpu_pre_run(CPUState *cpu) +{ + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + struct nvmm_machine *mach =3D get_nvmm_mach(); + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + X86CPU *x86_cpu =3D X86_CPU(cpu); + struct nvmm_x64_state *state =3D vcpu->state; + struct nvmm_vcpu_event *event =3D vcpu->event; + bool has_event =3D false; + bool sync_tpr =3D false; + uint8_t tpr; + int ret; + + qemu_mutex_lock_iothread(); + + tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); + if (tpr !=3D qcpu->tpr) { + qcpu->tpr =3D tpr; + sync_tpr =3D true; + } + + /* + * Force the VCPU out of its inner loop to process any INIT requests + * or commit pending TPR access. + */ + if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR))= { + cpu->exit_request =3D 1; + } + + if (!has_event && (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + if (nvmm_can_take_nmi(cpu)) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + event->type =3D NVMM_VCPU_EVENT_INTR; + event->vector =3D 2; + has_event =3D true; + } + } + + if (!has_event && (cpu->interrupt_request & CPU_INTERRUPT_HARD)) { + if (nvmm_can_take_int(cpu)) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + event->type =3D NVMM_VCPU_EVENT_INTR; + event->vector =3D cpu_get_pic_interrupt(env); + has_event =3D true; + } + } + + /* Don't want SMIs. */ + if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_SMI; + } + + if (sync_tpr) { + ret =3D nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_CRS); + if (ret =3D=3D -1) { + error_report("NVMM: Failed to get CPU state," + " error=3D%d", errno); + } + + state->crs[NVMM_X64_CR_CR8] =3D qcpu->tpr; + + ret =3D nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_CRS); + if (ret =3D=3D -1) { + error_report("NVMM: Failed to set CPU state," + " error=3D%d", errno); + } + } + + if (has_event) { + ret =3D nvmm_vcpu_inject(mach, vcpu); + if (ret =3D=3D -1) { + error_report("NVMM: Failed to inject event," + " error=3D%d", errno); + } + } + + qemu_mutex_unlock_iothread(); +} + +/* + * Called after the VCPU ran. We synchronize the host view of the TPR and + * RFLAGS. + */ +static void +nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) +{ + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + X86CPU *x86_cpu =3D X86_CPU(cpu); + uint64_t tpr; + + env->eflags =3D exit->exitstate.rflags; + qcpu->int_shadow =3D exit->exitstate.int_shadow; + qcpu->int_window_exit =3D exit->exitstate.int_window_exiting; + qcpu->nmi_window_exit =3D exit->exitstate.nmi_window_exiting; + + tpr =3D exit->exitstate.cr8; + if (qcpu->tpr !=3D tpr) { + qcpu->tpr =3D tpr; + qemu_mutex_lock_iothread(); + cpu_set_apic_tpr(x86_cpu->apic_state, qcpu->tpr); + qemu_mutex_unlock_iothread(); + } +} + +/* -----------------------------------------------------------------------= --- */ + +static void +nvmm_io_callback(struct nvmm_io *io) +{ + MemTxAttrs attrs =3D { 0 }; + int ret; + + ret =3D address_space_rw(&address_space_io, io->port, attrs, io->data, + io->size, !io->in); + if (ret !=3D MEMTX_OK) { + error_report("NVMM: I/O Transaction Failed " + "[%s, port=3D%u, size=3D%zu]", (io->in ? "in" : "out"), + io->port, io->size); + } + + /* Needed, otherwise infinite loop. */ + current_cpu->vcpu_dirty =3D false; +} + +static void +nvmm_mem_callback(struct nvmm_mem *mem) +{ + cpu_physical_memory_rw(mem->gpa, mem->data, mem->size, mem->write); + + /* Needed, otherwise infinite loop. */ + current_cpu->vcpu_dirty =3D false; +} + +static struct nvmm_assist_callbacks nvmm_callbacks =3D { + .io =3D nvmm_io_callback, + .mem =3D nvmm_mem_callback +}; + +/* -----------------------------------------------------------------------= --- */ + +static int +nvmm_handle_mem(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu) +{ + int ret; + + ret =3D nvmm_assist_mem(mach, vcpu); + if (ret =3D=3D -1) { + error_report("NVMM: Mem Assist Failed [gpa=3D%p]", + (void *)vcpu->exit->u.mem.gpa); + } + + return ret; +} + +static int +nvmm_handle_io(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu) +{ + int ret; + + ret =3D nvmm_assist_io(mach, vcpu); + if (ret =3D=3D -1) { + error_report("NVMM: I/O Assist Failed [port=3D%d]", + (int)vcpu->exit->u.io.port); + } + + return ret; +} + +static int +nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, + struct nvmm_vcpu_exit *exit) +{ + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + X86CPU *x86_cpu =3D X86_CPU(cpu); + struct nvmm_x64_state *state =3D vcpu->state; + uint64_t val; + int ret; + + switch (exit->u.rdmsr.msr) { + case MSR_IA32_APICBASE: + val =3D cpu_get_apic_base(x86_cpu->apic_state); + break; + case MSR_MTRRcap: + case MSR_MTRRdefType: + case MSR_MCG_CAP: + case MSR_MCG_STATUS: + val =3D 0; + break; + default: /* More MSRs to add? */ + val =3D 0; + error_report("NVMM: Unexpected RDMSR 0x%x, ignored", + exit->u.rdmsr.msr); + break; + } + + ret =3D nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_GPRS); + if (ret =3D=3D -1) { + return -1; + } + + state->gprs[NVMM_X64_GPR_RAX] =3D (val & 0xFFFFFFFF); + state->gprs[NVMM_X64_GPR_RDX] =3D (val >> 32); + state->gprs[NVMM_X64_GPR_RIP] =3D exit->u.rdmsr.npc; + + ret =3D nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_GPRS); + if (ret =3D=3D -1) { + return -1; + } + + return 0; +} + +static int +nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, + struct nvmm_vcpu_exit *exit) +{ + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + X86CPU *x86_cpu =3D X86_CPU(cpu); + struct nvmm_x64_state *state =3D vcpu->state; + uint64_t val; + int ret; + + val =3D exit->u.wrmsr.val; + + switch (exit->u.wrmsr.msr) { + case MSR_IA32_APICBASE: + cpu_set_apic_base(x86_cpu->apic_state, val); + break; + case MSR_MTRRdefType: + case MSR_MCG_STATUS: + break; + default: /* More MSRs to add? */ + error_report("NVMM: Unexpected WRMSR 0x%x [val=3D0x%lx], ignored", + exit->u.wrmsr.msr, val); + break; + } + + ret =3D nvmm_vcpu_getstate(mach, vcpu, NVMM_X64_STATE_GPRS); + if (ret =3D=3D -1) { + return -1; + } + + state->gprs[NVMM_X64_GPR_RIP] =3D exit->u.wrmsr.npc; + + ret =3D nvmm_vcpu_setstate(mach, vcpu, NVMM_X64_STATE_GPRS); + if (ret =3D=3D -1) { + return -1; + } + + return 0; +} + +static int +nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, + struct nvmm_vcpu_exit *exit) +{ + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + int ret =3D 0; + + qemu_mutex_lock_iothread(); + + if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + (env->eflags & IF_MASK)) && + !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu->exception_index =3D EXCP_HLT; + cpu->halted =3D true; + ret =3D 1; + } + + qemu_mutex_unlock_iothread(); + + return ret; +} + +static int +nvmm_inject_ud(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu) +{ + struct nvmm_vcpu_event *event =3D vcpu->event; + + event->type =3D NVMM_VCPU_EVENT_EXCP; + event->vector =3D 6; + event->u.excp.error =3D 0; + + return nvmm_vcpu_inject(mach, vcpu); +} + +static int +nvmm_vcpu_loop(CPUState *cpu) +{ + struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + struct nvmm_machine *mach =3D get_nvmm_mach(); + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + X86CPU *x86_cpu =3D X86_CPU(cpu); + struct nvmm_vcpu_exit *exit =3D vcpu->exit; + int ret; + + /* + * Some asynchronous events must be handled outside of the inner + * VCPU loop. They are handled here. + */ + if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { + nvmm_cpu_synchronize_state(cpu); + do_cpu_init(x86_cpu); + /* set int/nmi windows back to the reset state */ + } + if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + apic_poll_irq(x86_cpu->apic_state); + } + if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + (env->eflags & IF_MASK)) || + (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu->halted =3D false; + } + if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { + nvmm_cpu_synchronize_state(cpu); + do_cpu_sipi(x86_cpu); + } + if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_TPR; + nvmm_cpu_synchronize_state(cpu); + apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, + env->tpr_access_type); + } + + if (cpu->halted) { + cpu->exception_index =3D EXCP_HLT; + qatomic_set(&cpu->exit_request, false); + return 0; + } + + qemu_mutex_unlock_iothread(); + cpu_exec_start(cpu); + + /* + * Inner VCPU loop. + */ + do { + if (cpu->vcpu_dirty) { + nvmm_set_registers(cpu); + cpu->vcpu_dirty =3D false; + } + + if (qcpu->stop) { + cpu->exception_index =3D EXCP_INTERRUPT; + qcpu->stop =3D false; + ret =3D 1; + break; + } + + nvmm_vcpu_pre_run(cpu); + + if (qatomic_read(&cpu->exit_request)) { + nvmm_vcpu_stop(vcpu); + } + + /* Read exit_request before the kernel reads the immediate exit fl= ag */ + smp_rmb(); + ret =3D nvmm_vcpu_run(mach, vcpu); + if (ret =3D=3D -1) { + error_report("NVMM: Failed to exec a virtual processor," + " error=3D%d", errno); + break; + } + + nvmm_vcpu_post_run(cpu, exit); + + switch (exit->reason) { + case NVMM_VCPU_EXIT_NONE: + break; + case NVMM_VCPU_EXIT_STOPPED: + /* + * The kernel cleared the immediate exit flag; cpu->exit_reque= st + * must be cleared after + */ + smp_wmb(); + qcpu->stop =3D true; + break; + case NVMM_VCPU_EXIT_MEMORY: + ret =3D nvmm_handle_mem(mach, vcpu); + break; + case NVMM_VCPU_EXIT_IO: + ret =3D nvmm_handle_io(mach, vcpu); + break; + case NVMM_VCPU_EXIT_INT_READY: + case NVMM_VCPU_EXIT_NMI_READY: + case NVMM_VCPU_EXIT_TPR_CHANGED: + break; + case NVMM_VCPU_EXIT_HALTED: + ret =3D nvmm_handle_halted(mach, cpu, exit); + break; + case NVMM_VCPU_EXIT_SHUTDOWN: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + cpu->exception_index =3D EXCP_INTERRUPT; + ret =3D 1; + break; + case NVMM_VCPU_EXIT_RDMSR: + ret =3D nvmm_handle_rdmsr(mach, cpu, exit); + break; + case NVMM_VCPU_EXIT_WRMSR: + ret =3D nvmm_handle_wrmsr(mach, cpu, exit); + break; + case NVMM_VCPU_EXIT_MONITOR: + case NVMM_VCPU_EXIT_MWAIT: + ret =3D nvmm_inject_ud(mach, vcpu); + break; + default: + error_report("NVMM: Unexpected VM exit code 0x%lx [hw=3D0x%lx]= ", + exit->reason, exit->u.inv.hwcode); + nvmm_get_registers(cpu); + qemu_mutex_lock_iothread(); + qemu_system_guest_panicked(cpu_get_crash_info(cpu)); + qemu_mutex_unlock_iothread(); + ret =3D -1; + break; + } + } while (ret =3D=3D 0); + + cpu_exec_end(cpu); + qemu_mutex_lock_iothread(); + + qatomic_set(&cpu->exit_request, false); + + return ret < 0; +} + +/* -----------------------------------------------------------------------= --- */ + +static void +do_nvmm_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg) +{ + nvmm_get_registers(cpu); + cpu->vcpu_dirty =3D true; +} + +static void +do_nvmm_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg) +{ + nvmm_set_registers(cpu); + cpu->vcpu_dirty =3D false; +} + +static void +do_nvmm_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg) +{ + nvmm_set_registers(cpu); + cpu->vcpu_dirty =3D false; +} + +static void +do_nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu, run_on_cpu_data arg) +{ + cpu->vcpu_dirty =3D true; +} + +void nvmm_cpu_synchronize_state(CPUState *cpu) +{ + if (!cpu->vcpu_dirty) { + run_on_cpu(cpu, do_nvmm_cpu_synchronize_state, RUN_ON_CPU_NULL); + } +} + +void nvmm_cpu_synchronize_post_reset(CPUState *cpu) +{ + run_on_cpu(cpu, do_nvmm_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); +} + +void nvmm_cpu_synchronize_post_init(CPUState *cpu) +{ + run_on_cpu(cpu, do_nvmm_cpu_synchronize_post_init, RUN_ON_CPU_NULL); +} + +void nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu) +{ + run_on_cpu(cpu, do_nvmm_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); +} + +/* -----------------------------------------------------------------------= --- */ + +static Error *nvmm_migration_blocker; + +/* + * The nvmm_vcpu_stop() mechanism breaks races between entering the VMM + * and another thread signaling the vCPU thread to exit. + */ + +static void +nvmm_ipi_signal(int sigcpu) +{ + if (current_cpu) { + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(current_cpu); + struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; + nvmm_vcpu_stop(vcpu); + } +} + +static void +nvmm_init_cpu_signals(void) +{ + struct sigaction sigact; + sigset_t set; + + /* Install the IPI handler. */ + memset(&sigact, 0, sizeof(sigact)); + sigact.sa_handler =3D nvmm_ipi_signal; + sigaction(SIG_IPI, &sigact, NULL); + + /* Allow IPIs on the current thread. */ + sigprocmask(SIG_BLOCK, NULL, &set); + sigdelset(&set, SIG_IPI); + pthread_sigmask(SIG_SETMASK, &set, NULL); +} + +int +nvmm_init_vcpu(CPUState *cpu) +{ + struct nvmm_machine *mach =3D get_nvmm_mach(); + struct nvmm_vcpu_conf_cpuid cpuid; + struct nvmm_vcpu_conf_tpr tpr; + Error *local_error =3D NULL; + struct qemu_vcpu *qcpu; + int ret, err; + + nvmm_init_cpu_signals(); + + if (nvmm_migration_blocker =3D=3D NULL) { + error_setg(&nvmm_migration_blocker, + "NVMM: Migration not supported"); + + (void)migrate_add_blocker(nvmm_migration_blocker, &local_error); + if (local_error) { + error_report_err(local_error); + migrate_del_blocker(nvmm_migration_blocker); + error_free(nvmm_migration_blocker); + return -EINVAL; + } + } + + qcpu =3D g_malloc0(sizeof(*qcpu)); + if (qcpu =3D=3D NULL) { + error_report("NVMM: Failed to allocate VCPU context."); + return -ENOMEM; + } + + ret =3D nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Failed to create a virtual processor," + " error=3D%d", err); + g_free(qcpu); + return -err; + } + + memset(&cpuid, 0, sizeof(cpuid)); + cpuid.mask =3D 1; + cpuid.leaf =3D 0x00000001; + cpuid.u.mask.set.edx =3D CPUID_MCE | CPUID_MCA | CPUID_MTRR; + ret =3D nvmm_vcpu_configure(mach, &qcpu->vcpu, NVMM_VCPU_CONF_CPUID, + &cpuid); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Failed to configure a virtual processor," + " error=3D%d", err); + g_free(qcpu); + return -err; + } + + ret =3D nvmm_vcpu_configure(mach, &qcpu->vcpu, NVMM_VCPU_CONF_CALLBACK= S, + &nvmm_callbacks); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Failed to configure a virtual processor," + " error=3D%d", err); + g_free(qcpu); + return -err; + } + + if (qemu_mach.cap.arch.vcpu_conf_support & NVMM_CAP_ARCH_VCPU_CONF_TPR= ) { + memset(&tpr, 0, sizeof(tpr)); + tpr.exit_changed =3D 1; + ret =3D nvmm_vcpu_configure(mach, &qcpu->vcpu, NVMM_VCPU_CONF_TPR,= &tpr); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Failed to configure a virtual processor," + " error=3D%d", err); + g_free(qcpu); + return -err; + } + } + + cpu->vcpu_dirty =3D true; + cpu->hax_vcpu =3D (struct hax_vcpu_state *)qcpu; + + return 0; +} + +int +nvmm_vcpu_exec(CPUState *cpu) +{ + int ret, fatal; + + while (1) { + if (cpu->exception_index >=3D EXCP_INTERRUPT) { + ret =3D cpu->exception_index; + cpu->exception_index =3D -1; + break; + } + + fatal =3D nvmm_vcpu_loop(cpu); + + if (fatal) { + error_report("NVMM: Failed to execute a VCPU."); + abort(); + } + } + + return ret; +} + +void +nvmm_destroy_vcpu(CPUState *cpu) +{ + struct nvmm_machine *mach =3D get_nvmm_mach(); + struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + + nvmm_vcpu_destroy(mach, &qcpu->vcpu); + g_free(cpu->hax_vcpu); +} + +/* -----------------------------------------------------------------------= --- */ + +static void +nvmm_update_mapping(hwaddr start_pa, ram_addr_t size, uintptr_t hva, + bool add, bool rom, const char *name) +{ + struct nvmm_machine *mach =3D get_nvmm_mach(); + int ret, prot; + + if (add) { + prot =3D PROT_READ | PROT_EXEC; + if (!rom) { + prot |=3D PROT_WRITE; + } + ret =3D nvmm_gpa_map(mach, hva, start_pa, size, prot); + } else { + ret =3D nvmm_gpa_unmap(mach, hva, start_pa, size); + } + + if (ret =3D=3D -1) { + error_report("NVMM: Failed to %s GPA range '%s' PA:%p, " + "Size:%p bytes, HostVA:%p, error=3D%d", + (add ? "map" : "unmap"), name, (void *)(uintptr_t)start_pa, + (void *)size, (void *)hva, errno); + } +} + +static void +nvmm_process_section(MemoryRegionSection *section, int add) +{ + MemoryRegion *mr =3D section->mr; + hwaddr start_pa =3D section->offset_within_address_space; + ram_addr_t size =3D int128_get64(section->size); + unsigned int delta; + uintptr_t hva; + + if (!memory_region_is_ram(mr)) { + return; + } + + /* Adjust start_pa and size so that they are page-aligned. */ + delta =3D qemu_real_host_page_size - (start_pa & ~qemu_real_host_page_= mask); + delta &=3D ~qemu_real_host_page_mask; + if (delta > size) { + return; + } + start_pa +=3D delta; + size -=3D delta; + size &=3D qemu_real_host_page_mask; + if (!size || (start_pa & ~qemu_real_host_page_mask)) { + return; + } + + hva =3D (uintptr_t)memory_region_get_ram_ptr(mr) + + section->offset_within_region + delta; + + nvmm_update_mapping(start_pa, size, hva, add, + memory_region_is_rom(mr), mr->name); +} + +static void +nvmm_region_add(MemoryListener *listener, MemoryRegionSection *section) +{ + memory_region_ref(section->mr); + nvmm_process_section(section, 1); +} + +static void +nvmm_region_del(MemoryListener *listener, MemoryRegionSection *section) +{ + nvmm_process_section(section, 0); + memory_region_unref(section->mr); +} + +static void +nvmm_transaction_begin(MemoryListener *listener) +{ + /* nothing */ +} + +static void +nvmm_transaction_commit(MemoryListener *listener) +{ + /* nothing */ +} + +static void +nvmm_log_sync(MemoryListener *listener, MemoryRegionSection *section) +{ + MemoryRegion *mr =3D section->mr; + + if (!memory_region_is_ram(mr)) { + return; + } + + memory_region_set_dirty(mr, 0, int128_get64(section->size)); +} + +static MemoryListener nvmm_memory_listener =3D { + .begin =3D nvmm_transaction_begin, + .commit =3D nvmm_transaction_commit, + .region_add =3D nvmm_region_add, + .region_del =3D nvmm_region_del, + .log_sync =3D nvmm_log_sync, + .priority =3D 10, +}; + +static void +nvmm_ram_block_added(RAMBlockNotifier *n, void *host, size_t size) +{ + struct nvmm_machine *mach =3D get_nvmm_mach(); + uintptr_t hva =3D (uintptr_t)host; + int ret; + + ret =3D nvmm_hva_map(mach, hva, size); + + if (ret =3D=3D -1) { + error_report("NVMM: Failed to map HVA, HostVA:%p " + "Size:%p bytes, error=3D%d", + (void *)hva, (void *)size, errno); + } +} + +static struct RAMBlockNotifier nvmm_ram_notifier =3D { + .ram_block_added =3D nvmm_ram_block_added +}; + +/* -----------------------------------------------------------------------= --- */ + +static int +nvmm_accel_init(MachineState *ms) +{ + int ret, err; + + ret =3D nvmm_init(); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Initialization failed, error=3D%d", errno); + return -err; + } + + ret =3D nvmm_capability(&qemu_mach.cap); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Unable to fetch capability, error=3D%d", errno= ); + return -err; + } + if (qemu_mach.cap.version < NVMM_KERN_VERSION) { + error_report("NVMM: Unsupported version %u", qemu_mach.cap.version= ); + return -EPROGMISMATCH; + } + if (qemu_mach.cap.state_size !=3D sizeof(struct nvmm_x64_state)) { + error_report("NVMM: Wrong state size %u", qemu_mach.cap.state_size= ); + return -EPROGMISMATCH; + } + + ret =3D nvmm_machine_create(&qemu_mach.mach); + if (ret =3D=3D -1) { + err =3D errno; + error_report("NVMM: Machine creation failed, error=3D%d", errno); + return -err; + } + + memory_listener_register(&nvmm_memory_listener, &address_space_memory); + ram_block_notifier_add(&nvmm_ram_notifier); + + printf("NetBSD Virtual Machine Monitor accelerator is operational\n"); + return 0; +} + +int +nvmm_enabled(void) +{ + return nvmm_allowed; +} + +static void +nvmm_accel_class_init(ObjectClass *oc, void *data) +{ + AccelClass *ac =3D ACCEL_CLASS(oc); + ac->name =3D "NVMM"; + ac->init_machine =3D nvmm_accel_init; + ac->allowed =3D &nvmm_allowed; +} + +static const TypeInfo nvmm_accel_type =3D { + .name =3D ACCEL_CLASS_NAME("nvmm"), + .parent =3D TYPE_ACCEL, + .class_init =3D nvmm_accel_class_init, +}; + +static void +nvmm_type_init(void) +{ + type_register_static(&nvmm_accel_type); +} + +type_init(nvmm_type_init); --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kamil Rytarowski , Reinoud Zandijk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Reinoud Zandijk Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk Message-Id: <20210402202535.11550-4-reinoud@NetBSD.org> Signed-off-by: Paolo Bonzini --- include/sysemu/hw_accel.h | 1 + include/sysemu/nvmm.h | 26 ++++++++++++++++++++++++++ target/i386/helper.c | 2 +- 3 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 include/sysemu/nvmm.h diff --git a/include/sysemu/hw_accel.h b/include/sysemu/hw_accel.h index 61672f9b32..01b5ebf442 100644 --- a/include/sysemu/hw_accel.h +++ b/include/sysemu/hw_accel.h @@ -16,6 +16,7 @@ #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "sysemu/whpx.h" +#include "sysemu/nvmm.h" =20 void cpu_synchronize_state(CPUState *cpu); void cpu_synchronize_post_reset(CPUState *cpu); diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h new file mode 100644 index 0000000000..6d216599b0 --- /dev/null +++ b/include/sysemu/nvmm.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018-2019 Maxime Villard, All rights reserved. + * + * NetBSD Virtual Machine Monitor (NVMM) accelerator support. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_NVMM_H +#define QEMU_NVMM_H + +#include "config-host.h" +#include "qemu-common.h" + +#ifdef CONFIG_NVMM + +int nvmm_enabled(void); + +#else /* CONFIG_NVMM */ + +#define nvmm_enabled() (0) + +#endif /* CONFIG_NVMM */ + +#endif /* CONFIG_NVMM */ diff --git a/target/i386/helper.c b/target/i386/helper.c index 618ad1c409..8c180b5b2b 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -495,7 +495,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess = access) X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); =20 - if (kvm_enabled() || whpx_enabled()) { + if (kvm_enabled() || whpx_enabled() || nvmm_enabled()) { env->tpr_access_type =3D access; =20 cpu_interrupt(cs, CPU_INTERRUPT_TPR); --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1619861725; cv=none; d=zohomail.com; s=zohoarc; b=Qow6sFkYhrKkHhBWxbm4Ss/fwInD5fTwltVGonQJySJbfuVwjHZpnGxdFEcCcBYIPEsQFf9yU8eIq+dnl6xu2wZ1CzHdunUu0WsAJ8+VromJFdRamv7BOBylxEZo1f2ojgh1qPoEm8wffKwLND9azBGRqZ7gpWRYUIzcEAQgNgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619861725; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vV+zf/1bQAsAUU58HSRZ4dlpBrgD7hp3E95gfiSrSSU=; b=TWWMn5R3UfLS5+6eQ1QCJELWD6Hb3oVom8HKim61MUj+bXNhUrKCIIeazQV+2lRghw WVjp6EaoMNBKdfkKB5sOXOKyWkAWx+ba7tZUaUgtfna9+53Y1S1jd5zPxzdBqvyA7fEh SSilaIoSRzpSB2tFEETy9uF6ueIEHf/hsYI7tyj8BMT3CHfFiT4cQD3ar0pLlbOj7ZpL PQ9lqQck4FJTtE0a+J0ZV3r0Z1uVky3+6fPGxzNc/w8mHczhnjheC8lsFfqyoqMjb08p haccSdx862cRIN6+GBWKgEtWNOXlE4cudpVRINKuxWugClw34IZiIDcLQyH5upHUm0wH UFUg== X-Gm-Message-State: AOAM533ER2U7VufYoYPGtTLEHa0QQN71T59ZWwlRbQwAfxMuK2OANc1i /AZnQENh5tgx8uVJJlAQDwLKGZrMFcA= X-Google-Smtp-Source: ABdhPJyFKcXsACahlNrb4dlSpT4jRGihbX1YIzwNSmi7eAN25aAd3My/59s3/aLvllgLeqfc4Id0Hg== X-Received: by 2002:a05:6402:268f:: with SMTP id w15mr1968039edd.321.1619861435040; Sat, 01 May 2021 02:30:35 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 06/10] ratelimit: protect with a mutex Date: Sat, 1 May 2021 11:30:22 +0200 Message-Id: <20210501093026.189429-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210501093026.189429-1-pbonzini@redhat.com> References: <20210501093026.189429-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Right now, rate limiting is protected by the AioContext mutex, which is taken for example both by the block jobs and by qmp_block_job_set_speed (via find_block_job). We would like to remove the dependency of block layer code on the AioContext mutex, since most drivers and the core I/O code are already not relying on it. However, there is no existing lock that can easily be taken by both ratelimit_set_speed and ratelimit_calculate_delay, especially because the latter might run in coroutine context (and therefore under a CoMutex) but the former will not. Since concurrent calls to ratelimit_calculate_delay are not possible, one idea could be to use a seqlock to get a snapshot of slice_ns and slice_quota. But for now keep it simple, and just add a mutex to the RateLimit struct; block jobs are generally not performance critical to the point of optimizing the clock cycles spent in synchronization. This also requires the introduction of init/destroy functions, so add them to the two users of ratelimit.h. Signed-off-by: Paolo Bonzini --- block/block-copy.c | 2 ++ blockjob.c | 3 +++ include/qemu/ratelimit.h | 14 ++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/block/block-copy.c b/block/block-copy.c index 39ae481c8b..9b4af00614 100644 --- a/block/block-copy.c +++ b/block/block-copy.c @@ -230,6 +230,7 @@ void block_copy_state_free(BlockCopyState *s) return; } =20 + ratelimit_destroy(&s->rate_limit); bdrv_release_dirty_bitmap(s->copy_bitmap); shres_destroy(s->mem); g_free(s); @@ -289,6 +290,7 @@ BlockCopyState *block_copy_state_new(BdrvChild *source,= BdrvChild *target, s->copy_size =3D MAX(s->cluster_size, BLOCK_COPY_MAX_BUFFER); } =20 + ratelimit_init(&s->rate_limit); QLIST_INIT(&s->tasks); QLIST_INIT(&s->calls); =20 diff --git a/blockjob.c b/blockjob.c index 207e8c7fd9..46f15befe8 100644 --- a/blockjob.c +++ b/blockjob.c @@ -87,6 +87,7 @@ void block_job_free(Job *job) =20 block_job_remove_all_bdrv(bjob); blk_unref(bjob->blk); + ratelimit_destroy(&bjob->limit); error_free(bjob->blocker); } =20 @@ -435,6 +436,8 @@ void *block_job_create(const char *job_id, const BlockJ= obDriver *driver, assert(job->job.driver->free =3D=3D &block_job_free); assert(job->job.driver->user_resume =3D=3D &block_job_user_resume); =20 + ratelimit_init(&job->limit); + job->blk =3D blk; =20 job->finalize_cancelled_notifier.notify =3D block_job_event_cancelled; diff --git a/include/qemu/ratelimit.h b/include/qemu/ratelimit.h index 01da8d63f1..003ea6d5a3 100644 --- a/include/qemu/ratelimit.h +++ b/include/qemu/ratelimit.h @@ -14,9 +14,11 @@ #ifndef QEMU_RATELIMIT_H #define QEMU_RATELIMIT_H =20 +#include "qemu/lockable.h" #include "qemu/timer.h" =20 typedef struct { + QemuMutex lock; int64_t slice_start_time; int64_t slice_end_time; uint64_t slice_quota; @@ -40,6 +42,7 @@ static inline int64_t ratelimit_calculate_delay(RateLimit= *limit, uint64_t n) int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); double delay_slices; =20 + QEMU_LOCK_GUARD(&limit->lock); assert(limit->slice_quota && limit->slice_ns); =20 if (limit->slice_end_time < now) { @@ -65,9 +68,20 @@ static inline int64_t ratelimit_calculate_delay(RateLimi= t *limit, uint64_t n) return limit->slice_end_time - now; } =20 +static inline void ratelimit_init(RateLimit *limit) +{ + qemu_mutex_init(&limit->lock); +} + +static inline void ratelimit_destroy(RateLimit *limit) +{ + qemu_mutex_destroy(&limit->lock); +} + static inline void ratelimit_set_speed(RateLimit *limit, uint64_t speed, uint64_t slice_ns) { + QEMU_LOCK_GUARD(&limit->lock); limit->slice_ns =3D slice_ns; limit->slice_quota =3D MAX(((double)speed * slice_ns) / 1000000000ULL,= 1); } --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1619861570; cv=none; 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Sat, 01 May 2021 02:30:35 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 07/10] slirp: add configure option to disable smbd Date: Sat, 1 May 2021 11:30:23 +0200 Message-Id: <20210501093026.189429-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210501093026.189429-1-pbonzini@redhat.com> References: <20210501093026.189429-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Samuel Thibault , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joelle van Dyne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Joelle van Dyne Replace Windows specific macro with a more generic feature detection macro. Allows slirp smb feature to be disabled manually as well. Acked-by: Samuel Thibault Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Joelle van Dyne Message-Id: <20210315180341.31638-5-j@getutm.app> [Use $default_feature as the default. - Paolo] Signed-off-by: Paolo Bonzini --- configure | 26 +++++++++++++++++++++++--- meson.build | 2 +- net/slirp.c | 16 ++++++++-------- 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/configure b/configure index 268460d63d..ccc58ccc46 100755 --- a/configure +++ b/configure @@ -464,6 +464,7 @@ gettext=3D"auto" fuse=3D"auto" fuse_lseek=3D"auto" multiprocess=3D"auto" +slirp_smbd=3D"$default_feature" =20 malloc_trim=3D"auto" gio=3D"$default_feature" @@ -836,8 +837,6 @@ do fi done =20 -: ${smbd=3D${SMBD-/usr/sbin/smbd}} - # Default objcc to clang if available, otherwise use CC if has clang; then objcc=3Dclang @@ -1570,6 +1569,10 @@ for opt do ;; --disable-gio) gio=3Dno ;; + --enable-slirp-smbd) slirp_smbd=3Dyes + ;; + --disable-slirp-smbd) slirp_smbd=3Dno + ;; *) echo "ERROR: unknown option $opt" echo "Try '$0 --help' for more information" @@ -1925,6 +1928,7 @@ disabled with --disable-FEATURE, default is enabled i= f available fuse-lseek SEEK_HOLE/SEEK_DATA support for FUSE exports multiprocess Out of process device emulation support gio libgio support + slirp-smbd use smbd (at path --smbd=3D*) in slirp networking =20 NOTE: The object files are built at the place where configure is launched EOF @@ -5261,6 +5265,19 @@ case "$slirp" in ;; esac =20 +# Check for slirp smbd dupport +: ${smbd=3D${SMBD-/usr/sbin/smbd}} +if test "$slirp_smbd" !=3D "no" ; then + if test "$mingw32" =3D "yes" ; then + if test "$slirp_smbd" =3D "yes" ; then + error_exit "Host smbd not supported on this platform." + fi + slirp_smbd=3Dno + else + slirp_smbd=3Dyes + fi +fi + ########################################## # check for usable __NR_keyctl syscall =20 @@ -5536,7 +5553,10 @@ fi if test "$guest_agent" =3D "yes" ; then echo "CONFIG_GUEST_AGENT=3Dy" >> $config_host_mak fi -echo "CONFIG_SMBD_COMMAND=3D\"$smbd\"" >> $config_host_mak +if test "$slirp_smbd" =3D "yes" ; then + echo "CONFIG_SLIRP_SMBD=3Dy" >> $config_host_mak + echo "CONFIG_SMBD_COMMAND=3D\"$smbd\"" >> $config_host_mak +fi if test "$vde" =3D "yes" ; then echo "CONFIG_VDE=3Dy" >> $config_host_mak echo "VDE_LIBS=3D$vde_libs" >> $config_host_mak diff --git a/meson.build b/meson.build index 14dd3fe068..cf0bcf6b53 100644 --- a/meson.build +++ b/meson.build @@ -2464,7 +2464,7 @@ summary_info +=3D {'genisoimage': config_host['= GENISOIMAGE']} if targetos =3D=3D 'windows' and config_host.has_key('CONFIG_GUEST_AGENT') summary_info +=3D {'wixl': wixl.found() ? wixl.full_path() : = false} endif -if slirp_opt !=3D 'disabled' +if slirp_opt !=3D 'disabled' and 'CONFIG_SLIRP_SMBD' in config_host summary_info +=3D {'smbd': config_host['CONFIG_SMBD_COMMAND']} endif summary(summary_info, bool_yn: true, section: 'Host binaries') diff --git a/net/slirp.c b/net/slirp.c index a01a0fccd3..1d9cb3bd6b 100644 --- a/net/slirp.c +++ b/net/slirp.c @@ -27,7 +27,7 @@ #include "net/slirp.h" =20 =20 -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) #include #include #endif @@ -91,7 +91,7 @@ typedef struct SlirpState { Slirp *slirp; Notifier poll_notifier; Notifier exit_notifier; -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) gchar *smb_dir; #endif GSList *fwd; @@ -104,7 +104,7 @@ static QTAILQ_HEAD(, SlirpState) slirp_stacks =3D static int slirp_hostfwd(SlirpState *s, const char *redir_str, Error **err= p); static int slirp_guestfwd(SlirpState *s, const char *config_str, Error **e= rrp); =20 -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) static int slirp_smb(SlirpState *s, const char *exported_dir, struct in_addr vserver_addr, Error **errp); static void slirp_smb_cleanup(SlirpState *s); @@ -377,7 +377,7 @@ static int net_slirp_init(NetClientState *peer, const c= har *model, struct in6_addr ip6_prefix; struct in6_addr ip6_host; struct in6_addr ip6_dns; -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) struct in_addr smbsrv =3D { .s_addr =3D 0 }; #endif NetClientState *nc; @@ -487,7 +487,7 @@ static int net_slirp_init(NetClientState *peer, const c= har *model, return -1; } =20 -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) if (vsmbserver && !inet_aton(vsmbserver, &smbsrv)) { error_setg(errp, "Failed to parse SMB address"); return -1; @@ -602,7 +602,7 @@ static int net_slirp_init(NetClientState *peer, const c= har *model, } } } -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) if (smb_export) { if (slirp_smb(s, smb_export, smbsrv, errp) < 0) { goto error; @@ -794,7 +794,7 @@ void hmp_hostfwd_add(Monitor *mon, const QDict *qdict) =20 } =20 -#ifndef _WIN32 +#if defined(CONFIG_SLIRP_SMBD) =20 /* automatic user mode samba server configuration */ static void slirp_smb_cleanup(SlirpState *s) @@ -909,7 +909,7 @@ static int slirp_smb(SlirpState* s, const char *exporte= d_dir, return 0; } =20 -#endif /* !defined(_WIN32) */ +#endif /* defined(CONFIG_SLIRP_SMBD) */ =20 static int guestfwd_can_read(void *opaque) { --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Sat, 01 May 2021 02:30:36 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 08/10] configure: reindent meson invocation Date: Sat, 1 May 2021 11:30:24 +0200 Message-Id: <20210501093026.189429-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210501093026.189429-1-pbonzini@redhat.com> References: <20210501093026.189429-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=paolo.bonzini@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- configure | 76 +++++++++++++++++++++++++++---------------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/configure b/configure index ccc58ccc46..0b8283c95c 100755 --- a/configure +++ b/configure @@ -6345,33 +6345,33 @@ for rom in seabios; do done =20 if test "$skip_meson" =3D no; then -cross=3D"config-meson.cross.new" -meson_quote() { + cross=3D"config-meson.cross.new" + meson_quote() { echo "'$(echo $* | sed "s/ /','/g")'" -} - -echo "# Automatically generated by configure - do not modify" > $cross -echo "[properties]" >> $cross -test -z "$cxx" && echo "link_language =3D 'c'" >> $cross -echo "[built-in options]" >> $cross -echo "c_args =3D [${CFLAGS:+$(meson_quote $CFLAGS)}]" >> $cross -echo "cpp_args =3D [${CXXFLAGS:+$(meson_quote $CXXFLAGS)}]" >> $cross -echo "c_link_args =3D [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross -echo "cpp_link_args =3D [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross -echo "[binaries]" >> $cross -echo "c =3D [$(meson_quote $cc)]" >> $cross -test -n "$cxx" && echo "cpp =3D [$(meson_quote $cxx)]" >> $cross -test -n "$objcc" && echo "objc =3D [$(meson_quote $objcc)]" >> $cross -echo "ar =3D [$(meson_quote $ar)]" >> $cross -echo "nm =3D [$(meson_quote $nm)]" >> $cross -echo "pkgconfig =3D [$(meson_quote $pkg_config_exe)]" >> $cross -echo "ranlib =3D [$(meson_quote $ranlib)]" >> $cross -if has $sdl2_config; then - echo "sdl2-config =3D [$(meson_quote $sdl2_config)]" >> $cross -fi -echo "strip =3D [$(meson_quote $strip)]" >> $cross -echo "windres =3D [$(meson_quote $windres)]" >> $cross -if test "$cross_compile" =3D "yes"; then + } + + echo "# Automatically generated by configure - do not modify" > $cross + echo "[properties]" >> $cross + test -z "$cxx" && echo "link_language =3D 'c'" >> $cross + echo "[built-in options]" >> $cross + echo "c_args =3D [${CFLAGS:+$(meson_quote $CFLAGS)}]" >> $cross + echo "cpp_args =3D [${CXXFLAGS:+$(meson_quote $CXXFLAGS)}]" >> $cross + echo "c_link_args =3D [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross + echo "cpp_link_args =3D [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross + echo "[binaries]" >> $cross + echo "c =3D [$(meson_quote $cc)]" >> $cross + test -n "$cxx" && echo "cpp =3D [$(meson_quote $cxx)]" >> $cross + test -n "$objcc" && echo "objc =3D [$(meson_quote $objcc)]" >> $cross + echo "ar =3D [$(meson_quote $ar)]" >> $cross + echo "nm =3D [$(meson_quote $nm)]" >> $cross + echo "pkgconfig =3D [$(meson_quote $pkg_config_exe)]" >> $cross + echo "ranlib =3D [$(meson_quote $ranlib)]" >> $cross + if has $sdl2_config; then + echo "sdl2-config =3D [$(meson_quote $sdl2_config)]" >> $cross + fi + echo "strip =3D [$(meson_quote $strip)]" >> $cross + echo "windres =3D [$(meson_quote $windres)]" >> $cross + if test "$cross_compile" =3D "yes"; then cross_arg=3D"--cross-file config-meson.cross" echo "[host_machine]" >> $cross if test "$mingw32" =3D "yes" ; then @@ -6403,17 +6403,17 @@ if test "$cross_compile" =3D "yes"; then else echo "endian =3D 'little'" >> $cross fi -else + else cross_arg=3D"--native-file config-meson.cross" -fi -mv $cross config-meson.cross + fi + mv $cross config-meson.cross =20 -rm -rf meson-private meson-info meson-logs -unset staticpic -if ! version_ge "$($meson --version)" 0.56.0; then - staticpic=3D$(if test "$pie" =3D yes; then echo true; else echo false; f= i) -fi -NINJA=3D$ninja $meson setup \ + rm -rf meson-private meson-info meson-logs + unset staticpic + if ! version_ge "$($meson --version)" 0.56.0; then + staticpic=3D$(if test "$pie" =3D yes; then echo true; else echo false;= fi) + fi + NINJA=3D$ninja $meson setup \ --prefix "$prefix" \ --libdir "$libdir" \ --libexecdir "$libexecdir" \ @@ -6455,9 +6455,9 @@ NINJA=3D$ninja $meson setup \ $cross_arg \ "$PWD" "$source_path" =20 -if test "$?" -ne 0 ; then - error_exit "meson setup failed" -fi + if test "$?" -ne 0 ; then + error_exit "meson setup failed" + fi fi =20 if test -n "${deprecated_features}"; then --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1619861868; cv=none; d=zohomail.com; s=zohoarc; b=DdDpaldPD6+Pj5byh9xR37Xg+IDlDvFecTumZTefwIlFEOoZaquBk87i8Jd/0GN63yXSbSMb4reWjpxF10obr+DM850t2C++kfDwswlaoUOoKCRJhIUhDFjMTw9ddJZouYfW/r8Qd3fWyN9rVZJHJeIQ40+oa8HQxWnUI5ax+H0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619861868; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ezztMan+aCk3LpSU9driVzqY0tgeZFrNCnQhZCY0Sws=; b=JMwBOEisOosbbQarsLS3xYhsWhJNf9QSHeIK9o3yZBoVypxcV8oKnM8hoQh8ZJe4a9 cton4UdmdaT1dk+iZarQ1pivUhtdh0477MpvPPaNeymcckFQqt2OZ+nRqcNQGhh9uHSC gbn1nugC0AmXB96DLWWJd2pDp7vJ1JRD7SdVxEUgiwy3ObWm2udceMGqlOf1CgZXbHgG ANiZCt2EvkraYzo0IzXnsHjAQPT6zZsqXxXEbtJHSqp0sNTjkp0UFxuwg9g6jf51hnHY Yf+FqW4oV0u5u3VOg8SHG+K/mb5JQrg4ZZlLo5Dsa8Z7T3FVjqeoHkbOOwTBm+jefvgg 3fvw== X-Gm-Message-State: AOAM5309ibB0WgZHd1q6kdPsa1dNZPSBoDEXtLOoogF6jld4SspgXgTM 1j0mm2mXLhOXy0pEquogXe6nHnLt3H4= X-Google-Smtp-Source: ABdhPJziBt/NSFnxeHNj1J9um0fvBwGIBPEb8+CUMrfiNpXIXjUhsyfKkxj8VQV5xImtp8a5MQ52lg== X-Received: by 2002:aa7:dbc7:: with SMTP id v7mr10697634edt.110.1619861437364; Sat, 01 May 2021 02:30:37 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 09/10] configure: handle meson options that have changed type Date: Sat, 1 May 2021 11:30:25 +0200 Message-Id: <20210501093026.189429-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210501093026.189429-1-pbonzini@redhat.com> References: <20210501093026.189429-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=paolo.bonzini@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Usually Meson uses pre-serialized information in meson-private to speed up re-runs. This is not possible for version changes, where Meson instead rebuilds the serialized information using cmd_line.txt. In some cases cmd_line.txt can contain stale information, since it is not rebuild except when "meson setup" is invoked. Update it in the configure script to allow upgrading our Meson version. Signed-off-by: Paolo Bonzini --- configure | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/configure b/configure index 0b8283c95c..54f8475444 100755 --- a/configure +++ b/configure @@ -6458,6 +6458,15 @@ if test "$skip_meson" =3D no; then if test "$?" -ne 0 ; then error_exit "meson setup failed" fi +else + if test -f meson-private/cmd_line.txt; then + # Adjust old command line options whose type was changed + # Avoids having to use "setup --wipe" when Meson is upgraded + perl -i -ne ' + s/^gettext =3D true$/gettext =3D auto/; + s/^gettext =3D false$/gettext =3D disabled/; + print;' meson-private/cmd_line.txt + fi fi =20 if test -n "${deprecated_features}"; then --=20 2.31.1 From nobody Sat Feb 7 03:51:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Sat, 01 May 2021 02:30:38 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 10/10] gitlab-ci: use --meson=internal for CFI jobs Date: Sat, 1 May 2021 11:30:26 +0200 Message-Id: <20210501093026.189429-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210501093026.189429-1-pbonzini@redhat.com> References: <20210501093026.189429-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=paolo.bonzini@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" If we use the system Meson but it is too old, the subsequent "meson configu= re" will fail. Always use the submodule when building with CFI. Signed-off-by: Paolo Bonzini --- .gitlab-ci.yml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 52d65d6c04..dcb6317aac 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -19,17 +19,21 @@ include: before_script: - JOBS=3D$(expr $(nproc) + 1) script: + - if test -n "$LD_JOBS"; + then + scripts/git-submodule.sh update meson ; + fi - mkdir build - cd build - if test -n "$TARGETS"; then - ../configure --enable-werror --disable-docs $CONFIGURE_ARGS --targ= et-list=3D"$TARGETS" ; + ../configure --enable-werror --disable-docs ${LD_JOBS:+--meson=3Di= nternal} $CONFIGURE_ARGS --target-list=3D"$TARGETS" ; else - ../configure --enable-werror --disable-docs $CONFIGURE_ARGS ; + ../configure --enable-werror --disable-docs ${LD_JOBS:+--meson=3Di= nternal} $CONFIGURE_ARGS ; fi || { cat config.log meson-logs/meson-log.txt && exit 1; } - if test -n "$LD_JOBS"; then - meson configure . -Dbackend_max_links=3D"$LD_JOBS" ; + ../meson/meson.py configure . -Dbackend_max_links=3D"$LD_JOBS" ; fi || exit 1; - make -j"$JOBS" - if test -n "$MAKE_CHECK_ARGS"; --=20 2.31.1