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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabiano Rosas , qemu-devel@nongnu.org, Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=3D0b10 mode. Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c | 7 ++++- target/ppc/cpu-qom.h | 2 ++ target/ppc/cpu.h | 5 +-- target/ppc/excp_helper.c | 54 +++++++++++++++++++++++++++++++-- target/ppc/translate.c | 3 +- target/ppc/translate_init.c.inc | 2 +- 6 files changed, 65 insertions(+), 8 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 2fbe04a689..7275d0bba1 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_m= ode(PowerPCCPU *cpu, } =20 if (mflags =3D=3D 1) { - /* AIL=3D1 is reserved */ + /* AIL=3D1 is reserved in POWER8/POWER9/POWER10 */ + return H_UNSUPPORTED_FLAG; + } + + if (mflags =3D=3D 2 && (pcc->insns_flags2 & PPC2_ISA310)) { + /* AIL=3D2 is reserved in POWER10 (ISA v3.1) */ return H_UNSUPPORTED_FLAG; } =20 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 118baf8d41..06b6571bc9 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -116,6 +116,8 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER8, /* POWER9 exception model */ POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, }; =20 /*************************************************************************= ****/ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index be24a501fc..8a076fab48 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,10 +354,11 @@ typedef struct ppc_v3_pate_t { #define LPCR_PECE_U_SHIFT (63 - 19) #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ -#define LPCR_RMLS_SHIFT (63 - 37) +#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */ #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) +#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3D3 equivalent */ #define LPCR_ILE PPC_BIT(38) -#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ +#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 73360bb872..5e30a5a056 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -170,7 +170,27 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCSt= ate *env, int excp, * +-------------------------------------------------------+ * * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be se= nt to - * the hypervisor in AIL mode if the guest is radix. + * the hypervisor in AIL mode if the guest is radix. This is good for + * performance but allows the guest to influence the AIL of hypervisor + * interrupts using its MSR, and also the hypervisor must disallow guest + * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not wan= t to + * use AIL for its MSR[HV] 0->1 interrupts. + * + * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applie= d to + * interrupts that begin execution with MSR[HV]=3D1 (so both MSR[HV] 0->1 = and + * MSR[HV] 1->1). + * + * HAIL=3D1 is equivalent to AIL=3D3, for interrupts delivered with MSR[HV= ]=3D1. + * + * POWER10 behaviour is + * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+------------+-------------+---------+-------------+-----+ + * | a | h | 00/01/10 | 0 | 0 | 0 | + * | a | h | 11 | 0 | 0 | a | + * | a | h | x | 0 | 1 | h | + * | a | h | 00/01/10 | 1 | 1 | 0 | + * | a | h | 11 | 1 | 1 | h | + * +--------------------------------------------------------------------+ */ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int= excp, target_ulong msr, @@ -213,6 +233,32 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu,= int excp_model, int excp, /* AIL=3D1 is reserved, treat it like AIL=3D0 */ return; } + + } else if (excp_model =3D=3D POWERPC_EXCP_POWER10) { + if (!mmu_all_on && !hv_escalation) { + /* + * AIL works for HV interrupts even with guest MSR[IR/DR] disa= bled. + * Guest->guest and HV->HV interrupts do require MMU on. + */ + return; + } + + if (*new_msr & MSR_HVB) { + if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { + /* HV interrupts depend on LPCR[HAIL] */ + return; + } + ail =3D 3; /* HAIL=3D1 gives AIL=3D3 behaviour for HV interrup= ts */ + } else { + ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + } + if (ail =3D=3D 0) { + return; + } + if (ail =3D=3D 1 || ail =3D=3D 2) { + /* AIL=3D1 and AIL=3D2 are reserved, treat them like AIL=3D0 */ + return; + } } else { /* Other processors do not support AIL */ return; @@ -328,7 +374,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) #if defined(TARGET_PPC64) if (excp_model =3D=3D POWERPC_EXCP_POWER7 || excp_model =3D=3D POWERPC_EXCP_POWER8 || - excp_model =3D=3D POWERPC_EXCP_POWER9) { + excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); } else #endif /* defined(TARGET_PPC64) */ @@ -848,7 +895,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) } else if (env->spr[SPR_LPCR] & LPCR_ILE) { new_msr |=3D (target_ulong)1 << MSR_LE; } - } else if (excp_model =3D=3D POWERPC_EXCP_POWER9) { + } else if (excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { if (new_msr & MSR_HVB) { if (env->spr[SPR_HID0] & HID0_POWER9_HILE) { new_msr |=3D (target_ulong)1 << MSR_LE; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a53463b9b8..3bbd4cf6ac 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) #if defined(TARGET_PPC64) if (env->excp_model =3D=3D POWERPC_EXCP_POWER7 || env->excp_model =3D=3D POWERPC_EXCP_POWER8 || - env->excp_model =3D=3D POWERPC_EXCP_POWER9) { + env->excp_model =3D=3D POWERPC_EXCP_POWER9 || + env->excp_model =3D=3D POWERPC_EXCP_POWER10) { qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n= ", env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 01fa76e4a0..78cd2243f4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -9317,7 +9317,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->radix_page_info =3D &POWER10_radix_page_info; pcc->lrg_decr_bits =3D 56; #endif - pcc->excp_model =3D POWERPC_EXCP_POWER9; + pcc->excp_model =3D POWERPC_EXCP_POWER10; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | --=20 2.23.0