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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=evwPWxFbg++RdgeYJYEEF07pvcfOxDn6UBMVw2R8gZ4=; b=X2KEvNyEv5xwuLoObVq/htx6qUiKLLYW6qhmC3psIEpFqsZ+pUeM1tki3hA6pUPjn2 FHhb+QCU28StSFn2rHR/IWJmtRC/ySzpuXl0Jb1AWwG9km2eRxpb9RzDky/eJxZ+gcl2 M+jkDgzDBYqPdhyOSwyLV7qvj0QzrMV9gBUh/qffNF6XQuZdysot2zASEgvKY7ocnZvg mIA66GGsntnzqP7fqdUNSPYqJsoos8etn2JcoCzLDCMp/QLoCB2qDNpXkUd+tDDHNuYS yeKGqXH+DVqeMsyNYPKDLwD3p0CDpM4O7k70dHHs/KLFsiC0MLZzKsMMdjxwLqFyKCui EFVg== X-Gm-Message-State: AOAM530trfoMNxaYLyynPxWbAEg8Q7a/M6et40GlVxCuaF2Qw78Lfya9 lmPi7/KlHlsV6RogR3NbtvYnLpjkjmQ= X-Google-Smtp-Source: ABdhPJzCc3pjUDnR0tvOGUDCPOYcL6WEdhr6NqSIQmHW5d6rQftfKdYqSkqetLCKxW2GKb2d/MY2Jw== X-Received: by 2002:a17:902:c40c:b029:ed:7032:649c with SMTP id k12-20020a170902c40cb02900ed7032649cmr9573434plk.74.1619853887992; Sat, 01 May 2021 00:24:47 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Date: Sat, 1 May 2021 17:24:34 +1000 Message-Id: <20210501072436.145444-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210501072436.145444-1-npiggin@gmail.com> References: <20210501072436.145444-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabiano Rosas , qemu-devel@nongnu.org, Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The AIL logic is becoming unmanageable spread all over powerpc_excp(), and it is slated to get even worse with POWER10 support. Move it all to a new helper function. Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c | 3 +- target/ppc/cpu.h | 8 -- target/ppc/excp_helper.c | 165 ++++++++++++++++++++------------ target/ppc/translate_init.c.inc | 2 +- 4 files changed, 108 insertions(+), 70 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..2fbe04a689 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1395,7 +1395,8 @@ static target_ulong h_set_mode_resource_addr_trans_mo= de(PowerPCCPU *cpu, return H_P4; } =20 - if (mflags =3D=3D AIL_RESERVED) { + if (mflags =3D=3D 1) { + /* AIL=3D1 is reserved */ return H_UNSUPPORTED_FLAG; } =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8c18bb0762..be24a501fc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2405,14 +2405,6 @@ enum { HMER_XSCOM_STATUS_MASK =3D PPC_BITMASK(21, 23), }; =20 -/* Alternate Interrupt Location (AIL) */ -enum { - AIL_NONE =3D 0, - AIL_RESERVED =3D 1, - AIL_0001_8000 =3D 2, - AIL_C000_0000_0000_4000 =3D 3, -}; - /*************************************************************************= ****/ =20 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 344af66f66..73360bb872 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -136,25 +136,111 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPC= State *env, int excp, return POWERPC_EXCP_RESET; } =20 -static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail) +/* + * AIL - Alternate Interrupt Location, a mode that allows interrupts to be + * taken with the MMU on, and which uses an alternate location (e.g., so t= he + * kernel/hv can map the vectors there with an effective address). + * + * An interrupt is considered to be taken "with AIL" or "AIL applies" if t= hey + * are delivered in this way. AIL requires the LPCR to be set to enable th= is + * mode, and then a number of conditions have to be true for AIL to apply. + * + * First of all, SRESET, MCE, and HMI are always delivered without AIL, be= cause + * they specifically want to be in real mode (e.g., the MCE might be signa= ling + * a SLB multi-hit which requires SLB flush before the MMU can be enabled). + * + * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV], + * whether or not the interrupt changes MSR[HV] from 0 to 1, and the curre= nt + * radix mode (LPCR[HR]). + * + * POWER8, POWER9 with LPCR[HR]=3D0 + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+-------------+---------+-------------+-----+ + * | a | 00/01/10 | x | x | 0 | + * | a | 11 | 0 | 1 | 0 | + * | a | 11 | 1 | 1 | a | + * | a | 11 | 0 | 0 | a | + * +-------------------------------------------------------+ + * + * POWER9 with LPCR[HR]=3D1 + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+-------------+---------+-------------+-----+ + * | a | 00/01/10 | x | x | 0 | + * | a | 11 | x | x | a | + * +-------------------------------------------------------+ + * + * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be se= nt to + * the hypervisor in AIL mode if the guest is radix. + */ +static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int= excp, + target_ulong msr, + target_ulong *new_msr, + target_ulong *vector) { - uint64_t offset =3D 0; +#if defined(TARGET_PPC64) + CPUPPCState *env =3D &cpu->env; + bool mmu_all_on =3D ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); + bool hv_escalation =3D !(msr & MSR_HVB) && (*new_msr & MSR_HVB); + int ail =3D 0; + + if (excp =3D=3D POWERPC_EXCP_MCHECK || + excp =3D=3D POWERPC_EXCP_RESET || + excp =3D=3D POWERPC_EXCP_HV_MAINT) { + /* SRESET, MCE, HMI never apply AIL */ + return; + } =20 - switch (ail) { - case AIL_NONE: - break; - case AIL_0001_8000: - offset =3D 0x18000; - break; - case AIL_C000_0000_0000_4000: - offset =3D 0xc000000000004000ull; - break; - default: - cpu_abort(cs, "Invalid AIL combination %d\n", ail); - break; + if (excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9) { + if (!mmu_all_on) { + /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */ + return; + } + if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { + /* + * AIL does not work if there is a MSR[HV] 0->1 transition and= the + * partition is in HPT mode. For radix guests, such interrupts= are + * allowed to be delivered to the hypervisor in ail mode. + */ + return; + } + + ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + if (ail =3D=3D 0) { + return; + } + if (ail =3D=3D 1) { + /* AIL=3D1 is reserved, treat it like AIL=3D0 */ + return; + } + } else { + /* Other processors do not support AIL */ + return; } =20 - return offset; + /* + * AIL applies, so the new MSR gets IR and DR set, and an offset appli= ed + * to the new IP. + */ + *new_msr |=3D (1 << MSR_IR) | (1 << MSR_DR); + + if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { + if (ail =3D=3D 2) { + *vector |=3D 0x0000000000018000ull; + } else if (ail =3D=3D 3) { + *vector |=3D 0xc000000000004000ull; + } + } else { + /* + * scv AIL is a little different. AIL=3D2 does not change the address, + * only the MSR. AIL=3D3 replaces the 0x17000 base with 0xc...3000. + */ + if (ail =3D=3D 3) { + *vector &=3D ~0x0000000000017000ull; /* Un-apply the base offs= et */ + *vector |=3D 0xc000000000003000ull; /* Apply scv's AIL=3D3 off= set */ + } + } +#endif } =20 static inline void powerpc_set_excp_state(PowerPCCPU *cpu, @@ -197,7 +283,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1, asrr0, asrr1, lev =3D -1, ail; + int srr0, srr1, asrr0, asrr1, lev =3D -1; bool lpes0; =20 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx @@ -238,25 +324,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) * * On anything else, we behave as if LPES0 is 1 * (externals don't alter MSR:HV) - * - * AIL is initialized here but can be cleared by - * selected exceptions */ #if defined(TARGET_PPC64) if (excp_model =3D=3D POWERPC_EXCP_POWER7 || excp_model =3D=3D POWERPC_EXCP_POWER8 || excp_model =3D=3D POWERPC_EXCP_POWER9) { lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - if (excp_model !=3D POWERPC_EXCP_POWER7) { - ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; - } else { - ail =3D 0; - } } else #endif /* defined(TARGET_PPC64) */ { lpes0 =3D true; - ail =3D 0; } =20 /* @@ -315,7 +392,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) */ new_msr |=3D (target_ulong)MSR_HVB; } - ail =3D 0; =20 /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); @@ -519,7 +595,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) "exception %d with no HV support\n", excp); } } - ail =3D 0; break; case POWERPC_EXCP_DSEG: /* Data segment exception = */ case POWERPC_EXCP_ISEG: /* Instruction segment exception = */ @@ -790,24 +865,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) } #endif =20 - /* - * AIL only works if MSR[IR] and MSR[DR] are both enabled. - */ - if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) { - ail =3D 0; - } - - /* - * AIL does not work if there is a MSR[HV] 0->1 transition and the - * partition is in HPT mode. For radix guests, such interrupts are - * allowed to be delivered to the hypervisor in ail mode. - */ - if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) { - if (!(env->spr[SPR_LPCR] & LPCR_HR)) { - ail =3D 0; - } - } - vector =3D env->excp_vectors[excp]; if (vector =3D=3D (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -848,23 +905,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) /* Save MSR */ env->spr[srr1] =3D msr; =20 - /* Handle AIL */ - if (ail) { - new_msr |=3D (1 << MSR_IR) | (1 << MSR_DR); - vector |=3D ppc_excp_vector_offset(cs, ail); - } - #if defined(TARGET_PPC64) } else { - /* scv AIL is a little different */ - if (ail) { - new_msr |=3D (1 << MSR_IR) | (1 << MSR_DR); - } - if (ail =3D=3D AIL_C000_0000_0000_4000) { - vector |=3D 0xc000000000003000ull; - } else { - vector |=3D 0x0000000000017000ull; - } vector +=3D lev * 0x20; =20 env->lr =3D env->nip; @@ -872,6 +914,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) #endif } =20 + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + powerpc_set_excp_state(cpu, vector, new_msr); } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 9ab2c32cc4..01fa76e4a0 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -3457,7 +3457,7 @@ static void init_excp_POWER9(CPUPPCState *env) =20 #if !defined(CONFIG_USER_ONLY) env->excp_vectors[POWERPC_EXCP_HVIRT] =3D 0x00000EA0; - env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] =3D 0x00000000; + env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] =3D 0x00017000; #endif } =20 --=20 2.23.0 From nobody Sat May 18 06:31:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619854039; cv=none; d=zohomail.com; s=zohoarc; b=OeKUlok4yIh+yPQ9PNOY00Q0a+msFCYult3yt8ceXCetIns0suJCLxWOhl6IRCfyh+fMMfAnbCMaMGTkOGLH/scz9W+sGj23kDMDBShH2ZeVekUp3XLObwkgDhfoI6tJieU4hISnlfL6ogbhBiH3224nh2GK5kEKrYV+T6eriU4= ARC-Message-Signature: i=1; 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Sat, 01 May 2021 00:24:51 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 2/2] target/ppc: Add POWER10 exception model Date: Sat, 1 May 2021 17:24:35 +1000 Message-Id: <20210501072436.145444-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210501072436.145444-1-npiggin@gmail.com> References: <20210501072436.145444-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabiano Rosas , qemu-devel@nongnu.org, Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=3D0b10 mode. Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c | 7 ++++- target/ppc/cpu-qom.h | 2 ++ target/ppc/cpu.h | 5 +-- target/ppc/excp_helper.c | 54 +++++++++++++++++++++++++++++++-- target/ppc/translate.c | 3 +- target/ppc/translate_init.c.inc | 2 +- 6 files changed, 65 insertions(+), 8 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 2fbe04a689..7275d0bba1 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_m= ode(PowerPCCPU *cpu, } =20 if (mflags =3D=3D 1) { - /* AIL=3D1 is reserved */ + /* AIL=3D1 is reserved in POWER8/POWER9/POWER10 */ + return H_UNSUPPORTED_FLAG; + } + + if (mflags =3D=3D 2 && (pcc->insns_flags2 & PPC2_ISA310)) { + /* AIL=3D2 is reserved in POWER10 (ISA v3.1) */ return H_UNSUPPORTED_FLAG; } =20 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 118baf8d41..06b6571bc9 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -116,6 +116,8 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER8, /* POWER9 exception model */ POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, }; =20 /*************************************************************************= ****/ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index be24a501fc..8a076fab48 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,10 +354,11 @@ typedef struct ppc_v3_pate_t { #define LPCR_PECE_U_SHIFT (63 - 19) #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ -#define LPCR_RMLS_SHIFT (63 - 37) +#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */ #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) +#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3D3 equivalent */ #define LPCR_ILE PPC_BIT(38) -#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ +#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 73360bb872..5e30a5a056 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -170,7 +170,27 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCSt= ate *env, int excp, * +-------------------------------------------------------+ * * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be se= nt to - * the hypervisor in AIL mode if the guest is radix. + * the hypervisor in AIL mode if the guest is radix. This is good for + * performance but allows the guest to influence the AIL of hypervisor + * interrupts using its MSR, and also the hypervisor must disallow guest + * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not wan= t to + * use AIL for its MSR[HV] 0->1 interrupts. + * + * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applie= d to + * interrupts that begin execution with MSR[HV]=3D1 (so both MSR[HV] 0->1 = and + * MSR[HV] 1->1). + * + * HAIL=3D1 is equivalent to AIL=3D3, for interrupts delivered with MSR[HV= ]=3D1. + * + * POWER10 behaviour is + * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+------------+-------------+---------+-------------+-----+ + * | a | h | 00/01/10 | 0 | 0 | 0 | + * | a | h | 11 | 0 | 0 | a | + * | a | h | x | 0 | 1 | h | + * | a | h | 00/01/10 | 1 | 1 | 0 | + * | a | h | 11 | 1 | 1 | h | + * +--------------------------------------------------------------------+ */ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int= excp, target_ulong msr, @@ -213,6 +233,32 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu,= int excp_model, int excp, /* AIL=3D1 is reserved, treat it like AIL=3D0 */ return; } + + } else if (excp_model =3D=3D POWERPC_EXCP_POWER10) { + if (!mmu_all_on && !hv_escalation) { + /* + * AIL works for HV interrupts even with guest MSR[IR/DR] disa= bled. + * Guest->guest and HV->HV interrupts do require MMU on. + */ + return; + } + + if (*new_msr & MSR_HVB) { + if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { + /* HV interrupts depend on LPCR[HAIL] */ + return; + } + ail =3D 3; /* HAIL=3D1 gives AIL=3D3 behaviour for HV interrup= ts */ + } else { + ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + } + if (ail =3D=3D 0) { + return; + } + if (ail =3D=3D 1 || ail =3D=3D 2) { + /* AIL=3D1 and AIL=3D2 are reserved, treat them like AIL=3D0 */ + return; + } } else { /* Other processors do not support AIL */ return; @@ -328,7 +374,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) #if defined(TARGET_PPC64) if (excp_model =3D=3D POWERPC_EXCP_POWER7 || excp_model =3D=3D POWERPC_EXCP_POWER8 || - excp_model =3D=3D POWERPC_EXCP_POWER9) { + excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); } else #endif /* defined(TARGET_PPC64) */ @@ -848,7 +895,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) } else if (env->spr[SPR_LPCR] & LPCR_ILE) { new_msr |=3D (target_ulong)1 << MSR_LE; } - } else if (excp_model =3D=3D POWERPC_EXCP_POWER9) { + } else if (excp_model =3D=3D POWERPC_EXCP_POWER9 || + excp_model =3D=3D POWERPC_EXCP_POWER10) { if (new_msr & MSR_HVB) { if (env->spr[SPR_HID0] & HID0_POWER9_HILE) { new_msr |=3D (target_ulong)1 << MSR_LE; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a53463b9b8..3bbd4cf6ac 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) #if defined(TARGET_PPC64) if (env->excp_model =3D=3D POWERPC_EXCP_POWER7 || env->excp_model =3D=3D POWERPC_EXCP_POWER8 || - env->excp_model =3D=3D POWERPC_EXCP_POWER9) { + env->excp_model =3D=3D POWERPC_EXCP_POWER9 || + env->excp_model =3D=3D POWERPC_EXCP_POWER10) { qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n= ", env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 01fa76e4a0..78cd2243f4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -9317,7 +9317,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->radix_page_info =3D &POWER10_radix_page_info; pcc->lrg_decr_bits =3D 56; #endif - pcc->excp_model =3D POWERPC_EXCP_POWER9; + pcc->excp_model =3D POWERPC_EXCP_POWER10; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | --=20 2.23.0