From nobody Tue Feb 10 09:58:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1619808284; cv=none; d=zohomail.com; s=zohoarc; b=WoY0BZQOtwLGB+gmyq7VGcp6EHa6KkfTFC68FSc5zZ7M8xNkema1SD9+Pm+DYb5Bskg/SGsPVFekh0tTzRlJZlK5ew3nV8RhTQ/KdOcYhbaDYCLrAldInaX//ZsvtY0YX/lcO8jx5de7GMqURsRrKHaBpuXOVM2ELkk9KGUGJeE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619808284; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=0CKsRh8DU8qLkTGKv2W2N+up7CqCR6p207jvxrv7zps=; b=Q0PzAWUMIFTgc4TpIXA2cpZLEGFwrmPFmspMjkV7p53PVrkh2JuqyP1iSY1T3jKqAAmk90KiRz17iMqSk3iT301QrCl7MLYIhgzhxq4uv+3+UkR7claR3zG1KrguZvzBUwGwIvtCc1xMnrJ0JkRHB9ptu6nW+E+MWg1QoHi5i1g= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619808284367663.0863241481943; Fri, 30 Apr 2021 11:44:44 -0700 (PDT) Received: from localhost ([::1]:50402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcY82-0000D4-T4 for importer@patchew.org; Fri, 30 Apr 2021 14:44:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcY4m-0006Ih-ID; Fri, 30 Apr 2021 14:41:20 -0400 Received: from [201.28.113.2] (port=4684 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcY4j-0002GC-L5; Fri, 30 Apr 2021 14:41:20 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Fri, 30 Apr 2021 15:41:09 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id D3B818013C2; Fri, 30 Apr 2021 15:41:09 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH v2 2/2] hw/ppc: Moved TCG code to spapr_hcall_tcg Date: Fri, 30 Apr 2021 15:40:47 -0300 Message-Id: <20210430184047.81653-3-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430184047.81653-1-lucas.araujo@eldorado.org.br> References: <20210430184047.81653-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 30 Apr 2021 18:41:10.0006 (UTC) FILETIME=[636A1160:01D73DF0] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, "Lucas Mateus Castro \(alqotel\)" , farosas@linux.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Moved h_enter, remove_hpte, h_remove, h_bulk_remove,h_protect and h_read to spapr_hcall_tcg.c, added h_tcg_only to be used in a !TCG environment in spapr_hcall.c and changed build options to only build spapr_hcall_tcg.c when CONFIG_TCG is enabled. Added the function h_tcg_only to be used for hypercalls that should be called only in TCG environment but have been called in a TCG-less one. Right now, a #ifndef is used to know if there is a need of a h_tcg_only function to be implemented and used as hypercalls, I initially thought of always having that option turned on and having spapr_hcall_tcg.c overwrite those hypercalls when TCG is enabled, but spapr_register_hypercalls checks if a hypercall already exists for that opcode so that wouldn't work, so if anyone has any suggestions I'm interested. Also spapr_hcall_tcg.c only has 2 duplicated functions (valid_ptex and is_ram_address), what is the advised way to deal with these duplications? Signed-off-by: Lucas Mateus Castro (alqotel) --- hw/ppc/meson.build | 3 + hw/ppc/spapr_hcall.c | 300 ++-------------------------------- hw/ppc/spapr_hcall_tcg.c | 343 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 363 insertions(+), 283 deletions(-) create mode 100644 hw/ppc/spapr_hcall_tcg.c diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 218631c883..3c7f2f08b7 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -29,6 +29,9 @@ ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files( 'spapr_numa.c', 'pef.c', )) +ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_TCG'], if_true: files( + 'spapr_hcall_tcg.c' +)) ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c')) ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_LINUX'], if_true: files( 'spapr_pci_vfio.c', diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 4b0ba69841..b37fbdc32e 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -22,6 +22,15 @@ #include "mmu-book3s-v3.h" #include "hw/mem/memory-device.h" =20 +#ifndef CONFIG_TCG +static target_ulong h_tcg_only(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + g_assert_not_reached(); + return 0; +} +#endif /* !CONFIG_TCG */ + static bool has_spr(PowerPCCPU *cpu, int spr) { /* We can test whether the SPR is defined by checking for a valid name= */ @@ -55,284 +64,6 @@ static bool is_ram_address(SpaprMachineState *spapr, hw= addr addr) return false; } =20 -static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, - target_ulong opcode, target_ulong *args) -{ - target_ulong flags =3D args[0]; - target_ulong ptex =3D args[1]; - target_ulong pteh =3D args[2]; - target_ulong ptel =3D args[3]; - unsigned apshift; - target_ulong raddr; - target_ulong slot; - const ppc_hash_pte64_t *hptes; - - apshift =3D ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); - if (!apshift) { - /* Bad page size encoding */ - return H_PARAMETER; - } - - raddr =3D (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); - - if (is_ram_address(spapr, raddr)) { - /* Regular RAM - should have WIMG=3D0010 */ - if ((ptel & HPTE64_R_WIMG) !=3D HPTE64_R_M) { - return H_PARAMETER; - } - } else { - target_ulong wimg_flags; - /* Looks like an IO address */ - /* FIXME: What WIMG combinations could be sensible for IO? - * For now we allow WIMG=3D010x, but are there others? */ - /* FIXME: Should we check against registered IO addresses? */ - wimg_flags =3D (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); - - if (wimg_flags !=3D HPTE64_R_I && - wimg_flags !=3D (HPTE64_R_I | HPTE64_R_M)) { - return H_PARAMETER; - } - } - - pteh &=3D ~0x60ULL; - - if (!valid_ptex(cpu, ptex)) { - return H_PARAMETER; - } - - slot =3D ptex & 7ULL; - ptex =3D ptex & ~7ULL; - - if (likely((flags & H_EXACT) =3D=3D 0)) { - hptes =3D ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); - for (slot =3D 0; slot < 8; slot++) { - if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { - break; - } - } - ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); - if (slot =3D=3D 8) { - return H_PTEG_FULL; - } - } else { - hptes =3D ppc_hash64_map_hptes(cpu, ptex + slot, 1); - if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { - ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); - return H_PTEG_FULL; - } - ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); - } - - spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); - - args[0] =3D ptex + slot; - return H_SUCCESS; -} - -typedef enum { - REMOVE_SUCCESS =3D 0, - REMOVE_NOT_FOUND =3D 1, - REMOVE_PARM =3D 2, - REMOVE_HW =3D 3, -} RemoveResult; - -static RemoveResult remove_hpte(PowerPCCPU *cpu - , target_ulong ptex, - target_ulong avpn, - target_ulong flags, - target_ulong *vp, target_ulong *rp) -{ - const ppc_hash_pte64_t *hptes; - target_ulong v, r; - - if (!valid_ptex(cpu, ptex)) { - return REMOVE_PARM; - } - - hptes =3D ppc_hash64_map_hptes(cpu, ptex, 1); - v =3D ppc_hash64_hpte0(cpu, hptes, 0); - r =3D ppc_hash64_hpte1(cpu, hptes, 0); - ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); - - if ((v & HPTE64_V_VALID) =3D=3D 0 || - ((flags & H_AVPN) && (v & ~0x7fULL) !=3D avpn) || - ((flags & H_ANDCOND) && (v & avpn) !=3D 0)) { - return REMOVE_NOT_FOUND; - } - *vp =3D v; - *rp =3D r; - spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); - ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); - return REMOVE_SUCCESS; -} - -static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, - target_ulong opcode, target_ulong *args) -{ - CPUPPCState *env =3D &cpu->env; - target_ulong flags =3D args[0]; - target_ulong ptex =3D args[1]; - target_ulong avpn =3D args[2]; - RemoveResult ret; - - ret =3D remove_hpte(cpu, ptex, avpn, flags, - &args[0], &args[1]); - - switch (ret) { - case REMOVE_SUCCESS: - check_tlb_flush(env, true); - return H_SUCCESS; - - case REMOVE_NOT_FOUND: - return H_NOT_FOUND; - - case REMOVE_PARM: - return H_PARAMETER; - - case REMOVE_HW: - return H_HARDWARE; - } - - g_assert_not_reached(); -} - -#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL -#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL -#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL -#define H_BULK_REMOVE_END 0xc000000000000000ULL -#define H_BULK_REMOVE_CODE 0x3000000000000000ULL -#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL -#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL -#define H_BULK_REMOVE_PARM 0x2000000000000000ULL -#define H_BULK_REMOVE_HW 0x3000000000000000ULL -#define H_BULK_REMOVE_RC 0x0c00000000000000ULL -#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL -#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL -#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL -#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL -#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL - -#define H_BULK_REMOVE_MAX_BATCH 4 - -static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spap= r, - target_ulong opcode, target_ulong *args) -{ - CPUPPCState *env =3D &cpu->env; - int i; - target_ulong rc =3D H_SUCCESS; - - for (i =3D 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { - target_ulong *tsh =3D &args[i*2]; - target_ulong tsl =3D args[i*2 + 1]; - target_ulong v, r, ret; - - if ((*tsh & H_BULK_REMOVE_TYPE) =3D=3D H_BULK_REMOVE_END) { - break; - } else if ((*tsh & H_BULK_REMOVE_TYPE) !=3D H_BULK_REMOVE_REQUEST)= { - return H_PARAMETER; - } - - *tsh &=3D H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; - *tsh |=3D H_BULK_REMOVE_RESPONSE; - - if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN))= { - *tsh |=3D H_BULK_REMOVE_PARM; - return H_PARAMETER; - } - - ret =3D remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, - (*tsh & H_BULK_REMOVE_FLAGS) >> 26, - &v, &r); - - *tsh |=3D ret << 60; - - switch (ret) { - case REMOVE_SUCCESS: - *tsh |=3D (r & (HPTE64_R_C | HPTE64_R_R)) << 43; - break; - - case REMOVE_PARM: - rc =3D H_PARAMETER; - goto exit; - - case REMOVE_HW: - rc =3D H_HARDWARE; - goto exit; - } - } - exit: - check_tlb_flush(env, true); - - return rc; -} - -static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, - target_ulong opcode, target_ulong *args) -{ - CPUPPCState *env =3D &cpu->env; - target_ulong flags =3D args[0]; - target_ulong ptex =3D args[1]; - target_ulong avpn =3D args[2]; - const ppc_hash_pte64_t *hptes; - target_ulong v, r; - - if (!valid_ptex(cpu, ptex)) { - return H_PARAMETER; - } - - hptes =3D ppc_hash64_map_hptes(cpu, ptex, 1); - v =3D ppc_hash64_hpte0(cpu, hptes, 0); - r =3D ppc_hash64_hpte1(cpu, hptes, 0); - ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); - - if ((v & HPTE64_V_VALID) =3D=3D 0 || - ((flags & H_AVPN) && (v & ~0x7fULL) !=3D avpn)) { - return H_NOT_FOUND; - } - - r &=3D ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | - HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); - r |=3D (flags << 55) & HPTE64_R_PP0; - r |=3D (flags << 48) & HPTE64_R_KEY_HI; - r |=3D flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); - spapr_store_hpte(cpu, ptex, - (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); - ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); - /* Flush the tlb */ - check_tlb_flush(env, true); - /* Don't need a memory barrier, due to qemu's global lock */ - spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); - return H_SUCCESS; -} - -static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, - target_ulong opcode, target_ulong *args) -{ - target_ulong flags =3D args[0]; - target_ulong ptex =3D args[1]; - int i, ridx, n_entries =3D 1; - const ppc_hash_pte64_t *hptes; - - if (!valid_ptex(cpu, ptex)) { - return H_PARAMETER; - } - - if (flags & H_READ_4) { - /* Clear the two low order bits */ - ptex &=3D ~(3ULL); - n_entries =3D 4; - } - - hptes =3D ppc_hash64_map_hptes(cpu, ptex, n_entries); - for (i =3D 0, ridx =3D 0; i < n_entries; i++) { - args[ridx++] =3D ppc_hash64_hpte0(cpu, hptes, i); - args[ridx++] =3D ppc_hash64_hpte1(cpu, hptes, i); - } - ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); - - return H_SUCCESS; -} - struct SpaprPendingHpt { /* These fields are read-only after initialization */ int shift; @@ -2021,14 +1752,17 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, targe= t_ulong opcode, =20 static void hypercall_register_types(void) { + +#ifndef CONFIG_TCG /* hcall-pft */ - spapr_register_hypercall(H_ENTER, h_enter); - spapr_register_hypercall(H_REMOVE, h_remove); - spapr_register_hypercall(H_PROTECT, h_protect); - spapr_register_hypercall(H_READ, h_read); + spapr_register_hypercall(H_ENTER, h_tcg_only); + spapr_register_hypercall(H_REMOVE, h_tcg_only); + spapr_register_hypercall(H_PROTECT, h_tcg_only); + spapr_register_hypercall(H_READ, h_tcg_only); =20 /* hcall-bulk */ - spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); + spapr_register_hypercall(H_BULK_REMOVE, h_tcg_only); +#endif /* !CONFIG_TCG */ =20 /* hcall-hpt-resize */ spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); diff --git a/hw/ppc/spapr_hcall_tcg.c b/hw/ppc/spapr_hcall_tcg.c new file mode 100644 index 0000000000..92ff24c8dc --- /dev/null +++ b/hw/ppc/spapr_hcall_tcg.c @@ -0,0 +1,343 @@ +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "sysemu/hw_accel.h" +#include "sysemu/runstate.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "helper_regs.h" +#include "hw/ppc/spapr.h" +#include "hw/ppc/spapr_cpu_core.h" +#include "mmu-hash64.h" +#include "mmu-misc.h" +#include "cpu-models.h" +#include "trace.h" +#include "kvm_ppc.h" +#include "hw/ppc/fdt.h" +#include "hw/ppc/spapr_ovec.h" +#include "mmu-book3s-v3.h" +#include "hw/mem/memory-device.h" + +static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) +{ + /* + * hash value/pteg group index is normalized by HPT mask + */ + if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { + return false; + } + return true; +} + +static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) +{ + MachineState *machine =3D MACHINE(spapr); + DeviceMemoryState *dms =3D machine->device_memory; + + if (addr < machine->ram_size) { + return true; + } + if ((addr >=3D dms->base) + && ((addr - dms->base) < memory_region_size(&dms->mr))) { + return true; + } + + return false; +} + +static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong ptex =3D args[1]; + target_ulong pteh =3D args[2]; + target_ulong ptel =3D args[3]; + unsigned apshift; + target_ulong raddr; + target_ulong slot; + const ppc_hash_pte64_t *hptes; + + apshift =3D ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); + if (!apshift) { + /* Bad page size encoding */ + return H_PARAMETER; + } + + raddr =3D (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); + + if (is_ram_address(spapr, raddr)) { + /* Regular RAM - should have WIMG=3D0010 */ + if ((ptel & HPTE64_R_WIMG) !=3D HPTE64_R_M) { + return H_PARAMETER; + } + } else { + target_ulong wimg_flags; + /* Looks like an IO address */ + /* FIXME: What WIMG combinations could be sensible for IO? + * For now we allow WIMG=3D010x, but are there others? */ + /* FIXME: Should we check against registered IO addresses? */ + wimg_flags =3D (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); + + if (wimg_flags !=3D HPTE64_R_I && + wimg_flags !=3D (HPTE64_R_I | HPTE64_R_M)) { + return H_PARAMETER; + } + } + + pteh &=3D ~0x60ULL; + + if (!valid_ptex(cpu, ptex)) { + return H_PARAMETER; + } + + slot =3D ptex & 7ULL; + ptex =3D ptex & ~7ULL; + + if (likely((flags & H_EXACT) =3D=3D 0)) { + hptes =3D ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); + for (slot =3D 0; slot < 8; slot++) { + if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { + break; + } + } + ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); + if (slot =3D=3D 8) { + return H_PTEG_FULL; + } + } else { + hptes =3D ppc_hash64_map_hptes(cpu, ptex + slot, 1); + if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { + ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); + return H_PTEG_FULL; + } + ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); + } + + spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); + + args[0] =3D ptex + slot; + return H_SUCCESS; +} + +typedef enum { + REMOVE_SUCCESS =3D 0, + REMOVE_NOT_FOUND =3D 1, + REMOVE_PARM =3D 2, + REMOVE_HW =3D 3, +} RemoveResult; + +static RemoveResult remove_hpte(PowerPCCPU *cpu + , target_ulong ptex, + target_ulong avpn, + target_ulong flags, + target_ulong *vp, target_ulong *rp) +{ + const ppc_hash_pte64_t *hptes; + target_ulong v, r; + + if (!valid_ptex(cpu, ptex)) { + return REMOVE_PARM; + } + + hptes =3D ppc_hash64_map_hptes(cpu, ptex, 1); + v =3D ppc_hash64_hpte0(cpu, hptes, 0); + r =3D ppc_hash64_hpte1(cpu, hptes, 0); + ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); + + if ((v & HPTE64_V_VALID) =3D=3D 0 || + ((flags & H_AVPN) && (v & ~0x7fULL) !=3D avpn) || + ((flags & H_ANDCOND) && (v & avpn) !=3D 0)) { + return REMOVE_NOT_FOUND; + } + *vp =3D v; + *rp =3D r; + spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); + ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); + return REMOVE_SUCCESS; +} + +static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + target_ulong ptex =3D args[1]; + target_ulong avpn =3D args[2]; + RemoveResult ret; + + ret =3D remove_hpte(cpu, ptex, avpn, flags, + &args[0], &args[1]); + + switch (ret) { + case REMOVE_SUCCESS: + check_tlb_flush(env, true); + return H_SUCCESS; + + case REMOVE_NOT_FOUND: + return H_NOT_FOUND; + + case REMOVE_PARM: + return H_PARAMETER; + + case REMOVE_HW: + return H_HARDWARE; + } + + g_assert_not_reached(); +} + +#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL +#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL +#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL +#define H_BULK_REMOVE_END 0xc000000000000000ULL +#define H_BULK_REMOVE_CODE 0x3000000000000000ULL +#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL +#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL +#define H_BULK_REMOVE_PARM 0x2000000000000000ULL +#define H_BULK_REMOVE_HW 0x3000000000000000ULL +#define H_BULK_REMOVE_RC 0x0c00000000000000ULL +#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL +#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL +#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL +#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL +#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL + +#define H_BULK_REMOVE_MAX_BATCH 4 + +static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spap= r, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + int i; + target_ulong rc =3D H_SUCCESS; + + for (i =3D 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { + target_ulong *tsh =3D &args[i*2]; + target_ulong tsl =3D args[i*2 + 1]; + target_ulong v, r, ret; + + if ((*tsh & H_BULK_REMOVE_TYPE) =3D=3D H_BULK_REMOVE_END) { + break; + } else if ((*tsh & H_BULK_REMOVE_TYPE) !=3D H_BULK_REMOVE_REQUEST)= { + return H_PARAMETER; + } + + *tsh &=3D H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; + *tsh |=3D H_BULK_REMOVE_RESPONSE; + + if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN))= { + *tsh |=3D H_BULK_REMOVE_PARM; + return H_PARAMETER; + } + + ret =3D remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, + (*tsh & H_BULK_REMOVE_FLAGS) >> 26, + &v, &r); + + *tsh |=3D ret << 60; + + switch (ret) { + case REMOVE_SUCCESS: + *tsh |=3D (r & (HPTE64_R_C | HPTE64_R_R)) << 43; + break; + + case REMOVE_PARM: + rc =3D H_PARAMETER; + goto exit; + + case REMOVE_HW: + rc =3D H_HARDWARE; + goto exit; + } + } + exit: + check_tlb_flush(env, true); + + return rc; +} + +static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + target_ulong ptex =3D args[1]; + target_ulong avpn =3D args[2]; + const ppc_hash_pte64_t *hptes; + target_ulong v, r; + + if (!valid_ptex(cpu, ptex)) { + return H_PARAMETER; + } + + hptes =3D ppc_hash64_map_hptes(cpu, ptex, 1); + v =3D ppc_hash64_hpte0(cpu, hptes, 0); + r =3D ppc_hash64_hpte1(cpu, hptes, 0); + ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); + + if ((v & HPTE64_V_VALID) =3D=3D 0 || + ((flags & H_AVPN) && (v & ~0x7fULL) !=3D avpn)) { + return H_NOT_FOUND; + } + + r &=3D ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | + HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); + r |=3D (flags << 55) & HPTE64_R_PP0; + r |=3D (flags << 48) & HPTE64_R_KEY_HI; + r |=3D flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); + spapr_store_hpte(cpu, ptex, + (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); + ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); + /* Flush the tlb */ + check_tlb_flush(env, true); + /* Don't need a memory barrier, due to qemu's global lock */ + spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); + return H_SUCCESS; +} + +static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong ptex =3D args[1]; + int i, ridx, n_entries =3D 1; + const ppc_hash_pte64_t *hptes; + + if (!valid_ptex(cpu, ptex)) { + return H_PARAMETER; + } + + if (flags & H_READ_4) { + /* Clear the two low order bits */ + ptex &=3D ~(3ULL); + n_entries =3D 4; + } + + hptes =3D ppc_hash64_map_hptes(cpu, ptex, n_entries); + for (i =3D 0, ridx =3D 0; i < n_entries; i++) { + args[ridx++] =3D ppc_hash64_hpte0(cpu, hptes, i); + args[ridx++] =3D ppc_hash64_hpte1(cpu, hptes, i); + } + ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); + + return H_SUCCESS; +} + + +static void hypercall_register_types(void) +{ + /* hcall-pft */ + spapr_register_hypercall(H_ENTER, h_enter); + spapr_register_hypercall(H_REMOVE, h_remove); + spapr_register_hypercall(H_PROTECT, h_protect); + spapr_register_hypercall(H_READ, h_read); + + /* hcall-bulk */ + spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); +} + +type_init(hypercall_register_types) --=20 2.17.1