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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GPn2l19Tl97twEGYdelqET0yx7jf0VXXEvaoWPFd1+c=; b=scn6RxAs73iH840hhFAZQRgVRIU6uz48PNS+th+aQ+B5Jq0oux5SFB8htU5RsJfmfz vxvZiDm0S+hON4WCtEexzJiVCExvDVhGqUXP/+ZCh6UY0JRjErKu0iDVAf03xgAd3gy2 BC0ye6eahaxnZcIMd2NV6mULBCieTLNWInkL2Pl7RD+MxBKF/wVOLzksABVYsXgzscTb vxCmqp/4xdqoHfF2vnJ/yD823dXfFh7j2bUOxT1SkJIYSznqDlhdzQGAUgu1++lT0kpa Zzoi+keuFF8QcW/HhEp4U7TxLVSpB8FoplyV+nt3+KL5l88UsvZJPGPa66KKD0YVylJX s9Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GPn2l19Tl97twEGYdelqET0yx7jf0VXXEvaoWPFd1+c=; b=F91XbK487mFt0jy4aKf1WbUmTvO52rbDywg/Skjr/KeXtT9OFv4vAsGvdmBDpI4Jsh TvZHSbQdn+8oShgBQ/7B8njkQkuics1oDriA/jU54I5IeF7fa37JdiNABMC5ZqXZGQjd /r86h6woFl+MqItxED90Yjv9ziWdy9ANaq9xGbPKD210rXCyIeDqpRNyrnyqmrdGo0c4 FWE7bWV6C3kT5TJj4/VrCeZRglx5dRjHbFQPFNedN9fESMUbclXrZbwyiUqoHGwqqdQ6 yeCvQj45WnFguPbNcg5YfP1BkHpW1g6A3EeFDRUs6jReUWLUiEZZnDI22x2f+pDH1/f9 X+dA== X-Gm-Message-State: AOAM5330rZTosySWkLw6ipPS9fdWjZ4RfucEFzAmT2fEyfZIb3ZPX281 htMowHolAQetAc5+anEqdyeIm3wAXTUaJfPm X-Google-Smtp-Source: ABdhPJzIvtUF+MZvA8F//80+cGKzLSCfvLpk5qG36aJSCI67EbBF+jZUxt9x5SXj8LDomFiviDOP+w== X-Received: by 2002:a5d:6510:: with SMTP id x16mr6939384wru.345.1619789267298; Fri, 30 Apr 2021 06:27:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Date: Fri, 30 Apr 2021 14:27:32 +0100 Message-Id: <20210430132740.10391-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the various gen_aa32* functions and macros out of translate.c and into translate-a32.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 51 ++++++++++++------------------------ 2 files changed, 69 insertions(+), 35 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index cb451f70a42..522aa83636a 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -57,4 +57,57 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } =20 +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc); + +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ + } + +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } + +static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index) +{ + gen_aa32_ld_i64(s, val, a32, index, MO_Q); +} + +static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index) +{ + gen_aa32_st_i64(s, val, a32, index, MO_Q); +} + +DO_GEN_LD(8u, MO_UB) +DO_GEN_LD(16u, MO_UW) +DO_GEN_LD(32u, MO_UL) +DO_GEN_ST(8, MO_UB) +DO_GEN_ST(16, MO_UW) +DO_GEN_ST(32, MO_UL) + +#undef DO_GEN_LD +#undef DO_GEN_ST + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 46f6dfcf421..5113cd2fea6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -899,24 +899,24 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a= 32, MemOp op) * Internal routines are used for NEON cases where the endianness * and/or alignment has already been taken into account and manipulated. */ -static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); tcg_temp_free(addr); } =20 -static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); tcg_temp_free(addr); } =20 -static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); =20 @@ -929,8 +929,8 @@ static void gen_aa32_ld_internal_i64(DisasContext *s, T= CGv_i64 val, tcg_temp_free(addr); } =20 -static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); =20 @@ -946,26 +946,26 @@ static void gen_aa32_st_internal_i64(DisasContext *s,= TCGv_i64 val, tcg_temp_free(addr); } =20 -static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 -static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); } =20 -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); } @@ -984,25 +984,6 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 = val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } =20 -static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index) -{ - gen_aa32_ld_i64(s, val, a32, index, MO_Q); -} - -static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index) -{ - gen_aa32_st_i64(s, val, a32, index, MO_Q); -} - -DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16u, MO_UW) -DO_GEN_LD(32u, MO_UL) -DO_GEN_ST(8, MO_UB) -DO_GEN_ST(16, MO_UW) -DO_GEN_ST(32, MO_UL) - static inline void gen_hvc(DisasContext *s, int imm16) { /* The pre HVC helper handles cases when HVC gets trapped --=20 2.20.1