From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619789801; cv=none; d=zohomail.com; s=zohoarc; b=hb+LNyDKczyPv069+evxB+/DhE3x1M9SAglDxWoyCKPj2cTVfrVkM6gDM9Rkdsrp2qL+J1wgQgqesOFaLY/BXrzYdTVHNudrKw54Ri7bLs1Pso5rrJN7WV+B8MkfkSziSi5q3Bl8XCCMPCImvcg7cEjuwrfwCVmGiPfXLYOpS2Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619789801; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hxR9cUBcBhIKjsbBPEpzkOhwLX13m2fjTkIEHgCHVJk=; b=hTUc6JUiU1/M+h4ALBWmOMPkcrLSXBB6cohjup94rMHnTYchrTHVUGH7kGholj+m9R1LzaRN+Ae4+A5CTfwXCrPxdAySs5/gzOU9BVT1wuhVQcNqZuihtdZR8RtGU8MMHsvkvIDGtCRa6DF9zNaeFOyTsZIW5k7fzsWuKkOM8S4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619789801328185.0678704204431; Fri, 30 Apr 2021 06:36:41 -0700 (PDT) Received: from localhost ([::1]:55534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcTJw-0005ik-9b for importer@patchew.org; Fri, 30 Apr 2021 09:36:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBa-0005qM-CH for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:02 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:38692) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBN-0003tu-A5 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:02 -0400 Received: by mail-wm1-x32d.google.com with SMTP id p6-20020a05600c3586b029014131bbe5c7so1714199wmq.3 for ; Fri, 30 Apr 2021 06:27:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hxR9cUBcBhIKjsbBPEpzkOhwLX13m2fjTkIEHgCHVJk=; b=WWgViwDxUXqjRLxXoeHVHiCS3uGu+AnvkeT+YqsrJYAd/E5QABqOjACau4Be66Q7xT y3xTZ9CREUnlGZ7PmyPd8ODNLcenmlgOUPJDwv5aXJIqo7+EbiZiU44HAkJKFV4BDFbp KyYBpjcRUXYktW5u9LoqCD1lj39BUEcrLJzQWq4ZyBSfj2dVNOMlrzjGGSRi+4oHG495 orRBLr+I1DATqIB8QJkcjld/rxp6VY40gSuL+nHRznUoCkd+0CEslgJhZh97EZm7E4ni gyIxUJFaNtSAmBKkxIVj/tkVZYLHT9HUJL1Gch/iy2cK5wrhaUtRWsJfKrsFlocHB1vf E6Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hxR9cUBcBhIKjsbBPEpzkOhwLX13m2fjTkIEHgCHVJk=; b=j+UXycu8UQKrtyMW+EyPH51psVPztxdXTEgqTpRwoE3Qd/2VuM+lav3Td7TRyLCPmO fPaaWVc1R1FsK1/4GfCULFdtv/iyDXF80LqZfSz30BlEfjZI3s5xsT+n+B2vWqJw1ram /Jk4wX3Fr508jvDnpisI8wRG2hipLaj9u62MtbKh1HwPzLFBwsbxaGsrxAMrB9xFne74 9XPa6orBC7CQFSCsDa+ozVRpYTzYRfm4Sbm1udWTpVZdBO3lp5OWWiVBdrpyZJBbtwRS 17NtM96Y9iXTclxWIl4s964PkLZ+6ozf5djtuYcpq2rX07uc10uqbiYYDxmEyr3mB+io Uqqw== X-Gm-Message-State: AOAM532jq28d38WzdgoFvXJ17ge2b05iOyB6/HywHTE+JoLAZ6fOtG36 ZqzswsmZou7h01qTUpFv97nMZkR2dbOy0rSm X-Google-Smtp-Source: ABdhPJz0Sa1I1XDsddTOl4SR2e9lzn5Wom4TyVIW95yg+ZmwOmKiGllUkRr0yB1ehod0/omS0BRf8Q== X-Received: by 2002:a05:600c:2148:: with SMTP id v8mr6189168wml.35.1619789263289; Fri, 30 Apr 2021 06:27:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 01/13] target/arm: Move constant expanders to translate.h Date: Fri, 30 Apr 2021 14:27:28 +0100 Message-Id: <20210430132740.10391-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Some of the constant expanders defined in translate.c are generically useful and will be used by the separate C files for VFP and Neon once they are created; move the expander definitions to translate.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate.h | 24 ++++++++++++++++++++++++ target/arm/translate.c | 24 ------------------------ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index ccf60c96d84..b5b21619597 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -118,6 +118,30 @@ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; =20 +/* + * Constant expanders for the decoders. + */ + +static inline int negate(DisasContext *s, int x) +{ + return -x; +} + +static inline int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + +static inline int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +static inline int times_4(DisasContext *s, int x) +{ + return x * 4; +} + static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) !=3D 0; diff --git a/target/arm/translate.c b/target/arm/translate.c index 43ff0d4b8ac..bb9e228d1ae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -109,30 +109,6 @@ static void arm_gen_condlabel(DisasContext *s) } } =20 -/* - * Constant expanders for the decoders. - */ - -static int negate(DisasContext *s, int x) -{ - return -x; -} - -static int plus_2(DisasContext *s, int x) -{ - return x + 2; -} - -static int times_2(DisasContext *s, int x) -{ - return x * 2; -} - -static int times_4(DisasContext *s, int x) -{ - return x * 4; -} - /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619792351; cv=none; d=zohomail.com; s=zohoarc; b=TCqLuFa6ZBcLhDtxEo3uJStULmZxTlu7R5iBtfbhugT5ciyU5jU/owT5CJyE74CpDPB7iMS2bSxmXKqDucZ/gtbv0EDbW/akGliKHLIFiASvNCaUyF9SESDKDLHoJWQzTTJLH4DwsT1Yu09Fz/619a7PSUMLwQiVHDIgR017wSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619792351; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LA2eurpLZvepeE69bD/NPo68d8WcE+ltuZoI9EZRHvU=; b=lTtRLaHD4mSz0M3uedYdv2xMuNi/5RL+9l6DSGkVDaJ++HcQQTaFP7bJ18i/U5tsoVkD/f0MpC9Ln7ycb7TouW9Vr+B8pCH2xyDd9zOdg1lfbXtNABvjzJvWo2xLOmJtgu8p008zG5uHQt62jF2k+M6S8IJLIin+1mtgOQ6IHuo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619792351951917.8055751950417; Fri, 30 Apr 2021 07:19:11 -0700 (PDT) Received: from localhost ([::1]:47964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcTz4-0008N6-VC for importer@patchew.org; Fri, 30 Apr 2021 10:19:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40368) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBa-0005rY-QN for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:02 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35331) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBL-0003tz-Nq for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:02 -0400 Received: by mail-wr1-x431.google.com with SMTP id a4so70614884wrr.2 for ; Fri, 30 Apr 2021 06:27:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LA2eurpLZvepeE69bD/NPo68d8WcE+ltuZoI9EZRHvU=; b=Mwxtwb7aH4rTQFU5twcV9oMaq3Dyug9b+ZWnl4w4CEf5GV608e6Sdnd50YwXA7NoND 2rhdE69hxehEnxd75oAhpWLkLt1SOZUfog0iiLl98X3sodqW5hi/dO4g76PKicrODFvQ D87ACMsraPCXbhz1DUaOgXgxIMqWE9lbl1S1qEa1cZRn/trVFZksvY8aK8ndnD3edSeX 71NZ1dwpqpeSnsR8BHQwOs2ryZtt20GsK8O2qOBHpH3GuiZUlNugncYrCOT51+vEBcPU HQS9JejRQYtVE1LRaqjG2oQYRcxV60HV88daiJDW7N/BuBxlHpNn74LG2/gWNtRP0f6X ALaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LA2eurpLZvepeE69bD/NPo68d8WcE+ltuZoI9EZRHvU=; b=n8yJa3a2ymxRhErCeWySibDdF1SRN/9iSeiJjKRWkm0xi5o/X1PGjRAOq1hk7TrNrg qpxu8k8Z2gByvQbRtdKY1W5BqwnWvdwKcz/9PNJLdQMIIou3BsDMg5lyOLPmG8BKJwLa 0w6SbE1NFz5rOWuxO2WkGhIRsJPXmMlGkAvKywjKI5zLpry1o2Aus8xwXyXYFUey7ON9 YLooNtq36T81MZHFc/Lto2ZNbs7a8vvPbkEhnq8LoiTHZM3jOminiwlxtVrpUdPEPBtG XmzV14Ci9gNvPZwyE+5Vi3K4v4DJrURbtvuo4NQpABdbMt00infxDXNa9jrBkFhr+8m9 nkHQ== X-Gm-Message-State: AOAM532FGJIFYqYJCpxrwfSIfp4eB1WPh8MQc9NsFNv0PTYD+Y9FDyRf xubMnaFW0/fZdt081sJB4alP3xY1DHQPl7hV X-Google-Smtp-Source: ABdhPJy5s5c8SsYZgjM8ot0ddWk3O3AVLRnXMAqW1OxscEKZuEfApZsk7M9zt94TWSHR9mmGB8bfKA== X-Received: by 2002:a05:6000:1547:: with SMTP id 7mr6953457wry.388.1619789263963; Fri, 30 Apr 2021 06:27:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 02/13] target/arm: Share unallocated_encoding() and gen_exception_insn() Date: Fri, 30 Apr 2021 14:27:29 +0100 Message-Id: <20210430132740.10391-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The unallocated_encoding() function is the same in both translate-a64.c and translate.c; make the translate.c function global and drop the translate-a64.c version. To do this we need to also share gen_exception_insn(), which currently exists in two slightly different versions for A32 and A64: merge those into a single function that can work for both. This will be useful for splitting up translate.c, which will require unallocated_encoding() to no longer be file-local. It's also hopefully less confusing to have only one version of the function rather than two. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a64.h | 2 -- target/arm/translate.h | 3 +++ target/arm/translate-a64.c | 15 --------------- target/arm/translate.c | 14 +++++++++----- 4 files changed, 12 insertions(+), 22 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 868d3550486..89437276e70 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -18,8 +18,6 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H =20 -void unallocated_encoding(DisasContext *s); - #define unsupported_encoding(s, insn) \ do { \ qemu_log_mask(LOG_UNIMP, \ diff --git a/target/arm/translate.h b/target/arm/translate.h index b5b21619597..8130a3be29d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -229,6 +229,9 @@ void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); +void unallocated_encoding(DisasContext *s); +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el); =20 /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 95897e63af0..0c80d0b5055 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -359,14 +359,6 @@ static void gen_exception_internal_insn(DisasContext *= s, uint64_t pc, int excp) s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syndrome, uint32_t target_el) -{ - gen_a64_set_pc_im(pc); - gen_exception(excp, syndrome, target_el); - s->base.is_jmp =3D DISAS_NORETURN; -} - static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { TCGv_i32 tcg_syn; @@ -437,13 +429,6 @@ static inline void gen_goto_tb(DisasContext *s, int n,= uint64_t dest) } } =20 -void unallocated_encoding(DisasContext *s) -{ - /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); -} - static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG diff --git a/target/arm/translate.c b/target/arm/translate.c index bb9e228d1ae..8b71b1c41b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1069,11 +1069,15 @@ static void gen_exception_internal_insn(DisasContex= t *s, uint32_t pc, int excp) s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp, - int syn, uint32_t target_el) +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el) { - gen_set_condexec(s); - gen_set_pc_im(s, pc); + if (s->aarch64) { + gen_a64_set_pc_im(pc); + } else { + gen_set_condexec(s); + gen_set_pc_im(s, pc); + } gen_exception(excp, syn, target_el); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1090,7 +1094,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, = uint32_t syn) s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void unallocated_encoding(DisasContext *s) +void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Gh79ck4FlFPcKEk1rzUMq0CLfgwlB1dTvg+/l16Ufic=; b=BoHE0kaT7dFEaSAmSVaJjR425Z5SsFYKHR0g2T6aNUOwOSfCDgREEuvltIfp3Uu+/b KVMFr+EOGneAfIDaPs3BeIO49bEkIGJynxgg7lXZ2o6fabt8ETlmElM4X8sK2wYyG81A 7JyFxHuDQqDD5D4lUtoq/aOVdnqO9Dupu0u+nIasvtTmzvRnQuBKZXTz77m9VWeODTr1 00v9uLutEe1rFGLOEtjcHVz0W9cMvZlzAILY8gDrqrYP906K1Z1C935MiJH6tUn8z40Y 5xB6aC8s+dOeed7Oqfo/rjOBM9hFX132rkqXlhbIZeCvwQv74Nzu1UECQS/kS3m8dwn0 bWbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gh79ck4FlFPcKEk1rzUMq0CLfgwlB1dTvg+/l16Ufic=; b=FOsnVdPqcPVnVtNcRzUUXvtNlW/W1+UqeJS60hxljITr2FBoReaSk471PwqmsDqI1+ xx/bQjRxvojXg+sJ6G2NISqHoONwpY00r/hvm2Gda4RJ6FW/D0zBTpTv/4GXz75lBBQd 2vK+L4IQkUuFZZ2UpDKL6G5yBAptYd+ZVUAoSCjXYc8HYnNhcOHO0+ogsJnApsbp2Y7u /RGaJA+6GOo9SNh3qp2FxFj0/ut6WVoxi1m63VMJ20aX/jcAyRkuBIjpzr71FHenlWD0 L2btu54TeUhjkSMsAVOYaLTY1n6raDo6fXIBQGetRxRbh4fd2wonlWD0bJEMiQz8+y2f k+bQ== X-Gm-Message-State: AOAM532jdNaQawDqD7uZOPwty9R6AYjUDFp5V4NhCdTfhSXHsJ5u0hJO rZtI6MHWHx+qRV3flwX5gQw3K8AEKbQtfcfy X-Google-Smtp-Source: ABdhPJxZZdZic5eSJfcOLZ9aaCkNBlgXmD8CWNLVBXNpDHxI0FCToqeOFe+1ojltJJmODKgKiLeonw== X-Received: by 2002:a5d:534d:: with SMTP id t13mr6862799wrv.153.1619789265225; Fri, 30 Apr 2021 06:27:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 03/13] target/arm: Make functions used by m-nocp global Date: Fri, 30 Apr 2021 14:27:30 +0100 Message-Id: <20210430132740.10391-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We want to split out the .c.inc files which are currently included into translate.c so they are separate compilation units. To do this we need to make some functions which are currently file-local to translate.c have global scope; create a translate-a32.h paralleling the existing translate-a64.h as a place for these declarations to live, so that code moved into the new compilation units can call them. The functions made global here are those required by the m-nocp.decode functions, except that I have converted the whole family of {read,write}_neon_element* and also both the load_cpu and store_cpu functions for consistency, even though m-nocp only wants a few functions from each. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 57 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 39 +++++------------------ target/arm/translate-vfp.c.inc | 2 +- 3 files changed, 65 insertions(+), 33 deletions(-) create mode 100644 target/arm/translate-a32.h diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h new file mode 100644 index 00000000000..c5d937b27e8 --- /dev/null +++ b/target/arm/translate-a32.h @@ -0,0 +1,57 @@ +/* + * AArch32 translation, common definitions. + * + * Copyright (c) 2021 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_TRANSLATE_A64_H +#define TARGET_ARM_TRANSLATE_A64_H + +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); +void arm_gen_condlabel(DisasContext *s); +bool vfp_access_check(DisasContext *s); +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); + +static inline TCGv_i32 load_cpu_offset(int offset) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_ld_i32(tmp, cpu_env, offset); + return tmp; +} + +#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) + +static inline void store_cpu_offset(TCGv_i32 var, int offset) +{ + tcg_gen_st_i32(var, cpu_env, offset); + tcg_temp_free_i32(var); +} + +#define store_cpu_field(var, name) \ + store_cpu_offset(var, offsetof(CPUARMState, name)) + +/* Create a new temporary and set it to the value of a CPU register. */ +static inline TCGv_i32 load_reg(DisasContext *s, int reg) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + load_reg_var(s, tmp, reg); + return tmp; +} + +#endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 8b71b1c41b6..3c1d52279bc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -50,6 +50,7 @@ #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 #include "translate.h" +#include "translate-a32.h" =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 @@ -101,7 +102,7 @@ void arm_translate_init(void) } =20 /* Generate a label used for skipping this instruction */ -static void arm_gen_condlabel(DisasContext *s) +void arm_gen_condlabel(DisasContext *s) { if (!s->condjmp) { s->condlabel =3D gen_new_label(); @@ -187,24 +188,6 @@ static inline int get_a32_user_mem_index(DisasContext = *s) } } =20 -static inline TCGv_i32 load_cpu_offset(int offset) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp, cpu_env, offset); - return tmp; -} - -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) - -static inline void store_cpu_offset(TCGv_i32 var, int offset) -{ - tcg_gen_st_i32(var, cpu_env, offset); - tcg_temp_free_i32(var); -} - -#define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUARMState, name)) - /* The architectural value of PC. */ static uint32_t read_pc(DisasContext *s) { @@ -212,7 +195,7 @@ static uint32_t read_pc(DisasContext *s) } =20 /* Set a variable to the value of a CPU register. */ -static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg =3D=3D 15) { tcg_gen_movi_i32(var, read_pc(s)); @@ -221,14 +204,6 @@ static void load_reg_var(DisasContext *s, TCGv_i32 var= , int reg) } } =20 -/* Create a new temporary and set it to the value of a CPU register. */ -static inline TCGv_i32 load_reg(DisasContext *s, int reg) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - load_reg_var(s, tmp, reg); - return tmp; -} - /* * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4). * This is used for load/store for which use of PC implies (literal), @@ -1208,7 +1183,7 @@ static inline void vfp_store_reg32(TCGv_i32 var, int = reg) tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); } =20 -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp mem= op) +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) { long off =3D neon_element_offset(reg, ele, memop); =20 @@ -1234,7 +1209,7 @@ static void read_neon_element32(TCGv_i32 dest, int re= g, int ele, MemOp memop) } } =20 -static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp mem= op) +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) { long off =3D neon_element_offset(reg, ele, memop); =20 @@ -1253,7 +1228,7 @@ static void read_neon_element64(TCGv_i64 dest, int re= g, int ele, MemOp memop) } } =20 -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp mem= op) +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) { long off =3D neon_element_offset(reg, ele, memop); =20 @@ -1272,7 +1247,7 @@ static void write_neon_element32(TCGv_i32 src, int re= g, int ele, MemOp memop) } } =20 -static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp mem= op) +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) { long off =3D neon_element_offset(reg, ele, memop); =20 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index e20d9c7ba66..c368ada877b 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -191,7 +191,7 @@ static bool full_vfp_access_check(DisasContext *s, bool= ignore_vfp_enabled) * The most usual kind of VFP access check, for everything except * FMXR/FMRX to the always-available special registers. */ -static bool vfp_access_check(DisasContext *s) +bool vfp_access_check(DisasContext *s) { return full_vfp_access_check(s, false); } --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=D7FruQvRFHnjz4CtUShCbppChsAJWnZ/hge8TYuS7M8=; b=w0tMj7PQcgzDU3LyCPoqydPyO/Pl0p/0b6O0YJRAtGK4O3sihQEVmvxffQtJbr9Lp3 UCZjiSpMmvLvwhrt+Sj/ij7ZalffWQBFrH0a4OEtQnaKl14p3Sr4VKHKVQDED5hcZyRf JGvsn2wMxZN+GCiO/CUdDBWT+JedTUNb4NJdqu7q2scky4ONuJyCYsIW20kZB1C/Zxd2 r4xtRW3+nb290V8VbWfPlRLoaEAtJVVqWwUHaWqfLV0hJyCcKRGV93sm/z/z6flhYDys iEs/mGwi/LMic8exkeNCmK7Hus73VswZyzOekXXPcV1JnE5Mnnl6w/NuHPI/8buWOQyj 2m5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7FruQvRFHnjz4CtUShCbppChsAJWnZ/hge8TYuS7M8=; b=Rrnk/+TjdtVvjYf8BhHzlu4HdcgJ5opRPUC90ulJD8aeaN5zueGDwTR10atZAPkqwK gtD8Nt+UNNZg//I1F4Ej6MYhw3ahirYmzV2vDZrfYAS195RnJBCyfP1JhSE2jZG7jwNO e9WbqR435CegjbO6JnM8TL65DRCiScXXx9eIqywC1i61+2XcAMymYkULCZcmR7gArb/F 13RzbvQ5HnBT+iu1ks/fhhtqQdPnEaZlBlYRvOZG+bgJAwJGGGwMtn+eOn8ghfcVhMh+ rm1wJc0pC/bRvqvFPuOojTU+r4AB4kV6/qFFK0/lxcBLsw8Bwciky9uRIIT6hd7hNHq7 Mjaw== X-Gm-Message-State: AOAM532dKGNRyAlU+77ndGXmU+8H7MWnEdPq0cMU11qpuzmOgITCcRL3 2Sp2vMjgcse7ch5WqMlnjCUpv90Z42ZrOt38 X-Google-Smtp-Source: ABdhPJwnTKVgSvdbJ7xYKM7wm0f5N1sE46BOqMhlw53ex1PXVLf0UTLSr5g1jJ7mVWAgbaHJ6EbImg== X-Received: by 2002:a5d:498c:: with SMTP id r12mr7079492wrq.31.1619789266174; Fri, 30 Apr 2021 06:27:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 04/13] target/arm: Split m-nocp trans functions into their own file Date: Fri, 30 Apr 2021 14:27:31 +0100 Message-Id: <20210430132740.10391-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently the trans functions for m-nocp.decode all live in translate-vfp.inc.c; move them out into their own translation unit, translate-m-nocp.c. The trans_* functions here are pure code motion with no changes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 3 + target/arm/translate-m-nocp.c | 221 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 1 - target/arm/translate-vfp.c.inc | 196 ----------------------------- target/arm/meson.build | 3 +- 5 files changed, 226 insertions(+), 198 deletions(-) create mode 100644 target/arm/translate-m-nocp.c diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index c5d937b27e8..cb451f70a42 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -20,6 +20,9 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H =20 +/* Prototypes for autogenerated disassembler functions */ +bool disas_m_nocp(DisasContext *dc, uint32_t insn); + void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); void arm_gen_condlabel(DisasContext *s); bool vfp_access_check(DisasContext *s); diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c new file mode 100644 index 00000000000..d47eb8e1535 --- /dev/null +++ b/target/arm/translate-m-nocp.c @@ -0,0 +1,221 @@ +/* + * ARM translation: M-profile NOCP special-case instructions + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "translate.h" +#include "translate-a32.h" + +#include "decode-m-nocp.c.inc" + +/* + * Decode VLLDM and VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that vfp_access_check() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + if (a->op) { + /* + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not + * to take the IMPDEF option to make memory accesses to the stack + * slots that correspond to the D16-D31 registers (discarding + * read data and writing UNKNOWN values), so for us the T2 + * encoding behaves identically to the T1 encoding. + */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + } else { + /* + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. + * This is currently architecturally impossible, but we add the + * check to stay in line with the pseudocode. Note that we must + * emit code for the UNDEF so it takes precedence over the NOCP. + */ + if (dc_isar_feature(aa32_simd_r32, s)) { + unallocated_encoding(s); + return true; + } + } + + /* + * If not secure, UNDEF. We must emit code for this + * rather than returning false so that this takes + * precedence over the m-nocp.decode NOCP fallback. + */ + if (!s->v8m_secure) { + unallocated_encoding(s); + return true; + } + /* If no fpu, NOP. */ + if (!dc_isar_feature(aa32_vfp, s)) { + return true; + } + + fptr =3D load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + return true; +} + +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) +{ + int btmreg, topreg; + TCGv_i64 zero; + TCGv_i32 aspen, sfpa; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + /* Before v8.1M, fall through in decode to NOCP check */ + return false; + } + + /* Explicitly UNDEF because this takes precedence over NOCP */ + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { + unallocated_encoding(s); + return true; + } + + if (!dc_isar_feature(aa32_vfp_simd, s)) { + /* NOP if we have neither FP nor MVE */ + return true; + } + + /* + * If FPCCR.ASPEN !=3D 0 && CONTROL_S.SFPA =3D=3D 0 then there is no + * active floating point context so we must NOP (without doing + * any lazy state preservation or the NOCP check). + */ + aspen =3D load_cpu_field(v7m.fpccr[M_REG_S]); + sfpa =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_or_i32(sfpa, sfpa, aspen); + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); + + if (s->fp_excp_el !=3D 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + topreg =3D a->vd + a->imm - 1; + btmreg =3D a->vd; + + /* Convert to Sreg numbers if the insn specified in Dregs */ + if (a->size =3D=3D 3) { + topreg =3D topreg * 2 + 1; + btmreg *=3D 2; + } + + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { + /* UNPREDICTABLE: we choose to undef */ + unallocated_encoding(s); + return true; + } + + /* Silently ignore requests to clear D16-D31 if they don't exist */ + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { + topreg =3D 31; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Zero the Sregs from btmreg to topreg inclusive. */ + zero =3D tcg_const_i64(0); + if (btmreg & 1) { + write_neon_element64(zero, btmreg >> 1, 1, MO_32); + btmreg++; + } + for (; btmreg + 1 <=3D topreg; btmreg +=3D 2) { + write_neon_element64(zero, btmreg >> 1, 0, MO_64); + } + if (btmreg =3D=3D topreg) { + write_neon_element64(zero, btmreg >> 1, 0, MO_32); + btmreg++; + } + assert(btmreg =3D=3D topreg + 1); + /* TODO: when MVE is implemented, zero VPR here */ + return true; +} + +static bool trans_NOCP(DisasContext *s, arg_nocp *a) +{ + /* + * Handle M-profile early check for disabled coprocessor: + * all we need to do here is emit the NOCP exception if + * the coprocessor is disabled. Otherwise we return false + * and the real VFP/etc decode will handle the insn. + */ + assert(arm_dc_feature(s, ARM_FEATURE_M)); + + if (a->cp =3D=3D 11) { + a->cp =3D 10; + } + if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && + (a->cp =3D=3D 8 || a->cp =3D=3D 9 || a->cp =3D=3D 14 || a->cp =3D= =3D 15)) { + /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ + a->cp =3D 10; + } + + if (a->cp !=3D 10) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), default_exception_el(s)); + return true; + } + + if (s->fp_excp_el !=3D 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + return false; +} + +static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) +{ + /* This range needs a coprocessor check for v8.1M and later only */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + return trans_NOCP(s, a); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 3c1d52279bc..46f6dfcf421 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1273,7 +1273,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) #define ARM_CP_RW_BIT (1 << 20) =20 /* Include the VFP and Neon decoders */ -#include "decode-m-nocp.c.inc" #include "translate-vfp.c.inc" #include "translate-neon.c.inc" =20 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index c368ada877b..500492f02fb 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3800,202 +3800,6 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_= VCVT_dp_int *a) return true; } =20 -/* - * Decode VLLDM and VLSTM are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that vfp_access_check() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ -static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) -{ - TCGv_i32 fptr; - - if (!arm_dc_feature(s, ARM_FEATURE_M) || - !arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - - if (a->op) { - /* - * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not - * to take the IMPDEF option to make memory accesses to the stack - * slots that correspond to the D16-D31 registers (discarding - * read data and writing UNKNOWN values), so for us the T2 - * encoding behaves identically to the T1 encoding. - */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; - } - } else { - /* - * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. - * This is currently architecturally impossible, but we add the - * check to stay in line with the pseudocode. Note that we must - * emit code for the UNDEF so it takes precedence over the NOCP. - */ - if (dc_isar_feature(aa32_simd_r32, s)) { - unallocated_encoding(s); - return true; - } - } - - /* - * If not secure, UNDEF. We must emit code for this - * rather than returning false so that this takes - * precedence over the m-nocp.decode NOCP fallback. - */ - if (!s->v8m_secure) { - unallocated_encoding(s); - return true; - } - /* If no fpu, NOP. */ - if (!dc_isar_feature(aa32_vfp, s)) { - return true; - } - - fptr =3D load_reg(s, a->rn); - if (a->l) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits */ - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - return true; -} - -static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) -{ - int btmreg, topreg; - TCGv_i64 zero; - TCGv_i32 aspen, sfpa; - - if (!dc_isar_feature(aa32_m_sec_state, s)) { - /* Before v8.1M, fall through in decode to NOCP check */ - return false; - } - - /* Explicitly UNDEF because this takes precedence over NOCP */ - if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { - unallocated_encoding(s); - return true; - } - - if (!dc_isar_feature(aa32_vfp_simd, s)) { - /* NOP if we have neither FP nor MVE */ - return true; - } - - /* - * If FPCCR.ASPEN !=3D 0 && CONTROL_S.SFPA =3D=3D 0 then there is no - * active floating point context so we must NOP (without doing - * any lazy state preservation or the NOCP check). - */ - aspen =3D load_cpu_field(v7m.fpccr[M_REG_S]); - sfpa =3D load_cpu_field(v7m.control[M_REG_S]); - tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); - tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); - tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); - tcg_gen_or_i32(sfpa, sfpa, aspen); - arm_gen_condlabel(s); - tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); - - if (s->fp_excp_el !=3D 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); - return true; - } - - topreg =3D a->vd + a->imm - 1; - btmreg =3D a->vd; - - /* Convert to Sreg numbers if the insn specified in Dregs */ - if (a->size =3D=3D 3) { - topreg =3D topreg * 2 + 1; - btmreg *=3D 2; - } - - if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { - /* UNPREDICTABLE: we choose to undef */ - unallocated_encoding(s); - return true; - } - - /* Silently ignore requests to clear D16-D31 if they don't exist */ - if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { - topreg =3D 31; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* Zero the Sregs from btmreg to topreg inclusive. */ - zero =3D tcg_const_i64(0); - if (btmreg & 1) { - write_neon_element64(zero, btmreg >> 1, 1, MO_32); - btmreg++; - } - for (; btmreg + 1 <=3D topreg; btmreg +=3D 2) { - write_neon_element64(zero, btmreg >> 1, 0, MO_64); - } - if (btmreg =3D=3D topreg) { - write_neon_element64(zero, btmreg >> 1, 0, MO_32); - btmreg++; - } - assert(btmreg =3D=3D topreg + 1); - /* TODO: when MVE is implemented, zero VPR here */ - return true; -} - -static bool trans_NOCP(DisasContext *s, arg_nocp *a) -{ - /* - * Handle M-profile early check for disabled coprocessor: - * all we need to do here is emit the NOCP exception if - * the coprocessor is disabled. Otherwise we return false - * and the real VFP/etc decode will handle the insn. - */ - assert(arm_dc_feature(s, ARM_FEATURE_M)); - - if (a->cp =3D=3D 11) { - a->cp =3D 10; - } - if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && - (a->cp =3D=3D 8 || a->cp =3D=3D 9 || a->cp =3D=3D 14 || a->cp =3D= =3D 15)) { - /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ - a->cp =3D 10; - } - - if (a->cp !=3D 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), default_exception_el(s)); - return true; - } - - if (s->fp_excp_el !=3D 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); - return true; - } - - return false; -} - -static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) -{ - /* This range needs a coprocessor check for v8.1M and later only */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; - } - return trans_NOCP(s, a); -} - static bool trans_VINS(DisasContext *s, arg_VINS *a) { TCGv_i32 rd, rm; diff --git a/target/arm/meson.build b/target/arm/meson.build index 15b936c1010..bbee1325bc4 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,7 +5,7 @@ gen =3D [ decodetree.process('neon-ls.decode', extra_args: '--static-decode=3Ddisa= s_neon_ls'), decodetree.process('vfp.decode', extra_args: '--static-decode=3Ddisas_vf= p'), decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=3Dd= isas_vfp_uncond'), - decodetree.process('m-nocp.decode', extra_args: '--static-decode=3Ddisas= _m_nocp'), + decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), @@ -26,6 +26,7 @@ arm_ss.add(files( 'op_helper.c', 'tlb_helper.c', 'translate.c', + 'translate-m-nocp.c', 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619790509; cv=none; d=zohomail.com; s=zohoarc; b=noC14Ct4wltKAGiiE1HF3AESL4MeA0qGrB7LsfAVpSyGSHZj+TeVf+mR/oum7vDoi+G9kMKE866d0GxmPN0MZX9t/aeXEQh/QqLYzpeB6cF8ORERz38Lu/JOo0DYvsSqavrT/ZrB1KFizqwqtFNlMGeO7jHn4B1Xm7BVIfDjXYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619790509; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GPn2l19Tl97twEGYdelqET0yx7jf0VXXEvaoWPFd1+c=; b=QehoI82L/7fd4akltbIx5G4xVCCALEym2FcXbRQJnyFeqhQRhyIzsdiZU2JZ8WYMtlgRx6ZZbI+ezn4GryNth5XqH2qkLBo8uVH8Mfu0LSkaWm7IrfaoPkwGD6mo85gxyU2Q9dWPOZkKS1iKDM01srjZCnNLT1U5/AHwghwS/Y0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619790509735169.11446386218313; Fri, 30 Apr 2021 06:48:29 -0700 (PDT) Received: from localhost ([::1]:59758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcTVM-0003Ff-LQ for importer@patchew.org; Fri, 30 Apr 2021 09:48:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBT-0005m7-GK for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:27:59 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:33391) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBN-0003uV-8y for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:27:55 -0400 Received: by mail-wr1-x42e.google.com with SMTP id n2so17423799wrm.0 for ; Fri, 30 Apr 2021 06:27:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GPn2l19Tl97twEGYdelqET0yx7jf0VXXEvaoWPFd1+c=; b=scn6RxAs73iH840hhFAZQRgVRIU6uz48PNS+th+aQ+B5Jq0oux5SFB8htU5RsJfmfz vxvZiDm0S+hON4WCtEexzJiVCExvDVhGqUXP/+ZCh6UY0JRjErKu0iDVAf03xgAd3gy2 BC0ye6eahaxnZcIMd2NV6mULBCieTLNWInkL2Pl7RD+MxBKF/wVOLzksABVYsXgzscTb vxCmqp/4xdqoHfF2vnJ/yD823dXfFh7j2bUOxT1SkJIYSznqDlhdzQGAUgu1++lT0kpa Zzoi+keuFF8QcW/HhEp4U7TxLVSpB8FoplyV+nt3+KL5l88UsvZJPGPa66KKD0YVylJX s9Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GPn2l19Tl97twEGYdelqET0yx7jf0VXXEvaoWPFd1+c=; b=F91XbK487mFt0jy4aKf1WbUmTvO52rbDywg/Skjr/KeXtT9OFv4vAsGvdmBDpI4Jsh TvZHSbQdn+8oShgBQ/7B8njkQkuics1oDriA/jU54I5IeF7fa37JdiNABMC5ZqXZGQjd /r86h6woFl+MqItxED90Yjv9ziWdy9ANaq9xGbPKD210rXCyIeDqpRNyrnyqmrdGo0c4 FWE7bWV6C3kT5TJj4/VrCeZRglx5dRjHbFQPFNedN9fESMUbclXrZbwyiUqoHGwqqdQ6 yeCvQj45WnFguPbNcg5YfP1BkHpW1g6A3EeFDRUs6jReUWLUiEZZnDI22x2f+pDH1/f9 X+dA== X-Gm-Message-State: AOAM5330rZTosySWkLw6ipPS9fdWjZ4RfucEFzAmT2fEyfZIb3ZPX281 htMowHolAQetAc5+anEqdyeIm3wAXTUaJfPm X-Google-Smtp-Source: ABdhPJzIvtUF+MZvA8F//80+cGKzLSCfvLpk5qG36aJSCI67EbBF+jZUxt9x5SXj8LDomFiviDOP+w== X-Received: by 2002:a5d:6510:: with SMTP id x16mr6939384wru.345.1619789267298; Fri, 30 Apr 2021 06:27:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Date: Fri, 30 Apr 2021 14:27:32 +0100 Message-Id: <20210430132740.10391-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the various gen_aa32* functions and macros out of translate.c and into translate-a32.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 51 ++++++++++++------------------------ 2 files changed, 69 insertions(+), 35 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index cb451f70a42..522aa83636a 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -57,4 +57,57 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } =20 +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc); + +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ + } + +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } + +static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index) +{ + gen_aa32_ld_i64(s, val, a32, index, MO_Q); +} + +static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index) +{ + gen_aa32_st_i64(s, val, a32, index, MO_Q); +} + +DO_GEN_LD(8u, MO_UB) +DO_GEN_LD(16u, MO_UW) +DO_GEN_LD(32u, MO_UL) +DO_GEN_ST(8, MO_UB) +DO_GEN_ST(16, MO_UW) +DO_GEN_ST(32, MO_UL) + +#undef DO_GEN_LD +#undef DO_GEN_ST + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 46f6dfcf421..5113cd2fea6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -899,24 +899,24 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a= 32, MemOp op) * Internal routines are used for NEON cases where the endianness * and/or alignment has already been taken into account and manipulated. */ -static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); tcg_temp_free(addr); } =20 -static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); tcg_temp_free(addr); } =20 -static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); =20 @@ -929,8 +929,8 @@ static void gen_aa32_ld_internal_i64(DisasContext *s, T= CGv_i64 val, tcg_temp_free(addr); } =20 -static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); =20 @@ -946,26 +946,26 @@ static void gen_aa32_st_internal_i64(DisasContext *s,= TCGv_i64 val, tcg_temp_free(addr); } =20 -static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 -static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); } =20 -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); } @@ -984,25 +984,6 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 = val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } =20 -static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index) -{ - gen_aa32_ld_i64(s, val, a32, index, MO_Q); -} - -static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index) -{ - gen_aa32_st_i64(s, val, a32, index, MO_Q); -} - -DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16u, MO_UW) -DO_GEN_LD(32u, MO_UL) -DO_GEN_ST(8, MO_UB) -DO_GEN_ST(16, MO_UW) -DO_GEN_ST(32, MO_UL) - static inline void gen_hvc(DisasContext *s, int imm16) { /* The pre HVC helper handles cases when HVC gets trapped --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JQ7yCHvVyn3dC2kUvL2RqYfRlHX1xoflpJBAYkM3TLA=; b=y54ZNsnY9O53W5w0JG+aV9kqFLYEaq9FODOuL6vj6qDWKjy8pe5rw3XlLudGfMAOaN 2NtmbuNY279kaWDGMBckC+DNg0lcrt00HewNg60EpKy5zwW0LuN6WtUg9+SWly6MJgsd QMYSJfOcCCR0kZrdI1DahGq+TLFUDaGelo6w4J+lJ2bdiEvczxzWkoECi97wc/DzsCYQ Za7UdyfPSekXqVNQaPNH+TUsdY8y/6/I9DcIQ0riLA4ZSlexCmeAmM9RIIfHi+pMGTmi ih7ZGrsJ65oOHXbAJXRQcProyxYN+Ivq/+XwkbjWKkipuuqrWOLVT8DprfFvfnrkAbNm QC6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JQ7yCHvVyn3dC2kUvL2RqYfRlHX1xoflpJBAYkM3TLA=; b=MsfMirdGLNdaLKROgIC5ln+ht6FLq+bzJTsCK7+h7udAGj7zzR8Nte/5A0YTft/yvQ nd5mGS1ZjuzWDHwOTUJgoatRS15syt4lph292M9UZk5dJetWAGdEYbgEeFkFT3c3mkQX eypKaKBL6jzo3T87hlPQNOvemI89a8oh0QmvEdNUZSlGoEiaE8/hcbAeZzmCe021wjxr ztnct/j2yBNvlAIsZ0pCMkh2+RMUTn7BA8exh3S9oMkdscOri86ZDkYn0NqeYHq3vvqg S1XWAGalMKhbPLnwZQteoBBLs2euSsIEX6xgN1fdOrvOzTYX0e9Iz4y1Un/xkerVnl3G jrRA== X-Gm-Message-State: AOAM533Tz8BUG1QOOEBmWBzzSJ6+G7JCuVP9mwx7Y/CsCCRH2zwRrfDY 9a6dt8PWpx7M77pfBThBTpHHAex7mwGvC3SR X-Google-Smtp-Source: ABdhPJzBWB42+H3lp1v51C3ZWwZmdhDk/Kv+OfOZ+UBgwGJMr3fFBJq4tBT1j2BeUdnnqLcSdrCMHQ== X-Received: by 2002:adf:cd8c:: with SMTP id q12mr6933704wrj.328.1619789267929; Fri, 30 Apr 2021 06:27:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc Date: Fri, 30 Apr 2021 14:27:33 +0100 Message-Id: <20210430132740.10391-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() and vfp_store_reg64() are used only in translate-vfp.c.inc. Move them to that file. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate.c | 20 -------------------- target/arm/translate-vfp.c.inc | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5113cd2fea6..c8b9cedfcfd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1144,26 +1144,6 @@ static long vfp_reg_offset(bool dp, unsigned reg) } } =20 -static inline void vfp_load_reg64(TCGv_i64 var, int reg) -{ - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); -} - -static inline void vfp_store_reg64(TCGv_i64 var, int reg) -{ - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); -} - -static inline void vfp_load_reg32(TCGv_i32 var, int reg) -{ - tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); -} - -static inline void vfp_store_reg32(TCGv_i32 var, int reg) -{ - tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); -} - void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) { long off =3D neon_element_offset(reg, ele, memop); diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 500492f02fb..1004d1fd095 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -30,6 +30,26 @@ #include "decode-vfp.c.inc" #include "decode-vfp-uncond.c.inc" =20 +static inline void vfp_load_reg64(TCGv_i64 var, int reg) +{ + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); +} + +static inline void vfp_store_reg64(TCGv_i64 var, int reg) +{ + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); +} + +static inline void vfp_load_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + +static inline void vfp_store_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + /* * The imm8 encodes the sign bit, enough bits to represent an exponent in * the range 01....1xx to 10....0xx, and the most significant 4 bits of --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619792560; cv=none; d=zohomail.com; s=zohoarc; b=K11NzFirNFymXp8NUbUClyugeFW0cFB4ktjNu/LrkeJjUp6MDjK9PimG6p0CZ45P/kMZaLbCfMOQ6gDcbIVn1j2X0or1bAl7cvkTfSA5gFKpnhI9jKhtrDsfu1GQwJAgwS3EjaEzAw3qR82GQDiTFOxR6x6CF0BGwkeIm31+VQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619792560; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WOqjrj/e9xRiNa1HS9aJmQcDMZVyUnFFfhTHfQgPJAA=; b=RKuuNhud4IECaYBxgBUkVI+q6zTdEIrzMxiq70o6AQ8bmCoRTjBPGgtub5nELFVQ9LThmGGSJzJ2p2Gv90fFlD88Nff9pyCZ/2vj74Nf/T0AzNsMcGjUnP9QmFA0HyBgfUt+++tDzR+PLqVon+5VHXUicazy9DbPG7/1WKEN3kI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619792560749420.12195420345427; Fri, 30 Apr 2021 07:22:40 -0700 (PDT) Received: from localhost ([::1]:52858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcU2R-00026t-J7 for importer@patchew.org; Fri, 30 Apr 2021 10:22:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBb-0005uk-S8 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:03 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38809) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBO-0003vK-5x for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:03 -0400 Received: by mail-wr1-x42c.google.com with SMTP id l14so745903wrx.5 for ; Fri, 30 Apr 2021 06:27:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WOqjrj/e9xRiNa1HS9aJmQcDMZVyUnFFfhTHfQgPJAA=; b=ftX3kY7x4nYciFrcfhu2vbj1sqpCyA9QJuVlgly4uKmZOm7m3GVSJNt8GKftbvTInv oTmDTaxCVBLEZGYE7eb0HhMzj89BhJDyZUWtYDEFMhGTQVHxvGQiA5EIByRsWSXXQFf6 PWR3x8bjQIp+M1yrL3iLBb8tiw+2HlgFQzzhYGSUTJmeq/broPP9PjNrLi3RZ4DqS/SR RK5b0Cq7iCM877gLvY3yGx9fblt6fuFw1PJzwW0KO3f8CtImoZoYmVxHS87v2w85HzCP juO589kxIMcM8NA1QQdErWeDs1vPyJrn24U7QYBBdqcNc4tOXFe9TczowWDTt3H4jjmR hECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WOqjrj/e9xRiNa1HS9aJmQcDMZVyUnFFfhTHfQgPJAA=; b=VBIkVClNYFGFvyUCLeC1/VcO//8MGuAS3E5hezChGQj937BvuSIx0G2ercL2twm+iT z0keOOLFV+W18aMVaXtx7fSSgKCpdZy8ivyPbCEmZOgOTJ9KYm/NA+W//hv1ts/8mfA9 s4O0wROTx+9OeBsEWTFTGYTldwk85cKWhlvbB6T+Cl9YwwipiAuKG3Yes+x9kl3+RyKm xq0S9UHo8WUo6m3b4zlks8xsIdA/S452gsd9UeN3DH7jIJq86hRf1Nert9FU62+4EF6W uUWt8f/X7mdC7Ma9oLfCazpDQ3eeK5kOf+K+NUUek6VNUF+9fUAvu/VxgIpnZA0dwbkP ITgQ== X-Gm-Message-State: AOAM532di8eGWGJi/6SYEX5XzGrmFfOQUjvQTj/YUf6W9QcrZPhbzbbY 1wBIKsQ6RS3TT6roDKu4GpKIp7YJv8zgwKiG X-Google-Smtp-Source: ABdhPJzsD9DU3Clfqvw+XTeF7DRXJIT4ILuqLDZMkFNiDW/7OzjUTiV2vPT4wCHhW6IV5hh9fEhR/g== X-Received: by 2002:adf:9d48:: with SMTP id o8mr6838964wre.183.1619789268681; Fri, 30 Apr 2021 06:27:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 07/13] target/arm: Make functions used by translate-vfp global Date: Fri, 30 Apr 2021 14:27:34 +0100 Message-Id: <20210430132740.10391-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Make the remaining functions which are needed by translate-vfp.c.inc global. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v2: made gen_set_cpsr and gen_set_condexec not inline at rth's suggestion --- target/arm/translate-a32.h | 18 ++++++++++++++++++ target/arm/translate.c | 25 ++++++++----------------- 2 files changed, 26 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 522aa83636a..326cbafe996 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -30,6 +30,13 @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele= , MemOp memop); void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); +void gen_set_cpsr(TCGv_i32 var, uint32_t mask); +void gen_set_condexec(DisasContext *s); +void gen_set_pc_im(DisasContext *s, target_ulong val); +void gen_lookup_tb(DisasContext *s); +long vfp_reg_offset(bool dp, unsigned reg); +long neon_full_reg_offset(unsigned reg); =20 static inline TCGv_i32 load_cpu_offset(int offset) { @@ -57,6 +64,8 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } =20 +void store_reg(DisasContext *s, int reg, TCGv_i32 var); + void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc); void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, @@ -110,4 +119,13 @@ DO_GEN_ST(32, MO_UL) #undef DO_GEN_LD #undef DO_GEN_ST =20 +#if defined(CONFIG_USER_ONLY) +#define IS_USER(s) 1 +#else +#define IS_USER(s) (s->user) +#endif + +/* Set NZCV flags from the high 4 bits of var. */ +#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index c8b9cedfcfd..c83f2205b67 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -52,12 +52,6 @@ #include "translate.h" #include "translate-a32.h" =20 -#if defined(CONFIG_USER_ONLY) -#define IS_USER(s) 1 -#else -#define IS_USER(s) (s->user) -#endif - /* These are TCG temporaries used only by the legacy iwMMXt decoder */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ @@ -209,7 +203,7 @@ void load_reg_var(DisasContext *s, TCGv_i32 var, int re= g) * This is used for load/store for which use of PC implies (literal), * or ADD that implies ADR. */ -static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) { TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 @@ -223,7 +217,7 @@ static TCGv_i32 add_reg_for_lit(DisasContext *s, int re= g, int ofs) =20 /* Set a CPU register. The source must be a temporary and will be marked as dead. */ -static void store_reg(DisasContext *s, int reg, TCGv_i32 var) +void store_reg(DisasContext *s, int reg, TCGv_i32 var) { if (reg =3D=3D 15) { /* In Thumb mode, we must ignore bit 0. @@ -264,15 +258,12 @@ static void store_sp_checked(DisasContext *s, TCGv_i3= 2 var) #define gen_sxtb16(var) gen_helper_sxtb16(var, var) #define gen_uxtb16(var) gen_helper_uxtb16(var, var) =20 - -static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask) +void gen_set_cpsr(TCGv_i32 var, uint32_t mask) { TCGv_i32 tmp_mask =3D tcg_const_i32(mask); gen_helper_cpsr_write(cpu_env, var, tmp_mask); tcg_temp_free_i32(tmp_mask); } -/* Set NZCV flags from the high 4 bits of var. */ -#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) =20 static void gen_exception_internal(int excp) { @@ -697,7 +688,7 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } =20 -static inline void gen_set_condexec(DisasContext *s) +void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { uint32_t val =3D (s->condexec_cond << 4) | (s->condexec_mask >> 1); @@ -707,7 +698,7 @@ static inline void gen_set_condexec(DisasContext *s) } } =20 -static inline void gen_set_pc_im(DisasContext *s, target_ulong val) +void gen_set_pc_im(DisasContext *s, target_ulong val) { tcg_gen_movi_i32(cpu_R[15], val); } @@ -1074,7 +1065,7 @@ static void gen_exception_el(DisasContext *s, int exc= p, uint32_t syn, } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ -static inline void gen_lookup_tb(DisasContext *s) +void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); s->base.is_jmp =3D DISAS_EXIT; @@ -1109,7 +1100,7 @@ static inline void gen_hlt(DisasContext *s, int imm) /* * Return the offset of a "full" NEON Dreg. */ -static long neon_full_reg_offset(unsigned reg) +long neon_full_reg_offset(unsigned reg) { return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); } @@ -1135,7 +1126,7 @@ static long neon_element_offset(int reg, int element,= MemOp memop) } =20 /* Return the offset of a VFP Dreg (dp =3D true) or VFP Sreg (dp =3D false= ). */ -static long vfp_reg_offset(bool dp, unsigned reg) +long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { return neon_element_offset(reg, 0, MO_64); --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619792781; cv=none; d=zohomail.com; s=zohoarc; b=kqvNjYx+LHTLCxVrsD53ReUr8SG1FQEQL1+bq6h+btsE3YQ7zXdL78rafSmSkwZ1Oe2W2B8t0yfufaiV27wbObeLMyQ184IcDQyE9ZpPrUf5QMIuunn4XthgLeqpgGopjt+JmxO2QtV1SvrCjVnNd3ywY2t5SfNa87JwATToWp8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619792781; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F5srNWLoR+tJvJGu3iqRKMB8Wtmf8qQwcyjFl8XuJIQ=; b=K526ZTk6gD3QYEC0LVYubX4bBYi9AvqB34kg9R6JpjYrA4biJzFFDxCx6M19WYZeWYEn28OfifYv1pjvcUIm4OaKdQTNWBMNDHggADvTC4bpv+utDqMAVoLNesgSeQJi7tV5RoXrcJgxImnq99N3DHtU+a8cdwMeDl/1bPnyKY8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619792781051861.4274836603711; Fri, 30 Apr 2021 07:26:21 -0700 (PDT) Received: from localhost ([::1]:34506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcU5z-0006Ju-Ie for importer@patchew.org; Fri, 30 Apr 2021 10:26:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40458) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBe-000618-BE for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:06 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:46626) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBP-0003vT-6O for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:06 -0400 Received: by mail-wm1-x32a.google.com with SMTP id k4-20020a7bc4040000b02901331d89fb83so1681065wmi.5 for ; Fri, 30 Apr 2021 06:27:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=F5srNWLoR+tJvJGu3iqRKMB8Wtmf8qQwcyjFl8XuJIQ=; b=LPOSVhE8fPkoBHNc97geEb8eAKe7nnwTEuTYNy5dTIicpVv+/H12+dsq/owd8HGKOp dR2SqayywT5wxneaov7ta1K22iLwfC70I7pdMthjabVUlJehVUYq5dT2Fy3nSYwM94yC DDKH/NQr2qWKqm3dYArilss7EBG8HerD8VAUEG1+3YU9ZUcTKtvfleMAPRrF+ZWhc8Iy CQoDnywBnOkHP4lymw2twsblbfm3HFrgg/4elyP03uLQn7cNOqHL1BXCie7mA8lR7MZx F5plBe6xl1QmELukNQpnAnJDchLEp8kHKHKxe2KgefKEhiWLS1eBWKrmUuDCqdhEeNDN jOAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F5srNWLoR+tJvJGu3iqRKMB8Wtmf8qQwcyjFl8XuJIQ=; b=bj1uq5XXBg8DiEuLPvjIwtNfsBfl756AaX9Tjf+JvjUG5UgSg3Xg+HOQW+jrfK75yo zu7XT8pKlq8aQQaH/2kpyURRyE9gJs6TXTdz7ka/NuFEqM70zMWMF5goURb7olFv32fy oW1fBrY+G9WF6MHip704ITWyh02ZzLkBv7ZUoogCtCtKJMitpqqNSojWXP2y2bC/BJ18 kre4mycgceRv9OC5wqoAHiOZh9t9KrAY5sV1p++bxCBnVwdDH5uM7TdTUjVFZ8NHjONR 2RkzO8mwXnQ8s192See3yhmVoKH8Aha5PRQyf/k68AdgQSkDQ4mnFoTumSix1X9f+9wK 3Dcw== X-Gm-Message-State: AOAM5304wZ+jQ0iz0F0H7wnSNI1UgG00SlHMUvpIJzTyeSVYg7cqen9j 2zDx35ZHpRXTDpg8lhHHoB1WuATNKv92oOYT X-Google-Smtp-Source: ABdhPJyV0W2wCRggpWdXdc2/vXG5NFWuhjfg9pTbCECgt8iDeSEThUNXvKPB7Y/phLwFvSDbIh2RDw== X-Received: by 2002:a1c:60c2:: with SMTP id u185mr6098606wmb.157.1619789269467; Fri, 30 Apr 2021 06:27:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit Date: Fri, 30 Apr 2021 14:27:35 +0100 Message-Id: <20210430132740.10391-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Switch translate-vfp.c.inc from being #included into translate.c to being its own compilation unit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 2 ++ target/arm/{translate-vfp.c.inc =3D> translate-vfp.c} | 12 +++++++----- target/arm/translate.c | 3 +-- target/arm/meson.build | 5 +++-- 4 files changed, 13 insertions(+), 9 deletions(-) rename target/arm/{translate-vfp.c.inc =3D> translate-vfp.c} (99%) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 326cbafe996..e767366f694 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -22,6 +22,8 @@ =20 /* Prototypes for autogenerated disassembler functions */ bool disas_m_nocp(DisasContext *dc, uint32_t insn); +bool disas_vfp(DisasContext *s, uint32_t insn); +bool disas_vfp_uncond(DisasContext *s, uint32_t insn); =20 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); void arm_gen_condlabel(DisasContext *s); diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c similarity index 99% rename from target/arm/translate-vfp.c.inc rename to target/arm/translate-vfp.c index 1004d1fd095..3da84f30a01 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c @@ -20,11 +20,13 @@ * License along with this library; if not, see . */ =20 -/* - * This file is intended to be included from translate.c; it uses - * some macros and definitions provided by that file. - * It might be possible to convert it to a standalone .c file eventually. - */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "translate.h" +#include "translate-a32.h" =20 /* Include the generated VFP decoder */ #include "decode-vfp.c.inc" diff --git a/target/arm/translate.c b/target/arm/translate.c index c83f2205b67..6aec494e81d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1224,8 +1224,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) =20 #define ARM_CP_RW_BIT (1 << 20) =20 -/* Include the VFP and Neon decoders */ -#include "translate-vfp.c.inc" +/* Include the Neon decoder */ #include "translate-neon.c.inc" =20 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) diff --git a/target/arm/meson.build b/target/arm/meson.build index bbee1325bc4..f6360f33f11 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -3,8 +3,8 @@ gen =3D [ decodetree.process('neon-shared.decode', extra_args: '--static-decode=3D= disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--static-decode=3Ddisa= s_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--static-decode=3Ddisa= s_neon_ls'), - decodetree.process('vfp.decode', extra_args: '--static-decode=3Ddisas_vf= p'), - decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=3Dd= isas_vfp_uncond'), + decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), + decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), @@ -27,6 +27,7 @@ arm_ss.add(files( 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', + 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IDION3oXJpT5OR6Bra+r6895wXbZrL9XVbTtZK09BTQ=; b=w95xCK3BWx+Ez9ZZdIk7ggs0RxVMS/d4WRLv7DiDwBNdwMCitMVUYvDfYop4jadI1o KmaJWtsCtHZhM4QrwYrTtBbR1k42Rmq0wKbGMPCqsByPViE7VnYIIRpSYyUTIKyBoYxd MBTjl7s0TEJF8f8nTyhHBfPg7WQMB1Tx35rhPT6N+rXTJ6MILea4EhVD62DdxfGJ5M1d ybmNgpUS73acsWsbQGFXrgUCptrGY+HmL6OqPs/Av9Mb3FbSSWS8czIcijxEnglhEdk0 Y8PAXC5VO6fik7FvKvUD4UsxayXI9P/8PXl+D6SvGDTyToyxAOaZqkqCrrwaFyhzNP+e IgiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IDION3oXJpT5OR6Bra+r6895wXbZrL9XVbTtZK09BTQ=; b=XdkOL3CI935SviexlpfhgrpTX3pfJhcUc/8VAF4IdsRjxCxbnhXqSDv7LFtuhDnea3 hGmx95mUtaLqyxxtiucU+jsiMNhQdEB8VK5xNOHotmkOoKVseFb+lPAiteNAp6/c0YmZ ENaMkucDHvclv5G90CnbhvSswFIpgBGynlHxfePWI8YU8EO+0H7oYE0nJfJwHsLTxu61 Jfe0b2gyVFse1k314BSZkEssvNd2WZ9S7lRp3AIS7gvZBc2U+auNnLkppbLMjaquWnrv ZNAG4J/tSDurcAgcvv0oERFn0LQvqAPSr7rh7YFQsu4dJ52z68kOWutQ6F4IoPWlJgaY jRaA== X-Gm-Message-State: AOAM533dN9RK9AOMoXAr9LvO9TiMgeaBWKxCZ05+bFrOl3d+aPybmlH5 aSNubXLnQEAkx6xFdgfx6kJOVKWGp9C8Mfyf X-Google-Smtp-Source: ABdhPJzvwLM9v45nsBlehabYjrKPA2zv4JCxMhuRDnl6xb+FkXMDO9ZOYowXPKlf9sRapMinFtUnmQ== X-Received: by 2002:adf:fc46:: with SMTP id e6mr6855949wrs.169.1619789270059; Fri, 30 Apr 2021 06:27:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc Date: Fri, 30 Apr 2021 14:27:36 +0100 Message-Id: <20210430132740.10391-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The function vfp_reg_ptr() is used only in translate-neon.c.inc; move it there. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate.c | 7 ------- target/arm/translate-neon.c.inc | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6aec494e81d..095b5c509e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1215,13 +1215,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int= ele, MemOp memop) } } =20 -static TCGv_ptr vfp_reg_ptr(bool dp, int reg) -{ - TCGv_ptr ret =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); - return ret; -} - #define ARM_CP_RW_BIT (1 << 20) =20 /* Include the Neon decoder */ diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index a02b8369a1d..73bf376ed32 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -60,6 +60,13 @@ static inline int neon_3same_fp_size(DisasContext *s, in= t x) #include "decode-neon-ls.c.inc" #include "decode-neon-shared.c.inc" =20 +static TCGv_ptr vfp_reg_ptr(bool dp, int reg) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); + return ret; +} + static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) { long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619792650; cv=none; d=zohomail.com; s=zohoarc; b=fOrLDeeulHqs1O8j1JrwtA0SGkSV0QkTATjudi9thyb5LPR9zfo53qJI640PF57whsTZdCNYSW/3XijoDzyIwY8r7M4EMjQrHc/dqjqHt57Fhaw+42z+IvYwBTm6tiAjuzUqPQxj+Xo/bzOLMc41efEAt5u7y0i4bD/qDdS26EA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619792650; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QuUuJ1pUTeudtTr2wsE0zE4ui6UzEIP2HwIFDweRVHQ=; b=BomFtm3eFCPo9Y67ZrDaFRx08AEN+99kbMplw2CTSI9qKyQP4E+k3z69ujmATfuMeHpU7yzFXqLWSrSNOcK6jjUbqoPO+MR9K0HJn+poMpJGx/nojnQ6WpI+altjnK/EKCaiOa9JL2YExRiLGGEnjrfGOLOl+6CobRHSWd5cqLg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619792650832232.03068617545364; Fri, 30 Apr 2021 07:24:10 -0700 (PDT) Received: from localhost ([::1]:57626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcU3t-00045z-NV for importer@patchew.org; Fri, 30 Apr 2021 10:24:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBd-0005yL-Ad for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:05 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:37650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBR-0003wn-Ca for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:05 -0400 Received: by mail-wr1-x435.google.com with SMTP id z6so9304473wrm.4 for ; Fri, 30 Apr 2021 06:27:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QuUuJ1pUTeudtTr2wsE0zE4ui6UzEIP2HwIFDweRVHQ=; b=BFme2z9X8P+InzQHejIy2HXd8gfniw6HcqUL2QrYnM9gSI1J0wu7i4IEfWqemvIsKN C9UnzeFH8ub0zaQ4EM09dcdrpIFE9euoJLC9HzExRlT8idi/zNU53vsgly/FGe9bK105 XVW5E0crB4h4LIfIC6I+egXw+Hs9EJDuy8YpkjDXm4NWgVxAtX6vWhMRJTus0VjzwDRO ynkUv8zo0Fzyio8pjYQTh0kyD9oZm9y7kI+WivUqVN1biOmoPdVl5rEXz19N9QOCSUeq rnsUT6N+dhUNyWXx6EMobxTnMMQkwpyxgwQlD65+8qFd4y1bht763Ea8XghiQZAxQe2Y twKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QuUuJ1pUTeudtTr2wsE0zE4ui6UzEIP2HwIFDweRVHQ=; b=JtCkQWU71FRgoxt5iraNt0fqcG+QE9AJNdqx4nT8pdGjiss2Ql5L82q9x01GSNYvE9 Xb5NIGjUBnxqLPHEkbqVgwbbnpSPj7NtPlBTJnAYH3fKDfxzT+f4IFeCs5Mqfeq5ifa/ x4QNaPEuR48jBjOrYKznm68eGqosPjoOotyzVJpekVgB3SflU0bMXoNJtCB8cMkeeDiI UK+nH7AYxrssX9gc2lHPC4wNLscEWtPzx/QHVXoahzvPJv1IEHiur+vQj0pkSWhAhzix HGm7qyPZf0ILADKivD4JFmAjUf89PApB7+267IabOnXQBs1L6BxgVNqYwy9RqyoJgzKF D9Cw== X-Gm-Message-State: AOAM5319Z0yP9qwNgTb11ZSFmkzQQCYqx/QqzX2Cq1UJn2cwBeYZKbAQ jTdxI75OmeySU4A+KyAPH7EPPtu0JmhCMjqf X-Google-Smtp-Source: ABdhPJwuSi5hpHOcPyjvEEq6MJWd/OLa0sK8tgIy9vcPAKm+dq24xlAbJTF25KYvTZYt83ZOUoNnFg== X-Received: by 2002:adf:f74a:: with SMTP id z10mr7059959wrp.406.1619789270766; Fri, 30 Apr 2021 06:27:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 10/13] target/arm: Delete unused typedef Date: Fri, 30 Apr 2021 14:27:37 +0100 Message-Id: <20210430132740.10391-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The VFPGenFixPointFn typedef is unused; delete it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 095b5c509e1..58cb3e8aafe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -69,8 +69,6 @@ static const char * const regnames[] =3D /* Function prototypes for gen_ functions calling Neon helpers. */ typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32, TCGv_i32); -/* Function prototypes for gen_ functions for fix point conversions */ -typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); =20 /* initialize TCG globals. */ void arm_translate_init(void) --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619790765; cv=none; d=zohomail.com; s=zohoarc; b=But86TwXvoDEuvX+uBl0H54NDHXfgzYYSD/jh/hy5ea1ACAjx1SCq3fJLane5jMhM90XL+vrSj191Ic+EiWHLAjDFWThnPQNNIs9+O50D6oT5pVX4+Z165iUhxTQko5F1qQLi0P8s2NaKcRs0U/Ch2+FNnDNB/yuZWmU7vCUN/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619790765; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WsY/6TlhQWmplPggiqYU8UZ1d8KHNZozZRTEu9NaL7o=; b=FSlXTlU0samukZwJ6tHMTST5bT/ijEnlR1TsSPW6plAXleymHobJAMUvRrHpk4yl5l458zGoWuuG7SE9gb2iVr37jKwA0GKS49/7Qr1MnCZPwSh+2TkCrQ4Z4krBTavrjsT2okZVAdLVjKxNiDraMvFGtHe5iziTfNEYPD6bVjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619790765526869.6398280763563; Fri, 30 Apr 2021 06:52:45 -0700 (PDT) Received: from localhost ([::1]:45118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcTZU-0000Y7-5q for importer@patchew.org; Fri, 30 Apr 2021 09:52:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBe-000620-Me for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:06 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:33392) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBT-0003wx-55 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:06 -0400 Received: by mail-wr1-x42e.google.com with SMTP id n2so17424077wrm.0 for ; Fri, 30 Apr 2021 06:27:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WsY/6TlhQWmplPggiqYU8UZ1d8KHNZozZRTEu9NaL7o=; b=Wx4Hwyt5xn60isixYQbAw2hFeN7zOLx26Pv6gvkr+nK5770QPlTGW7gohbEqh05/uq yKYO0ehF5A+qwq6PPupxbKLG8iFz/11AOrH2Iy4C9Gjf/TTmid1sPk1yJmoyy5Mb6gTm oymcs66+XGQgxFEor756lIukrYnAJSyR1ET/n+s3xarq5oMrK5gZwNuBhdYxwq1KwOs4 gbaPa/9A4E/1y/cVAN2dr6ae7MnYwv/1RVUFouyL3vAmKIPyRSc4oeKphCE2H0C/cAlD cLrMnKFGQbymYaH//SrtQBCakFEoKpRQa82c2VF5q1H87/Jx2NcyU0rlBd5ABZ5+j7BU tSTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WsY/6TlhQWmplPggiqYU8UZ1d8KHNZozZRTEu9NaL7o=; b=fmYEy1UvjaBj5bDPOc8X2Xm6erg7QePzCeRKLb9dhB9LymH1onxb5Vis0MSifPz92m FNTTgErvicb9gz2hOMS2qCTgywWKLArFMW7zy5uAhXKgE7XjKA2kL14UghHIrmoVnL/L X0I1CN4Qg/9rvY6FixVdPff7IzwG+EdVQAFx/QBj+E/edGf4IftbA9rXnusTtGuwSuXK KnpUnIsWd5s5lchYk5xMZvAAl0xM7oQse8E5yNMZZzVZ3mniG1OUODRpIa/DR/dhxyXA vRjvV1nhL2LFjXCF+XGL1/yOP03hyWlXMjPYodtwBoh47O3MRxOW1lSM5cY5sHTHnS/x JizQ== X-Gm-Message-State: AOAM531aOi4y+Olu5WGq+QYRyHRHKldPyBmuFiYGN7BEj5q891gqB0KP DuUqcXwXSoJH7lNIP8uhPCn6/3pktgfxLDy0 X-Google-Smtp-Source: ABdhPJwpw/JC49hDABjlwZ8A4tW8MJaWYTX5YSKb9RHVYo0SxA0r0WDWYwY9JA7KVBiOgKSgLRNRpQ== X-Received: by 2002:adf:9b96:: with SMTP id d22mr6933345wrc.225.1619789271396; Fri, 30 Apr 2021 06:27:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 11/13] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h Date: Fri, 30 Apr 2021 14:27:38 +0100 Message-Id: <20210430132740.10391-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the NeonGenThreeOpEnvFn typedef to translate.h together with the other similar typedefs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 2 ++ target/arm/translate.c | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 8130a3be29d..12c28b0d32c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -409,6 +409,8 @@ typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, + TCGv_i32, TCGv_i32); typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); diff --git a/target/arm/translate.c b/target/arm/translate.c index 58cb3e8aafe..7ff0425c752 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -66,9 +66,6 @@ static const char * const regnames[] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; =20 -/* Function prototypes for gen_ functions calling Neon helpers. */ -typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, - TCGv_i32, TCGv_i32); =20 /* initialize TCG globals. */ void arm_translate_init(void) --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619789948; cv=none; d=zohomail.com; s=zohoarc; b=bHuSLmyOiwE6Ry9SDTk6rSczS3iru9BmSjhxs/rhsgTam8eiU/wy359rucRaAXs8k5TCakuPGs5MjnVi9pUaEZSZ2cPhZvNxzDOaoJ2MayvZn3D7Iqhzh7KzJA43yHdg70aFDW9Hcp8gwk2srVO5ERLk+NmjjAhFGx8+tz2k3as= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619789948; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ILpSmeJTPLM2v5QVwpSeaY3R9jeZZgf64RSp8bd/BBg=; b=QvkaM9HOlD6G5VwOQIARjFy1EnHrM9UNVhJXrkxiQBLcTpUxHPz7PvIQrYCqMXC/nFUusnJa0KeqK9D3uUk1Y+JxFpLTEWK36aCMFj72QCQ4utdG4c3TcqLB5mheq1NsI7A7yuW1Fwo/8hLSnIpHvVI2G5miBfTpLUamFSPkkAk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619789948616868.1473577306961; Fri, 30 Apr 2021 06:39:08 -0700 (PDT) Received: from localhost ([::1]:34828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcTMJ-0000Ro-A8 for importer@patchew.org; Fri, 30 Apr 2021 09:39:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBd-0005zd-Uf for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:05 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:41955) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBT-0003xf-5S for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:05 -0400 Received: by mail-wm1-x32c.google.com with SMTP id t11-20020a05600c198bb02901476e13296aso1111125wmq.0 for ; Fri, 30 Apr 2021 06:27:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ILpSmeJTPLM2v5QVwpSeaY3R9jeZZgf64RSp8bd/BBg=; b=UV+aoBGHaJMlDwUrQ92RTWbf0lUYSP0NInqVOr6XqhwOUCwbPxFA+lKtS5KLvT+M0E vmdy86gxPU/gXr4T2CwnAVDZVFkoQRSQPQDztSB7rdfThi2CVTNhWoiw8BazObTPBrg+ SoWO4nA+Sxu4mJfl5Dya8IzDKLgX6/UrcLjhA/dN1rL56FBULNRZ1etD+OffCCP9Zs1j CgvZHQcFyTDmI+ewJoW8/o8mLHVCFtxtJ89qUQyb2pttYPkipAgrGL4xYMIUgWlIfAt/ X/pgPozxER8ogm70zb+hTtumHINlz3dD3bOAf5etiSL40grBmRlV+3Nkf9CzaAg7NMJ5 wXAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ILpSmeJTPLM2v5QVwpSeaY3R9jeZZgf64RSp8bd/BBg=; b=P5cZc/u43aU0vI5SF6S2dbLJxKqINXGXQj7o09VOT9sfAMi1yji3wPMZElSRSBirlU 471RV1XUUOnGkNhn1NOZnjOk90mkW0U+b7SuG8h7iEZDCeV0AqYDiefcFnMknNCGSCDI 2S+CGh+9wHyNsCji56HMNigCDWAmnbPrYPVeLXXvNT1zO+L4g/DcDxH4YFjY8gF5o9Di qHhEAN117OYtLD1YY2Hsws1t78DXjL6jow9fLy/tqMcGDxMBW5SF/bz0xZMH8LrXGlR9 orbLv72MGjA99BEHZNchJNZ8pTqGWa2H+hKievgb/kUGlE043Zo4+wZVd4iGicLFgSIp +Bzw== X-Gm-Message-State: AOAM533scV4iB+rjClgE27sHRbkWADF6crYDRxPlruRkDX40CNWvLlW9 vgJi3O3a9IR0RitR6/F6IiG564IKaEjeo94Z X-Google-Smtp-Source: ABdhPJy04nlEpzQEtQf9Smwg40e5RwBDkEKLONVPWC12Kec1AQzpXGcRaFnhKIMw7CsWwRzE9HZ3BQ== X-Received: by 2002:a1c:7c1a:: with SMTP id x26mr12725948wmc.22.1619789272096; Fri, 30 Apr 2021 06:27:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 12/13] target/arm: Make functions used by translate-neon global Date: Fri, 30 Apr 2021 14:27:39 +0100 Message-Id: <20210430132740.10391-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Make the remaining functions needed by the translate-neon code global. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 8 ++++++++ target/arm/translate.c | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index e767366f694..3ddb76b76b5 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -39,6 +39,8 @@ void gen_set_pc_im(DisasContext *s, target_ulong val); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); +long neon_element_offset(int reg, int element, MemOp memop); +void gen_rev16(TCGv_i32 dest, TCGv_i32 var); =20 static inline TCGv_i32 load_cpu_offset(int offset) { @@ -130,4 +132,10 @@ DO_GEN_ST(32, MO_UL) /* Set NZCV flags from the high 4 bits of var. */ #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) =20 +/* Swap low and high halfwords. */ +static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) +{ + tcg_gen_rotri_i32(dest, var, 16); +} + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 7ff0425c752..18de16ebd0a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -325,7 +325,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } =20 /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) +void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp =3D tcg_temp_new_i32(); TCGv_i32 mask =3D tcg_const_i32(0x00ff00ff); @@ -346,12 +346,6 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) tcg_gen_ext16s_i32(dest, var); } =20 -/* Swap low and high halfwords. */ -static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) -{ - tcg_gen_rotri_i32(dest, var, 16); -} - /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. tmp =3D (t0 ^ t1) & 0x8000; t0 &=3D ~0x8000; @@ -1104,7 +1098,7 @@ long neon_full_reg_offset(unsigned reg) * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, * where 0 is the least significant end of the register. */ -static long neon_element_offset(int reg, int element, MemOp memop) +long neon_element_offset(int reg, int element, MemOp memop) { int element_size =3D 1 << (memop & MO_SIZE); int ofs =3D element * element_size; --=20 2.20.1 From nobody Sat May 18 05:53:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619792881; cv=none; d=zohomail.com; s=zohoarc; b=Pjo7o0qIIz0aeJ2DPJ7B6Eio1jAu+W8oOxQJO+wuw7r90gczRaC3iYTPM+WaWmCPVi+Qv6BDACoiAUl9qYrfxw1+IBGdRsZURMj7Ic8cu0pp6xv11R9x/1Va1oG/GmNsD2UJAG/8pT2jZE4xjvl36MtPgt67Yfy0/VWtnSAaQBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619792881; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ziv4ut6jaiRoePWGy7KWl5QjX47CoE0VaiX3H3AeiJc=; b=C1uj8FwHDabm9wWZKS+JKdzT6izH8II/gMtSXQFir7D1sojV02FoCA/0JIjAozZDkXqjxFHOB8xd9iT2/muKGFZnoArFsmh9nVMYZZ0f06qmsEuogbWAOQn4DD1F4By6X47oLqWuID403SuNTm96nx0fDH2Ac+c44bEO3iLO33U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619792881330878.681853480641; Fri, 30 Apr 2021 07:28:01 -0700 (PDT) Received: from localhost ([::1]:36738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcU7c-0007Ft-4j for importer@patchew.org; Fri, 30 Apr 2021 10:28:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcTBf-00063N-6K for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:07 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:34751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcTBT-0003xl-7b for qemu-devel@nongnu.org; Fri, 30 Apr 2021 09:28:06 -0400 Received: by mail-wm1-x332.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso396005wmc.1 for ; Fri, 30 Apr 2021 06:27:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm2420349wrx.15.2021.04.30.06.27.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 06:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ziv4ut6jaiRoePWGy7KWl5QjX47CoE0VaiX3H3AeiJc=; b=QhqfpNTluwMU7ljz3DFUgbuaVZsdtQeRNhccGkBFnzWgCHg79LqCn95kosUfr51jWb ndVV1aivoEDWa2BsuLgPu1NSOQLCxL5HEmjDTITp02vSCoe1FStbM7+Ylhn/QxklTdAp rJ40NzVnTaqku7YJah0IvqQaL3YCLLnzyU658q0Vy1HZ4PeADgycTrMNKx/ELI7mAyS0 Qfh2oH77lZUqEnQ3Rcs5NUAtpGb45tswQjAC77HPhJTcEi7SAOSTT5/Ic5sF6ZpxpgwW zFoAmkprT/iTyqqw2KYRCoJjo/vBsJOfXCSlyMZMU484YwSi0CmTj2EClFn44nCD3Zjo egkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ziv4ut6jaiRoePWGy7KWl5QjX47CoE0VaiX3H3AeiJc=; b=oCG8QELS22GupJt8/ZMluanTrmEeHGhxlEF/2ann3YqFNK6juSM4UcHspK1N/ThW5z Lodfi5naAKEacbs8rVOR5Z8EdfktPdE9gKscrD2YyMuyG/Ylclnb1xDyg4RQBlzdBsqI PASLwfuU+u0Vvj8xgWwRt+tSISX8vkdYUGw1ZesssF9sQyu9rzuIHcAuHZmbCfEp5zyp WIfg6TYysOeomEPWHELA5+rHbpI2B+sJ0tU7cAS4c5CfV9xSbdc7E59cQs1kIcF+C9n6 7MOa2CHSEhTs2rorDJjguOqyv9LHq8vHgiB34X9iZ2VAgHrVfYmKndz1Fr1sX/yjT4U5 Uurw== X-Gm-Message-State: AOAM530MciouQM89RnvKasrny8Un7+l56TMrMlGKcI/SISWtRa5o36CO /g5vwUWt27FedlthNM4ls7q5hqHkukdO69ig X-Google-Smtp-Source: ABdhPJzNcvjlIAatsryKQHqvI22PE7ZJXVAQacbdy3DAdml5PxHpZnMNxBaaghxPv8lcTE/Gsidsyg== X-Received: by 2002:a7b:c312:: with SMTP id k18mr6239147wmj.89.1619789272925; Fri, 30 Apr 2021 06:27:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v2 13/13] target/arm: Make translate-neon.c.inc its own compilation unit Date: Fri, 30 Apr 2021 14:27:40 +0100 Message-Id: <20210430132740.10391-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430132740.10391-1-peter.maydell@linaro.org> References: <20210430132740.10391-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Switch translate-neon.c.inc from being #included into translate.c to being its own compilation unit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 3 +++ .../arm/{translate-neon.c.inc =3D> translate-neon.c} | 12 +++++++----- target/arm/translate.c | 3 --- target/arm/meson.build | 7 ++++--- 4 files changed, 14 insertions(+), 11 deletions(-) rename target/arm/{translate-neon.c.inc =3D> translate-neon.c} (99%) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 3ddb76b76b5..c997f4e3216 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -24,6 +24,9 @@ bool disas_m_nocp(DisasContext *dc, uint32_t insn); bool disas_vfp(DisasContext *s, uint32_t insn); bool disas_vfp_uncond(DisasContext *s, uint32_t insn); +bool disas_neon_dp(DisasContext *s, uint32_t insn); +bool disas_neon_ls(DisasContext *s, uint32_t insn); +bool disas_neon_shared(DisasContext *s, uint32_t insn); =20 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); void arm_gen_condlabel(DisasContext *s); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c similarity index 99% rename from target/arm/translate-neon.c.inc rename to target/arm/translate-neon.c index 73bf376ed32..658bd275dac 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c @@ -20,11 +20,13 @@ * License along with this library; if not, see . */ =20 -/* - * This file is intended to be included from translate.c; it uses - * some macros and definitions provided by that file. - * It might be possible to convert it to a standalone .c file eventually. - */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "translate.h" +#include "translate-a32.h" =20 static inline int plus1(DisasContext *s, int x) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 18de16ebd0a..455352bcf60 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1206,9 +1206,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int = ele, MemOp memop) =20 #define ARM_CP_RW_BIT (1 << 20) =20 -/* Include the Neon decoder */ -#include "translate-neon.c.inc" - static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) { tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); diff --git a/target/arm/meson.build b/target/arm/meson.build index f6360f33f11..5bfaf43b500 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,8 +1,8 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), - decodetree.process('neon-shared.decode', extra_args: '--static-decode=3D= disas_neon_shared'), - decodetree.process('neon-dp.decode', extra_args: '--static-decode=3Ddisa= s_neon_dp'), - decodetree.process('neon-ls.decode', extra_args: '--static-decode=3Ddisa= s_neon_ls'), + decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), + decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), + decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), @@ -27,6 +27,7 @@ arm_ss.add(files( 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', + 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', --=20 2.20.1