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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Bf/imavd9eUjfb3z2UO3I9eaVsDiw1wTDTip+/KNxIU=; b=kxh93zaf1/HE4dz6jqzugx5pyIh/0YhZ/tCcoAoKnjamyAA3KJO3PBB2s8CCJIV0dF ffjFRw35lBWZ7ETGsN9MKsBhzYILRkiOWX+7IPIPtHh9eEAhkldWAZpoTkVVMfH5skKt d7NNA9p6gNnvEtQ6u15Vx7I59l49I3A5iS5dnYQ+11eE1yfXSCyL74BBSkXlDrfeKtq9 nEsS5Ow6fJSbL0jiQI3k5tYU8KXtoeQea71IpUoYN0Bn2mVK8Vf6Tog+Bp1fpQEjfLvI t+F4phavklpWG7rMQblYWhipCWVc0euoZAyobOLRzwPDkFFsoAiPIOj1sdAm1XkIFfT1 ynBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bf/imavd9eUjfb3z2UO3I9eaVsDiw1wTDTip+/KNxIU=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b90d6880e78..ac60dcf7602 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2699,7 +2699,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, size); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2716,8 +2717,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) } clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, t= rue, + rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; =20 @@ -3505,15 +3507,18 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; bool is_store =3D false; - bool is_signed =3D false; bool extend =3D false; bool iss_sf; + MemOp mop; =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { unallocated_encoding(s); return; } =20 + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + mop =3D size | MO_ALIGN; + switch (opc) { case 0: /* STLURB */ is_store =3D true; @@ -3525,21 +3530,21 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) unallocated_encoding(s); return; } - is_signed =3D true; + mop |=3D MO_SIGN; break; case 3: /* LDAPURS* 32-bit variant */ if (size > 1) { unallocated_encoding(s); return; } - is_signed =3D true; + mop |=3D MO_SIGN; extend =3D true; /* zero-extend 32->64 after signed load */ break; default: g_assert_not_reached(); } =20 - iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + iss_sf =3D disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) !=3D 0, opc= ); =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); @@ -3552,13 +3557,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) if (is_store) { /* Store-Release semantics */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, t= rue); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, tr= ue); } else { /* * Load-AcquirePC semantics; we implement as the slightly more * restrictive Load-Acquire. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIG= N, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, extend, true, rt, iss_sf, true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } --=20 2.20.1