From nobody Sun Feb 8 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780009; cv=none; d=zohomail.com; s=zohoarc; b=QFY594reTuhek+TwR2kOzKPwZEv0ZffPho7IQvfOXVBCb7HBm85OXkc7S/4In+sjUj8uAQwuwANGfCVoxR5gIfB5LzKWwU1rf3gfFdiaUu/1FzNXwvAVEmwE1wVBJattiyGsGOyO1vFsZVfltbzFJP0Har8yPAzMomhwGcvxTNo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619780009; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Pr3emJngQ8q9YaGb+93M0B7Old0uTo2ChY3L4kgMIaA=; b=HpqxkF72eBkUEnqLyoBki5IOuoxuDg+nWNMrPhTFOPKG9v98TSt4yrm+WZLr72/8bY9cwsW3IFSxzFeOe0jrmVRfSpP2yPND3jRL7vwXv7Gal1nY/dbqSCaxdhcz2z4jzcUWT8r5HVO1CipIixWBUkh+JBzDsYSgUewO4IhmBXY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619780009854548.005378277501; Fri, 30 Apr 2021 03:53:29 -0700 (PDT) Received: from localhost ([::1]:49326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQm0-0004Nu-3J for importer@patchew.org; Fri, 30 Apr 2021 06:53:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU7-0007iq-Uu for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:59 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:43887) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU5-0001KG-0z for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:59 -0400 Received: by mail-wr1-x42b.google.com with SMTP id x7so69946277wrw.10 for ; Fri, 30 Apr 2021 03:34:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Pr3emJngQ8q9YaGb+93M0B7Old0uTo2ChY3L4kgMIaA=; b=hs0d8g5nFGgnVzpUuTJf69Dnr7R+zGX+r4BkVAclW5hs2KqRpmDPpSQ5Ck6aXIvDOv vFmtuz5LomI5vSybd9rUJLJhcUeVqcvJWCBw5IfywI7sJyo0vIZ9lTh3Vpik/YgcEIn/ 1FRZY5zzS3Qbej+A/bSPpSTkcCRz0hCnGkmYfDKcte3/Pcr2hL5POFYrIBMamI+ef54h xTZdMcft4hqk6EvtQs7fsHNtrXHySW1fF468k8SDkhMiJhPj+qArsc7m0+qRyCMoQ9eX F7jQjLvjvUtjfPNyUrMbTLI0hyhpWvZpUU2Mp6v+HnL1V/r1mnE8NJ5TmW+nRzMujHvH JGSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Pr3emJngQ8q9YaGb+93M0B7Old0uTo2ChY3L4kgMIaA=; b=uWDXvGRr8QsfRc1DzgzfED3fLyc8ybPrmLv8VuYEk0jd1DQxq30O3ME6ZAUOw88UAd n9EoeaNfGBsBHkN7wV0HjTT9iAAq65WQQMjrugS9O239XcZdgndAimOZ1rO8RIa0hBxG 1SkjpmHobVCYC8SOB0Ty3kooeCkYpnTMODlssLlDIW6p3hy7zfTRNJ1F8CwNEO376+rg 4o15JcwT07BQ/vaXyrdoot1eeXCBti2dcmFYY8f35bjsd97KdLsQ5q5aX9F6ZLSumSGT hkKvLiIIKZCzaVUl7u+lQFSZjBuTEmMxemU/Z4Gy4sutbQT/S+dgyozUInAHfFbT9Pra CR6Q== X-Gm-Message-State: AOAM533ZTRsamLTqwjvurpZSYKBKL9zrtHzn8u8tuLp2Nq9KU+4F7cBB 3u9PHSv74NFE9+SDJ79e4hWdnqfwENDvGp/i X-Google-Smtp-Source: ABdhPJxK+7aVqjyZwjpFSKVUh0BIhj9zz+77lRA/9cKE+ZuG0NU19UVGRRxwtgdAAdJ4bN2pBTT4iQ== X-Received: by 2002:a05:6000:136b:: with SMTP id q11mr5873641wrz.350.1619778895611; Fri, 30 Apr 2021 03:34:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Date: Fri, 30 Apr 2021 11:34:15 +0100 Message-Id: <20210430103437.4140-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Create a finalize_memop function that computes alignment and endianness and returns the final MemOp for the operation. Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32 so that s->be_data is not added by the callers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.h | 24 ++++++++ target/arm/translate.c | 100 +++++++++++++++++--------------- target/arm/translate-neon.c.inc | 9 +-- 3 files changed, 79 insertions(+), 54 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index b185c14a035..0c60b83b3d4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -459,4 +459,28 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour= flavour) return statusptr; } =20 +/** + * finalize_memop: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Build the complete MemOp for a memory operation, including alignment + * and endianness. + * + * If (op & MO_AMASK) then the operation already contains the required + * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally + * unaligned operation, e.g. for AccType_NORMAL. + * + * In the latter case, there are configuration bits that require alignment, + * and this is applied here. Note that there is no way to indicate that + * no alignment should ever be enforced; this must be handled manually. + */ +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +{ + if (s->align_mem && !(opc & MO_AMASK)) { + opc |=3D MO_ALIGN; + } + return opc | s->be_data; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 970e537eae0..5bf68b782a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,7 +908,8 @@ static inline void store_reg_from_load(DisasContext *s,= int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif =20 -/* Abstractions of "generate code to do a guest load/store for +/* + * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero * extended if we're a 64 bit core) and data is also * 32 bits unless specifically doing a 64 bit access. @@ -916,7 +917,7 @@ static inline void store_reg_from_load(DisasContext *s,= int reg, TCGv_i32 var) * that the address argument is TCGv_i32 rather than TCGv. */ =20 -static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) +static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { TCGv addr =3D tcg_temp_new(); tcg_gen_extu_i32_tl(addr, a32); @@ -928,47 +929,51 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCG= v_i32 a32, MemOp op) return addr; } =20 +/* + * Internal routines are used for NEON cases where the endianness + * and/or alignment has already been taken into account and manipulated. + */ +static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr =3D gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_ld_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr =3D gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_st_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; - - if (s->align_mem) { - opc |=3D MO_ALIGN; - } - - addr =3D gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i32(val, addr, index, opc); - tcg_temp_free(addr); + gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; + gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); +} =20 - if (s->align_mem) { - opc |=3D MO_ALIGN; +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ } =20 - addr =3D gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_st_i32(val, addr, index, opc); - tcg_temp_free(addr); -} - -#define DO_GEN_LD(SUFF, OPC) \ -static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} - -#define DO_GEN_ST(SUFF, OPC) \ -static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } =20 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) { @@ -6456,7 +6461,7 @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *= a, addr =3D op_addr_rr_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); =20 /* @@ -6485,7 +6490,7 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr = *a, addr =3D op_addr_rr_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); =20 @@ -6508,13 +6513,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst= _rr *a) addr =3D op_addr_rr_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt + 1, tmp); =20 /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6537,13 +6542,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst= _rr *a) addr =3D op_addr_rr_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 op_addr_rr_post(s, a, addr, -4); @@ -6608,7 +6613,7 @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *= a, addr =3D op_addr_ri_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); =20 /* @@ -6637,7 +6642,7 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri = *a, addr =3D op_addr_ri_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); =20 @@ -6653,13 +6658,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) addr =3D op_addr_ri_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, rt2, tmp); =20 /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6692,13 +6697,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) addr =3D op_addr_ri_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 op_addr_ri_post(s, a, addr, -4); @@ -6924,7 +6929,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp= mop) addr =3D load_reg(s, a->rn); tmp =3D load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); =20 tcg_temp_free_i32(tmp); @@ -7080,7 +7085,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp= mop) =20 addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); =20 @@ -8264,8 +8269,7 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *= a, bool half) addr =3D load_reg(s, a->rn); tcg_gen_add_i32(addr, addr, tmp); =20 - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - half ? MO_UW | s->be_data : MO_UB); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); tcg_temp_free_i32(addr); =20 tcg_gen_add_i32(tmp, tmp, tmp); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 0e5828744bb..c82aa1412e2 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -559,8 +559,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VL= D_all_lanes *a) addr =3D tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg =3D 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); if ((vd & 1) && vec_size =3D=3D 16) { /* * We cannot write 16 bytes at once because the @@ -650,13 +649,11 @@ static bool trans_VLDST_single(DisasContext *s, arg_V= LDST_single *a) */ for (reg =3D 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); } vd +=3D a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); --=20 2.20.1