From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619778979; cv=none; d=zohomail.com; s=zohoarc; b=CAhD4j9yRHuyhJ+bGZFEEBZkCHSRhmvzQVAQpYamagpgdInXMssdLf7znrNtgduNBZBFkcsPqK8LqR42LK0EV4SZ9GUo8nkokP/yXRxuc1Xbhn9Ev7JMHP/bEgkPOpw1JyX+2ny9B1BZEikhk5Dt8SF/IEsSZHghrIh3qCRvGQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619778979; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LCSM795lit02iUbRuFeeRsvWeeO13Mxp9oArfvKi8Bs=; b=my2kL6toY15U960xQHwGBKVZl3vAeGiPDfdXrJkAdYf4OQyt2MjB89tkFaH82sQKrReAssJWoPw/9cgk76WyhmZHTN/gvnzcRR8Bq9nrVsAkkMjijY5DzQzNyiCMJsP1KLXeCqQx03tSfFt7mTTnsqCgQ6e6T8+MGT8Gw2dR6UQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619778979921589.5415536890185; Fri, 30 Apr 2021 03:36:19 -0700 (PDT) Received: from localhost ([::1]:56522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQVO-0000YB-Ns for importer@patchew.org; Fri, 30 Apr 2021 06:36:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTr-0007DG-66 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:43 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:40667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTp-00019h-Hg for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:42 -0400 Received: by mail-wr1-x432.google.com with SMTP id d4so1560655wru.7 for ; Fri, 30 Apr 2021 03:34:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LCSM795lit02iUbRuFeeRsvWeeO13Mxp9oArfvKi8Bs=; b=oQCshL7f5SG/1Fu4jTlZUst03MTlzhnYyCfCeDBSZUChl/ORsBVrejm8lFrgctb8AF C6KxsYoVQiK/HcfaXmEezytNi4G/MpGka1ouTqEuiAkzIG0q3JyYUO4WFgluyZIpEf3X ZsZvPwmVIir2Y8mztFHywxUZQqWkrNOZ1plUXF0hLVY/LK5LaAQUXuoU3OufpMLhlUrr +ae7ZtIs6ptQEKWLIGqbudVclmBuDpHHmJdpjvIjVcgLcGTHE3mTU2kEI83p4+9ZpD5s N20qpZgU/UbgRieX/XW/akLZwX/wTSTZzNDLgIgKN8qS2jmN1W1RIKn/7zpUE9WyYZ5l bdWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LCSM795lit02iUbRuFeeRsvWeeO13Mxp9oArfvKi8Bs=; b=JdTvOkqhDxV1d6Fx6gJJqoi7OhN4jJ+gxMpthVerSQIX9/I/wykymMXhip9lnFvhv0 +qyIPH7ItYEi6YXjnjNpZcyGl7edLIyVpPcdMTdBfdw65md3AHBrFvSSwzbZR7f3LDzw 0Hi2PjA68CpGGGhu74USIslhx2lC2aZDJPJa/fk5KSS1HAb+oF+j9l3J6drDigsvCdqb EutLFlUaZrtnO6xvlU4n3TTvGjYE53AvKGAFxHvsx87hIstL68q/b1qYOebi0QFX6j3D cIo/rzXWayUk3BA79GkdUnMxl5P2LbTlIE3VsVCiqtUIwS7rBweKVhdbjvUeSGF9aIN3 8LMw== X-Gm-Message-State: AOAM530mIW+1I1Q/0laR2RuFXbbFVt1TAOmMCVOUax/yiu2E8ye0c7YS lZok8O8GotLe/OXKjrhndFZWzCfSvbD8DhZN X-Google-Smtp-Source: ABdhPJzCoazBjA5NjnpjmllVccWjuCXbUTZLg+JXt2/44c8doESxwtaB/66y9g8nX9Kyw3f9ivgbWA== X-Received: by 2002:adf:dd52:: with SMTP id u18mr5879456wrm.32.1619778880097; Fri, 30 Apr 2021 03:34:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule Date: Fri, 30 Apr 2021 11:33:55 +0100 Message-Id: <20210430103437.4140-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Kunkun Jiang The driver can query some bits in SMMUv3 IDR5 to learn which translation granules are supported. Arm recommends that SMMUv3 implementations support at least 4K and 64K granules. But in the vSMMUv3, there seems to be no reason not to support 16K translation granule. In addition, if 16K is not supported, vSVA will failed to be enabled in the future for 16K guest kernel. So it'd better to support it. Signed-off-by: Kunkun Jiang Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 87056125357..228dc54b0bc 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -259,8 +259,9 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, HAD, 1); =20 - /* 4K and 64K granule support */ + /* 4K, 16K and 64K granule support */ s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 b= its */ =20 @@ -503,7 +504,8 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEve= ntInfo *event) =20 tg =3D CD_TG(cd, i); tt->granule_sz =3D tg2granule(tg, i); - if ((tt->granule_sz !=3D 12 && tt->granule_sz !=3D 16) || CD_ENDI(= cd)) { + if ((tt->granule_sz !=3D 12 && tt->granule_sz !=3D 14 && + tt->granule_sz !=3D 16) || CD_ENDI(cd)) { goto bad_cd; } =20 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619778981; cv=none; d=zohomail.com; s=zohoarc; b=cHMpDVcrwNJlv5+7gMmGpM/DxkWJtNY2MHBejK0Acf7FImBvxbtKpmPF4fcmm/KP+UAyRUx58bCnHexKBXmaSxRL1czCwsNNf12LgtA1fZGnPleqY++7LcydyI8tuYS22tC3W0uzMA0zYIssQiUNFaAfiR9o0T2ysyJcBWQWaYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619778981; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4RgA8HjnjL0l3ff1bCKNaUeJ1xTQM5jESG7yIxF8FWg=; b=BfMlD2YolRn0pchMo+BVwITZNuTJC6SgLMLxJ4Uv8n/HH05nwJe4dXo6dCRaVVkaFXz7D2/XmINVvy/vUYtlwC9l4ptPdXpFBzYtf5MVgN1Zxwpabl5qsMknqVQ0/C9noTclSb00pWWZtzrzQM8pvdfh7QaVXbpZVv+JsICKglc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619778981118177.5799050747969; Fri, 30 Apr 2021 03:36:21 -0700 (PDT) Received: from localhost ([::1]:56718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQVP-0000d4-Uf for importer@patchew.org; Fri, 30 Apr 2021 06:36:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTs-0007DV-KH for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:44 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:46946) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTq-0001A2-8X for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:44 -0400 Received: by mail-wr1-x42b.google.com with SMTP id x5so19716015wrv.13 for ; Fri, 30 Apr 2021 03:34:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4RgA8HjnjL0l3ff1bCKNaUeJ1xTQM5jESG7yIxF8FWg=; b=fw4RIwLwIHts1m6aizZO44ElucVarrwjYk4JaJXb7cRitnMKIekVGQCBbk/m5W5cib XfzYUGLsqahTL9/mqK9iF077/h7d34K0Ey9jglR+77nTYRFIAo9mg5LZOKwpsYRawuXb BsMPHEOlYOs1JIt4y8nAj7EWvflEjVqyoOLWCeC0gq1yyDlrtQ/sBPqgyZUnXvURODn4 7e2SG56yQwafmWhzvK/mQsxjEnQkQA5+nQepyzeKG3/w+F7wSHupsuMQVOWPdn+uZ+dX f2hcWfoUHvDTI1g8MsztsT6ulsqTTINivvaFTEKy4lquynI6qK6bwqivHhYYuuRR03RU wNfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4RgA8HjnjL0l3ff1bCKNaUeJ1xTQM5jESG7yIxF8FWg=; b=DigBCuXTjplgSikLt5+YnJMxcDX0Fm5titt1whLLlTmAAo64aW9XYcPXnnKky2qxfL pLWOgajNmaBO+iXu5Vnm/kNbzpJlomO1wE69Q3bILeeBqineyUHeH7X4oARn7vNdDqIB eRYiMQ+U1AhKsd2FSARcF3lvFbLHXSL3XftN4ae8Q1WBX7hIgluVo5f6IQUW1RgrVM2e yhDJwk1Jx5JKj20z2rCKk4l1nyGKJAkGHzXv08RZnaCsWnZzzZTpj/4Bkc+aTaxfOExT ynEV4SUg8VTQvfzsWSqHaM5SHb3j5kqKXdURM6cXFkcOuQKVwCqePXS1mg93N6Tq/LOr re/Q== X-Gm-Message-State: AOAM531wdCeHfWt3Sezn+CrmW4Ha4upfwmy9skSXR1RJYau+TLRtXUZX MEjCtFQs0vEf5r2VXH3cAGGmWRC8FX5hFhhG X-Google-Smtp-Source: ABdhPJzn7ZaZZI0qHi0OfMPduqlcGuT01Tqcx5OhU9SsV0XWHqpHKxdCSCE9EBY5wS43mT+ra+tT3w== X-Received: by 2002:adf:d0c1:: with SMTP id z1mr6024034wrh.404.1619778880716; Fri, 30 Apr 2021 03:34:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111 Date: Fri, 30 Apr 2021 11:33:56 +0100 Message-Id: <20210430103437.4140-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The Arm ARM specifies that for Thumb encodings of the various plain store insns, if the Rn field is 1111 then we must UNDEF. This is different from the Arm encodings, where this case is either UNPREDICTABLE or has well-defined behaviour. The exclusive stores, store-release and STRD do not have this UNDEF case for any encoding. Enforce the UNDEF for this case in the Thumb plain store insns. Fixes: https://bugs.launchpad.net/qemu/+bug/1922887 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210408162402.5822-1-peter.maydell@linaro.org --- target/arm/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7103da2d7ab..68809e08f09 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6476,6 +6476,14 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr= *a, ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; TCGv_i32 addr, tmp; =20 + /* + * In Thumb encodings of stores Rn=3D1111 is UNDEF; for Arm it + * is either UNPREDICTABLE or has defined behaviour + */ + if (s->thumb && a->rn =3D=3D 15) { + return false; + } + addr =3D op_addr_rr_pre(s, a); =20 tmp =3D load_reg(s, a->rt); @@ -6620,6 +6628,14 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri= *a, ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; TCGv_i32 addr, tmp; =20 + /* + * In Thumb encodings of stores Rn=3D1111 is UNDEF; for Arm it + * is either UNPREDICTABLE or has defined behaviour + */ + if (s->thumb && a->rn =3D=3D 15) { + return false; + } + addr =3D op_addr_ri_pre(s, a); =20 tmp =3D load_reg(s, a->rt); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619778981; cv=none; d=zohomail.com; s=zohoarc; b=k54IwOXiHaVPVzxreu8hVAs1ygg89qZ/cPtSq5FhLcV6id9Eo3ZW2A0BqIwtOO3I1Ru+stJtKonGp59XVQBS7heV/rZIn5LxrV6WjnWcnbWZ7Gk2s7aNlNxEW8RK5vQvtYO5i5t1EfklioboIa1PIPqqoptKyflqTabuhJHwDaw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619778981; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Kw7jlqwrr+zV0rxqtI5yMdWAi84d/FR8/panxBOgGv8=; b=Dc2N3lSgbQz5wRZadf+aEzoG+owu1PPOnsxp3QDkC2HahbXsGB0CFO6d4YcKsFxG15VDP907TKyn/kDC6HWyiPvQfYh1d0tKHbDpRXo5loLz22NRxidXes94mtoLRVUf8XzWzEdtRTyqMq4U8+jWMLsl7hA7f09okVSOZGNxBCQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619778981680475.25826286303163; Fri, 30 Apr 2021 03:36:21 -0700 (PDT) Received: from localhost ([::1]:56730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQVQ-0000dT-Du for importer@patchew.org; Fri, 30 Apr 2021 06:36:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTt-0007De-BA for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:45 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:35459) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTq-0001AP-Pf for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:44 -0400 Received: by mail-wm1-x329.google.com with SMTP id 26-20020a05600c22dab029013efd7879b8so1486654wmg.0 for ; Fri, 30 Apr 2021 03:34:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Kw7jlqwrr+zV0rxqtI5yMdWAi84d/FR8/panxBOgGv8=; b=kN16AM3arv2GLXKm1VmhdhSAfbFDp3sA5L7929x3jmWhZtiReD+xm8ZqxoQDcHbdma eaACS8miAY2WgkfsbH2uTwF/XwATAS99P61/gOne5kq39Ew4mGwj2wPexmZaYYodNp+x Rl9pggCCPQ5HCmtBnRPi3vkTkaRL3hCLhgromAfwDVkvJK/vkUE/TGq8zovgBvVOK+qm ZzVeVFa/ct8YteyH5J19bMmlPPBEmcoPCLZQ4+KeH/DgBnxlIQ3ZAvpNOzygLYukgmT7 vlJVjhxYEuMIB7YFMicHnCtCjJhSggsdq2V/h8S9GOWu8ggdOSoVIkgIiq10fC5khSfn 6r6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kw7jlqwrr+zV0rxqtI5yMdWAi84d/FR8/panxBOgGv8=; b=qk4KmKLPig/f6PQRhf+TVIvDBZPG1y8C6HYZG4s8PU4Dzwu4Ksf0PXid0nAHK2FOps RqXIl9ufTBvD4zDWFycSpF0N41rkUm+2iPTE/dV3U2tqIQHGKEwqld+jkEbuO6OlhR4J nHeimBvBdAy9YWQTtg0UTsd60iNj9KMmu1s+3uKh/QnPp1kvY/x+I91a84XqwQcbY/90 sXl6oiO4uQxuVPzjLzos/3wAiZUoeAPVGyinj4XaD3/QOw2DS5x2nQnaNLJtPHGtfecD OYpefKrSxnenagGcZhvszS/3W/ppTT2MrDEyHw6Y0cj3WQIBdZ4wbCuLr1A87j/jyzvn fG1w== X-Gm-Message-State: AOAM530xpFgYrwA7eiovS/l6jfAjYCBhvPMsknvZ9k0wGgK35r77VrWW UBsy3++hSLmcPOCAak8O3wG0Sxz44LRlOSq9 X-Google-Smtp-Source: ABdhPJwZUmN/SXB9KtHXGzI5u9E9fjpFb/KFJDwXtl+vg6rBvVHjPqBiEKGt5szx10JttZY/XNg8FA== X-Received: by 2002:a1c:7c15:: with SMTP id x21mr306882wmc.186.1619778881416; Fri, 30 Apr 2021 03:34:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/43] target/arm: Fix mte_checkN Date: Fri, 30 Apr 2021 11:33:57 +0100 Message-Id: <20210430103437.4140-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. Therefore, the first failure is always either the first byte of the access, or the first byte of the granule. In addition, some of the arithmetic is off for last-first -> count. This does not become directly visible until a later patch that passes single bytes into this function, so ptr =3D=3D ptr_last. Buglink: https://bugs.launchpad.net/bugs/1921948 Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: tweaked a comment] Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 8be17e1b707..010d1c2e993 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -757,10 +757,10 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { int mmu_idx, ptr_tag, bit55; - uint64_t ptr_last, ptr_end, prev_page, next_page; - uint64_t tag_first, tag_end; - uint64_t tag_byte_first, tag_byte_end; - uint32_t esize, total, tag_count, tag_size, n, c; + uint64_t ptr_last, prev_page, next_page; + uint64_t tag_first, tag_last; + uint64_t tag_byte_first, tag_byte_last; + uint32_t total, tag_count, tag_size, n, c; uint8_t *mem1, *mem2; MMUAccessType type; =20 @@ -779,29 +779,27 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, =20 mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); type =3D FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_= LOAD; - esize =3D FIELD_EX32(desc, MTEDESC, ESIZE); total =3D FIELD_EX32(desc, MTEDESC, TSIZE); =20 - /* Find the addr of the end of the access, and of the last element. */ - ptr_end =3D ptr + total; - ptr_last =3D ptr_end - esize; + /* Find the addr of the end of the access */ + ptr_last =3D ptr + total - 1; =20 /* Round the bounds to the tag granule, and compute the number of tags= . */ tag_first =3D QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); - tag_end =3D QEMU_ALIGN_UP(ptr_last, TAG_GRANULE); - tag_count =3D (tag_end - tag_first) / TAG_GRANULE; + tag_last =3D QEMU_ALIGN_DOWN(ptr_last, TAG_GRANULE); + tag_count =3D ((tag_last - tag_first) / TAG_GRANULE) + 1; =20 /* Round the bounds to twice the tag granule, and compute the bytes. */ tag_byte_first =3D QEMU_ALIGN_DOWN(ptr, 2 * TAG_GRANULE); - tag_byte_end =3D QEMU_ALIGN_UP(ptr_last, 2 * TAG_GRANULE); + tag_byte_last =3D QEMU_ALIGN_DOWN(ptr_last, 2 * TAG_GRANULE); =20 /* Locate the page boundaries. */ prev_page =3D ptr & TARGET_PAGE_MASK; next_page =3D prev_page + TARGET_PAGE_SIZE; =20 - if (likely(tag_end - prev_page <=3D TARGET_PAGE_SIZE)) { + if (likely(tag_last - prev_page <=3D TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ - tag_size =3D (tag_byte_end - tag_byte_first) / (2 * TAG_GRANULE); + tag_size =3D ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)= ) + 1; mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, total, MMU_DATA_LOAD, tag_size, ra); if (!mem1) { @@ -815,9 +813,9 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, next_page - p= tr, MMU_DATA_LOAD, tag_size, ra); =20 - tag_size =3D (tag_byte_end - next_page) / (2 * TAG_GRANULE); + tag_size =3D ((tag_byte_last - next_page) / (2 * TAG_GRANULE)) + 1; mem2 =3D allocation_tag_mem(env, mmu_idx, next_page, type, - ptr_end - next_page, + ptr_last - next_page + 1, MMU_DATA_LOAD, tag_size, ra); =20 /* @@ -838,15 +836,13 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, } =20 /* - * If we failed, we know which granule. Compute the element that - * is first in that granule, and signal failure on that element. + * If we failed, we know which granule. For the first granule, the + * failure address is @ptr, the first byte accessed. Otherwise the + * failure address is the first byte of the nth granule. */ if (unlikely(n < tag_count)) { - uint64_t fail_ofs; - - fail_ofs =3D tag_first + n * TAG_GRANULE - ptr; - fail_ofs =3D ROUND_UP(fail_ofs, esize); - mte_check_fail(env, desc, ptr + fail_ofs, ra); + uint64_t fault =3D (n =3D=3D 0 ? ptr : tag_first + n * TAG_GRANULE= ); + mte_check_fail(env, desc, fault, ra); } =20 done: --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619778981; cv=none; d=zohomail.com; s=zohoarc; b=HiLeVU7P/yK2HSA7AkHa62SerYbPnemEBmScdzGQJQTZ9p9XqTLXWH2L0zl4LkQoRtf6UpdF2ok/a07kz6psnRADaSMjvTGcPWGkkZuv1iuh6mIiGKyL78B1YmeMOLCuO/UYCAxzDbeMTGNk0z9PrA4tFtQry07D7zsmKoD4+WU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619778981; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7k0slS5Qm8ux3QGcdgPebP+Vvjs6axythBtwet2XXQQ=; b=SKMg25OuWVfMmMvpWnDEL4R1KlFb7n0dNQ07tm1/uyUQ/DxrnvYrBRt0MRMxpvyq0L74l6DU+9JgJkH6V0hykLmqJv7IQQTGpEp5lkyROK3fuyNKa0vk1sIz2R2aGWa2rfJ3Rob4XWVaRsO71j3yZ+fwYSfRqirN5iaYQq27KKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619778981798269.2489177559056; Fri, 30 Apr 2021 03:36:21 -0700 (PDT) Received: from localhost ([::1]:56782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQVQ-0000eq-OI for importer@patchew.org; Fri, 30 Apr 2021 06:36:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTt-0007Dj-JE for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:45 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:38885) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTr-0001BR-IA for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:45 -0400 Received: by mail-wr1-x434.google.com with SMTP id l14so149049wrx.5 for ; Fri, 30 Apr 2021 03:34:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7k0slS5Qm8ux3QGcdgPebP+Vvjs6axythBtwet2XXQQ=; b=PvmwHtjO28+FV+/4VTluLx6C0P+9BAC9oQkBH2cPCdZrVV6jhDq3s2pkV4tskjooLr g1b3yy8U4nrAC3zihxHSoLL+ZxlFHIYK6RulecywOJ2QyV2lwAtZEGAhRr96HSvVyA+F 7/3A1NtYzsVNy03BJQycPzSzhXMb2tTqNQ8cHRdV1MESTyq5+TiD4poEGUFvMWNdiJue YcZntlvg0gKcKimZ22C88asr/tK/Isj34Dufbze2y04RNLvc/xaimTqzetrWny4WBnaA idwYgw9LPzKo/PBC5CYW90IgaQxEW0bVZYHfXsGTzQoJ8ihXuMqGUQY2o4diz8v2HkL1 p1wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7k0slS5Qm8ux3QGcdgPebP+Vvjs6axythBtwet2XXQQ=; b=PBNW4dlheD+Mra0pfv5gMq17jUeeh0csNXa2lUe0+neffSLIRoBLM2ELKpgZ7y0JAn 4rhTyyTdpDyDUIMCkY51VbkPU7kiOxnhJt31pON6D7Bqc9erS2rQCfNOuBEt+QO13FM5 QWX/f5islYuo6ydU1tlbZZ+NPp/vKvL2f3vOXDUfAWa+Ag6wBgCLi6Y2pK01E8zRmIp5 wPYNOtQJ7YbVg8UJVkacKtpj2On/ISPRkzfxgb9dn/vg1LvSDetYc7fM3tqnCrGdf4vW JB4YNLeDXsfst+n455FzTeEj7+P6CcJsfU09DfBsjXuI7HvSYNmPb3hv5yBWeRPSGmjL 2nLw== X-Gm-Message-State: AOAM533kgQLrElhCChmsiMDLiw6E9w2qyYTqSgM22wFjKcWkwK6Rz0lv xXbo5iKPyKBeqrPksjAP6q6+2I5GQT0l98e6 X-Google-Smtp-Source: ABdhPJyEHZlC8VICNtEw/PYehgVs0CsHQGBxSTKgcy88Wtxbnqdo7h7yHEAD8sh7Pbp90t+Mb0mj9A== X-Received: by 2002:a5d:4386:: with SMTP id i6mr307500wrq.207.1619778882277; Fri, 30 Apr 2021 03:34:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/43] target/arm: Split out mte_probe_int Date: Fri, 30 Apr 2021 11:33:58 +0100 Message-Id: <20210430103437.4140-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Split out a helper function from mte_checkN to perform all of the checking and address manpulation. So far, just use this in mte_checkN itself. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 52 +++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 010d1c2e993..2b5331f8dbc 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -753,33 +753,45 @@ static int checkN(uint8_t *mem, int odd, int cmp, int= count) return n; } =20 -uint64_t mte_checkN(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) +/** + * mte_probe_int() - helper for mte_probe and mte_check + * @env: CPU environment + * @desc: MTEDESC descriptor + * @ptr: virtual address of the base of the access + * @fault: return virtual address of the first check failure + * + * Internal routine for both mte_probe and mte_check. + * Return zero on failure, filling in *fault. + * Return negative on trivial success for tbi disabled. + * Return positive on success with tbi enabled. + */ +static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, + uintptr_t ra, uint32_t total, uint64_t *fault) { int mmu_idx, ptr_tag, bit55; uint64_t ptr_last, prev_page, next_page; uint64_t tag_first, tag_last; uint64_t tag_byte_first, tag_byte_last; - uint32_t total, tag_count, tag_size, n, c; + uint32_t tag_count, tag_size, n, c; uint8_t *mem1, *mem2; MMUAccessType type; =20 bit55 =3D extract64(ptr, 55, 1); + *fault =3D ptr; =20 /* If TBI is disabled, the access is unchecked, and ptr is not dirty. = */ if (unlikely(!tbi_check(desc, bit55))) { - return ptr; + return -1; } =20 ptr_tag =3D allocation_tag_from_addr(ptr); =20 if (tcma_check(desc, bit55, ptr_tag)) { - goto done; + return 1; } =20 mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); type =3D FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_= LOAD; - total =3D FIELD_EX32(desc, MTEDESC, TSIZE); =20 /* Find the addr of the end of the access */ ptr_last =3D ptr + total - 1; @@ -803,7 +815,7 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, total, MMU_DATA_LOAD, tag_size, ra); if (!mem1) { - goto done; + return 1; } /* Perform all of the comparisons. */ n =3D checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); @@ -829,23 +841,39 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, } if (n =3D=3D c) { if (!mem2) { - goto done; + return 1; } n +=3D checkN(mem2, 0, ptr_tag, tag_count - c); } } =20 + if (likely(n =3D=3D tag_count)) { + return 1; + } + /* * If we failed, we know which granule. For the first granule, the * failure address is @ptr, the first byte accessed. Otherwise the * failure address is the first byte of the nth granule. */ - if (unlikely(n < tag_count)) { - uint64_t fault =3D (n =3D=3D 0 ? ptr : tag_first + n * TAG_GRANULE= ); - mte_check_fail(env, desc, fault, ra); + if (n > 0) { + *fault =3D tag_first + n * TAG_GRANULE; } + return 0; +} =20 - done: +uint64_t mte_checkN(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + uint64_t fault; + uint32_t total =3D FIELD_EX32(desc, MTEDESC, TSIZE); + int ret =3D mte_probe_int(env, desc, ptr, ra, total, &fault); + + if (unlikely(ret =3D=3D 0)) { + mte_check_fail(env, desc, fault, ra); + } else if (ret < 0) { + return ptr; + } return useronly_clean_ptr(ptr); } =20 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779186; cv=none; d=zohomail.com; s=zohoarc; b=SZUH56HfrKH5MzrIjcEUxqHUl7tmRpi/4x2ljowU3mmEi/4CJSrQ2G9//CEP5aCywl/Ux7CHnQHwpH+/40Ou1v0k8ThjJhQR1EgTz+KlkbQDIeqT42BF4AyODkQUfgPF3UwF1tjVhiS0Jy+vBc0k2Ce7oNZ2hX40TGVkWr9wls4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779186; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hDecypmLsBixP4oL8UwqI6CKcvvOLSatSEv+SoClHSc=; b=NGU6h4Cp3sOvcjGmK9/Vg5xqBlIdrkQihUL+qdHPZUPQqilKgF5Bpmc9obScWwRvEhudNziQE8cNFdK0lOT/MwjEAIMtzi0jbMp5eC4VS1jZhrVs++3mfO69GC4uZixdzq2CcaidOA1HG14CQdenHtvdkctODQ4IeEMKOAkAKMk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779186705842.2812317363778; Fri, 30 Apr 2021 03:39:46 -0700 (PDT) Received: from localhost ([::1]:40104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQYj-0005Sq-Lu for importer@patchew.org; Fri, 30 Apr 2021 06:39:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTw-0007H7-7k for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:48 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46950) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTs-0001C2-Hx for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:47 -0400 Received: by mail-wr1-x42f.google.com with SMTP id x5so19716149wrv.13 for ; Fri, 30 Apr 2021 03:34:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hDecypmLsBixP4oL8UwqI6CKcvvOLSatSEv+SoClHSc=; b=J/aEd8rmJhsMy2ZV99gYVSpkn8CNHz6OwVdRYEMO9I7zQ5/AedRhJy/qbwNBv0Lga/ 1iVty3xeCYb0VMjREqt8WgMgePFADHifJvJa+oGGD7FbPqMWRlPVwSO5SuWxIf2vvcgg UJ95u8OG0S7+50l0Yq1nADtsd18dWZ4SLvxknZ2SQkz4nnFBHfJZLhA/bQbab5AVKLuB cFgX7iimhsaswAeznT2WlIonLxng0M1FFiYgK2/8+t2jaR1+ClCFooXFbCqBi3m3yjnf iUdOG6Y4/WEmiGrFV5ItDcFGdjxXAJ8znN36x77137YPmqztbeCXaLKQvP7IgEUqr/yO 4dBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hDecypmLsBixP4oL8UwqI6CKcvvOLSatSEv+SoClHSc=; b=pjLMUAo5eHucZRlTlvfKeWk7rfFYXHRMjNhDC9D9IJ8+PLKQBhuYGp5FQVDD6EHOtf 5tFMiZQu0QSFZ2xOlhBgKqf5QORqYIEwrV38fjic4kTKyEY9dxpE3CNWKViHkVuIJn3o VonahrRWrUB8cGhAJLChe2zYdLiNrWRz482Et8VnWHCAWhwjHUIAFPFkLI/jVQgluaSe v4/wLtcdcDw/x5dCCunGuO1Ke4xFhpi1k2CrN4I+mbIDQKa0cT/g7svgQ7Tr6980t1Sj vmCrr6Zwyk0W8c1/dHMdpXY51YEOhOH7hCx7B26rWc8332m/QdihrPoNLR2EAo0Hc48K ghqg== X-Gm-Message-State: AOAM5317+DuVLSCJ4dS572ZzMvj16ahmM98BIu5yyVg11vM/iWaOyglt rKsW1WnQWqvPfNwlXNkI2u4KFBvPDGjd+fJv X-Google-Smtp-Source: ABdhPJyZBunLqueD8srdVuQs59IirqehUFBEiOHyKkJ85gO9A5yeLg6CN0GmqrhSBPrRp/AAqtQ+pg== X-Received: by 2002:adf:f3c1:: with SMTP id g1mr6004121wrp.344.1619778883150; Fri, 30 Apr 2021 03:34:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1 Date: Fri, 30 Apr 2021 11:33:59 +0100 Message-Id: <20210430103437.4140-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. We cannot tell a priori whether or not a given scalar access is aligned, therefore we must at least check. Use mte_probe_int, which is already set up for checking multiple granules. Buglink: https://bugs.launchpad.net/bugs/1921948 Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 109 +++++++++++++--------------------------- 1 file changed, 35 insertions(+), 74 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 2b5331f8dbc..0ee0397eb26 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -617,80 +617,6 @@ static void mte_check_fail(CPUARMState *env, uint32_t = desc, } } =20 -/* - * Perform an MTE checked access for a single logical or atomic access. - */ -static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr, - uintptr_t ra, int bit55) -{ - int mem_tag, mmu_idx, ptr_tag, size; - MMUAccessType type; - uint8_t *mem; - - ptr_tag =3D allocation_tag_from_addr(ptr); - - if (tcma_check(desc, bit55, ptr_tag)) { - return true; - } - - mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); - type =3D FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_= LOAD; - size =3D FIELD_EX32(desc, MTEDESC, ESIZE); - - mem =3D allocation_tag_mem(env, mmu_idx, ptr, type, size, - MMU_DATA_LOAD, 1, ra); - if (!mem) { - return true; - } - - mem_tag =3D load_tag1(ptr, mem); - return ptr_tag =3D=3D mem_tag; -} - -/* - * No-fault version of mte_check1, to be used by SVE for MemSingleNF. - * Returns false if the access is Checked and the check failed. This - * is only intended to probe the tag -- the validity of the page must - * be checked beforehand. - */ -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - int bit55 =3D extract64(ptr, 55, 1); - - /* If TBI is disabled, the access is unchecked. */ - if (unlikely(!tbi_check(desc, bit55))) { - return true; - } - - return mte_probe1_int(env, desc, ptr, 0, bit55); -} - -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) -{ - int bit55 =3D extract64(ptr, 55, 1); - - /* If TBI is disabled, the access is unchecked, and ptr is not dirty. = */ - if (unlikely(!tbi_check(desc, bit55))) { - return ptr; - } - - if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) { - mte_check_fail(env, desc, ptr, ra); - } - - return useronly_clean_ptr(ptr); -} - -uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - return mte_check1(env, desc, ptr, GETPC()); -} - -/* - * Perform an MTE checked access for multiple logical accesses. - */ - /** * checkN: * @tag: tag memory to test @@ -882,6 +808,41 @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t= desc, uint64_t ptr) return mte_checkN(env, desc, ptr, GETPC()); } =20 +uint64_t mte_check1(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + uint64_t fault; + uint32_t total =3D FIELD_EX32(desc, MTEDESC, ESIZE); + int ret =3D mte_probe_int(env, desc, ptr, ra, total, &fault); + + if (unlikely(ret =3D=3D 0)) { + mte_check_fail(env, desc, fault, ra); + } else if (ret < 0) { + return ptr; + } + return useronly_clean_ptr(ptr); +} + +uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return mte_check1(env, desc, ptr, GETPC()); +} + +/* + * No-fault version of mte_check1, to be used by SVE for MemSingleNF. + * Returns false if the access is Checked and the check failed. This + * is only intended to probe the tag -- the validity of the page must + * be checked beforehand. + */ +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + uint64_t fault; + uint32_t total =3D FIELD_EX32(desc, MTEDESC, ESIZE); + int ret =3D mte_probe_int(env, desc, ptr, 0, total, &fault); + + return ret !=3D 0; +} + /* * Perform an MTE checked access for DC_ZVA. */ --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779145; cv=none; d=zohomail.com; s=zohoarc; b=GIQFw9WDjyA4BQYbdhTLeiUGOsV7R6dEDSKXYpeUEWECAU+Yu3vCrEwHZkWl1YNqAuU5vGB7I/qHxdC6/s32zOTtOfDVAEu8TM23XoO9sbZ1SZ/szFajDmAXyY9cB4Yy9p91QI++MTkU601JdJui9oJwTGOcJdI29ANt0y7ma9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779145; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v6VR+9uD8w53hdaBHlYSsfUrEwCJ0liC3DgXabSgbPw=; b=nzU+R3ABt/IUOal7++xa0jqK7d4SkUEQo0Z8Aj36ALl7R8aMpmsN59yswIRfASm/yQll3q3pTDhDFE+aoWgmToYHnwXhY6l6pkTIsCpYghVW2/R1SGHfgiqtqtOATU7D0PjEKyoqjAwMR7XXhAwLXgafY88HYeRyyA2ucN503VU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779145908903.8617082257144; Fri, 30 Apr 2021 03:39:05 -0700 (PDT) Received: from localhost ([::1]:36930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQY4-00049c-Te for importer@patchew.org; Fri, 30 Apr 2021 06:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTv-0007Ga-LX for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:48 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:33465) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTt-0001CN-LQ for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:47 -0400 Received: by mail-wr1-x42d.google.com with SMTP id n2so16824566wrm.0 for ; Fri, 30 Apr 2021 03:34:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v6VR+9uD8w53hdaBHlYSsfUrEwCJ0liC3DgXabSgbPw=; b=ClkUQlMzaYVXTH4QNGOwe3OlzzvBSEApxAtxFBpNxRiQycmy/TQ71YomAkHxVPbAij 1GGjTmkFx0VzQlrMOwQJEfcx2HnZRZe4GQlaiy42joYtZMViE0govoToLdSlFXFRbjY7 XM/e/4PePjAT4I2EV31hN8J292kFooiAtVaR2rR4Vt7QYY+g9fPZQ4IGBiMZT6rUaRBm YDw8RZLZEOJVfvK/VtAKNQKyApiNGhOOizLU28rwcm40ZIxKm0ubcIenOedZ+UcDBVMA cwcWFIg6O4jcRFsTxpo955KBKBfUiNzNT7usuaezF4yayAom7fc7c77mn+sbIWDgkmsB Wznw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v6VR+9uD8w53hdaBHlYSsfUrEwCJ0liC3DgXabSgbPw=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Buglink: https://bugs.launchpad.net/bugs/1921948 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/mte-5.c | 44 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/mte-5.c diff --git a/tests/tcg/aarch64/mte-5.c b/tests/tcg/aarch64/mte-5.c new file mode 100644 index 00000000000..6dbd6ab3ea7 --- /dev/null +++ b/tests/tcg/aarch64/mte-5.c @@ -0,0 +1,44 @@ +/* + * Memory tagging, faulting unaligned access. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code =3D=3D SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + void *p0, *p1, *p2; + long excl =3D 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 =3D alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction =3D pass; + sa.sa_flags =3D SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* Store store two different tags in sequential granules. */ + asm("stg %0, [%0]" : : "r"(p1)); + asm("stg %0, [%0]" : : "r"(p2 + 16)); + + /* Perform an unaligned load crossing the granules. */ + asm volatile("ldr %0, [%1]" : "=3Dr"(p0) : "r"(p1 + 12)); + abort(); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 05b2622bfc9..928357b10a9 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -37,7 +37,7 @@ AARCH64_TESTS +=3D bti-2 =20 # MTE Tests ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) -AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 mte-6 +AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-%: CFLAGS +=3D -march=3Darmv8.5-a+memtag endif =20 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zDMhF9whUnim/YaN7x4ONUph6MMcxiKXZ0kw0LzaTLs=; b=dB4wD42ef1Pc4J6N9gtuPzflv3BEY2RVa7NDrTOly4YQuIC1oE62J4nmwGlVZj0L0g 5nQ5fcS9Vu9dsA5I+yZmibVr+axwM/3dEdk+/UILynnYkyk6UVfqiT8+wGst1quPo6FP gJ2Rv7EGdNxGdttRy21BKQI+AFrolNzeDL6nVzdkMtOYLvvDlwGjYT3f8g996YZYPd+N EU11AmfmRSviAehpncj2AUgT2ofGmBf60xbtorb2B2ijzvjezyvLg/9JZQ8b3SKhLBHz gyEo1gg5/D6R6cFoQuyeBvq4TX0YoUO3pQEDMqEsmh/GakovY8NW4+IB82AOfYxbIFTX uefQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zDMhF9whUnim/YaN7x4ONUph6MMcxiKXZ0kw0LzaTLs=; b=sY1Ly/VD9fLZgGYccuLufQUgG+DZwgwcQ7aEdpPKZW6zcslpMryI16UdH4iT6GbaVP iKirM1D7zNhxxh/uhB1+79o3Wa4G14Cqp4yFR69QjGx4Fyp3z585yWcXaRBiZqYdNjwu aGx2BSdCpk8mQLE/jjrWc+cCfFr6CQTmR6W/SXErefJaTZIjUY/jEjBh8GDTdGeex7Ap MWFwOUrYtb29QsyiIMc2Y26U3HRzosSVvagFbzFvmQh15tsW6nmC7BJFpe0D2cUf3a32 ojWVXxzB46LGaXCD3QU5ynIDDSRT8C7kfPgdOgPBXIGKi9ihPiPudZ8ak8mZF+X/Zlux PSzw== X-Gm-Message-State: AOAM533HK+mLAXSvQPpWg9bg6FOVwxUMxBVydMn3TICX4UhezPw4rrDn Bbrc8BPX4wi7l/xYJhD8TtxpHrh5/REH3sOg X-Google-Smtp-Source: ABdhPJy4ABDa9+O9LjlIkNEPv7ZPk97jBuixF6+KXTpl3zhz1XcFZyQj/Si8+7n9HVoc50qI7GLaXw== X-Received: by 2002:adf:e2cc:: with SMTP id d12mr5967317wrj.90.1619778884644; Fri, 30 Apr 2021 03:34:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1 Date: Fri, 30 Apr 2021 11:34:01 +0100 Message-Id: <20210430103437.4140-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson After recent changes, mte_checkN does not use ESIZE, and mte_check1 never used TSIZE. We can combine the two into a single field: SIZEM1. Choose to pass size - 1 because size =3D=3D 0 is never used, our immediate need in mte_probe_int is for the address of the last byte (ptr + size - 1), and since almost all operations are powers of 2, this makes the immediate constant one bit smaller. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 4 ++-- target/arm/mte_helper.c | 18 ++++++++---------- target/arm/translate-a64.c | 5 ++--- target/arm/translate-sve.c | 5 ++--- 4 files changed, 14 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f11bd326962..2c77f2d50f0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H =20 #include "hw/registerfields.h" +#include "tcg/tcg-gvec-desc.h" #include "syndrome.h" =20 /* register banks for CPU modes */ @@ -1142,8 +1143,7 @@ FIELD(MTEDESC, MIDX, 0, 4) FIELD(MTEDESC, TBI, 4, 2) FIELD(MTEDESC, TCMA, 6, 2) FIELD(MTEDESC, WRITE, 8, 1) -FIELD(MTEDESC, ESIZE, 9, 5) -FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ +FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ =20 bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check1(CPUARMState *env, uint32_t desc, diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 0ee0397eb26..804057d3f6e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -692,13 +692,13 @@ static int checkN(uint8_t *mem, int odd, int cmp, int= count) * Return positive on success with tbi enabled. */ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, - uintptr_t ra, uint32_t total, uint64_t *fault) + uintptr_t ra, uint64_t *fault) { int mmu_idx, ptr_tag, bit55; uint64_t ptr_last, prev_page, next_page; uint64_t tag_first, tag_last; uint64_t tag_byte_first, tag_byte_last; - uint32_t tag_count, tag_size, n, c; + uint32_t sizem1, tag_count, tag_size, n, c; uint8_t *mem1, *mem2; MMUAccessType type; =20 @@ -718,9 +718,10 @@ static int mte_probe_int(CPUARMState *env, uint32_t de= sc, uint64_t ptr, =20 mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); type =3D FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_= LOAD; + sizem1 =3D FIELD_EX32(desc, MTEDESC, SIZEM1); =20 /* Find the addr of the end of the access */ - ptr_last =3D ptr + total - 1; + ptr_last =3D ptr + sizem1; =20 /* Round the bounds to the tag granule, and compute the number of tags= . */ tag_first =3D QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); @@ -738,7 +739,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t des= c, uint64_t ptr, if (likely(tag_last - prev_page <=3D TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ tag_size =3D ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)= ) + 1; - mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, total, + mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1, MMU_DATA_LOAD, tag_size, ra); if (!mem1) { return 1; @@ -792,8 +793,7 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { uint64_t fault; - uint32_t total =3D FIELD_EX32(desc, MTEDESC, TSIZE); - int ret =3D mte_probe_int(env, desc, ptr, ra, total, &fault); + int ret =3D mte_probe_int(env, desc, ptr, ra, &fault); =20 if (unlikely(ret =3D=3D 0)) { mte_check_fail(env, desc, fault, ra); @@ -812,8 +812,7 @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { uint64_t fault; - uint32_t total =3D FIELD_EX32(desc, MTEDESC, ESIZE); - int ret =3D mte_probe_int(env, desc, ptr, ra, total, &fault); + int ret =3D mte_probe_int(env, desc, ptr, ra, &fault); =20 if (unlikely(ret =3D=3D 0)) { mte_check_fail(env, desc, fault, ra); @@ -837,8 +836,7 @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t = desc, uint64_t ptr) bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) { uint64_t fault; - uint32_t total =3D FIELD_EX32(desc, MTEDESC, ESIZE); - int ret =3D mte_probe_int(env, desc, ptr, 0, total, &fault); + int ret =3D mte_probe_int(env, desc, ptr, 0, &fault); =20 return ret !=3D 0; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0b42e53500e..3af00ae90ef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -272,7 +272,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); @@ -306,8 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); - desc =3D FIELD_DP32(desc, MTEDESC, TSIZE, total_size); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0eefb612144..5179c1f8363 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4509,8 +4509,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); - desc =3D FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); desc <<=3D SVE_MTEDESC_SHIFT; } else { addr =3D clean_data_tbi(s, addr); @@ -5189,7 +5188,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int p= g, int zm, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); desc <<=3D SVE_MTEDESC_SHIFT; } desc =3D simd_desc(vsz, vsz, desc | scale); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gEptES1vzGILk1HgzB/fRCwsWZWFaXca8aMTyui+Yvo=; b=uj9vPdB3pB4jReGCZRUlFZqORWlnIn8Ic/kq+95pNzf+0d17gOnUkQMmB7Hd1dWJKl m1zLXc45l6sHOhHzzCOX6isLBBCcRn8jKo9tqU87sW7fL5O3b88hElGrrMk406ykMbaO fENKcA2TC3nl4V7UgfZnGZfo0kF7uw8pr5lsmL7QsopBuWM3eJT5+srTmBhcTYYKYYW6 e7w4Z1m65FMmaSDd1hKamu4m3Kp/EyHJzEXpdyyMf6bP+YgaUJ5t8m7iB58jjnJus0LF JDujnFDhJppWGuZexfck6XCDCmoRF3FHav/1x6ZhMvAZWkVOypolFOBo1rFyC5giJcCL fyuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gEptES1vzGILk1HgzB/fRCwsWZWFaXca8aMTyui+Yvo=; b=KtVUnMG2n3vSWXcSADAPHdP6k3JvBMjXMuwHqrpiML5v/yAxZvYFRBn4RKcOA4zXNT P3UnGmxYMd8N6hvFyFSGBy2VI8H3MdxbDiI1zoQbe38hHOL6Y65SZnC7GSlTZW8ZKPtr 9i4oRJTgOveUb5UDK7Jhm74S/CDnI6eYMYwxUGokzxtWQN+UYZYrDseSL4/dUWgfRpY6 cepmz1O1wIFNdJocih1dfOubQzvKgToJc/GfGRNNxNq9gh9CCavLaYMVGh8XVZ0npOSy O2C2X38tl/eZP3zQ8Bk8JqZT4hGDN1zobhc7jjaQ9/KK2++uConjJVLArMDoPN25osH+ Edzg== X-Gm-Message-State: AOAM531FWpNuCB50dcLE73FEW3LwDmozsMX8idaLeKn+7avjo1sOCF69 ihXZsTkY8k3IksCpe8kiD0kyfuXg157cfovc X-Google-Smtp-Source: ABdhPJyBo6U5HypkyOxHeYrUUxBETNh8Q5pVCd/OtzbIxGSQ72YGSDPX47XpQyjTP1nbObegnthcmw== X-Received: by 2002:a5d:5254:: with SMTP id k20mr3120483wrc.62.1619778885370; Fri, 30 Apr 2021 03:34:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/43] target/arm: Merge mte_check1, mte_checkN Date: Fri, 30 Apr 2021 11:34:02 +0100 Message-Id: <20210430103437.4140-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The mte_check1 and mte_checkN functions are now identical. Drop mte_check1 and rename mte_checkN to mte_check. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 3 +-- target/arm/internals.h | 5 +---- target/arm/mte_helper.c | 26 +++----------------------- target/arm/sve_helper.c | 14 +++++++------- target/arm/translate-a64.c | 4 ++-- 5 files changed, 14 insertions(+), 38 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index c139fa81f94..7b706571bb4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,8 +104,7 @@ DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 -DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) -DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) +DEF_HELPER_FLAGS_3(mte_check, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2c77f2d50f0..af1db2cd9c9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1146,10 +1146,7 @@ FIELD(MTEDESC, WRITE, 8, 1) FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ =20 bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra); -uint64_t mte_checkN(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra); +uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra); =20 static inline int allocation_tag_from_addr(uint64_t ptr) { diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 804057d3f6e..c91d561ce33 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -789,8 +789,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t des= c, uint64_t ptr, return 0; } =20 -uint64_t mte_checkN(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) +uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra) { uint64_t fault; int ret =3D mte_probe_int(env, desc, ptr, ra, &fault); @@ -803,28 +802,9 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, return useronly_clean_ptr(ptr); } =20 -uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) +uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr) { - return mte_checkN(env, desc, ptr, GETPC()); -} - -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) -{ - uint64_t fault; - int ret =3D mte_probe_int(env, desc, ptr, ra, &fault); - - if (unlikely(ret =3D=3D 0)) { - mte_check_fail(env, desc, fault, ra); - } else if (ret < 0) { - return ptr; - } - return useronly_clean_ptr(ptr); -} - -uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - return mte_check1(env, desc, ptr, GETPC()); + return mte_check(env, desc, ptr, GETPC()); } =20 /* diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index fd6c58f96a8..b63ddfc7f91 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4442,7 +4442,7 @@ static void sve_cont_ldst_mte_check1(SVEContLdSt *inf= o, CPUARMState *env, uintptr_t ra) { sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_check1); + mtedesc, ra, mte_check); } =20 static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, @@ -4451,7 +4451,7 @@ static void sve_cont_ldst_mte_checkN(SVEContLdSt *inf= o, CPUARMState *env, uintptr_t ra) { sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_checkN); + mtedesc, ra, mte_check); } =20 =20 @@ -4826,7 +4826,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, if (fault =3D=3D FAULT_FIRST) { /* Trapping mte check for the first-fault element. */ if (mtedesc) { - mte_check1(env, mtedesc, addr + mem_off, retaddr); + mte_check(env, mtedesc, addr + mem_off, retaddr); } =20 /* @@ -5373,7 +5373,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, info.attrs, BP_MEM_READ, reta= ddr); } if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } host_fn(&scratch, reg_off, info.host); } else { @@ -5386,7 +5386,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, BP_MEM_READ, retaddr); } if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, &scratch, reg_off, addr, retaddr); } @@ -5552,7 +5552,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, */ addr =3D base + (off_fn(vm, reg_off) << scale); if (mtedesc) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, vd, reg_off, addr, retaddr); =20 @@ -5773,7 +5773,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, } =20 if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } } i +=3D 1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3af00ae90ef..a68d5dd5d13 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -276,7 +276,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); - gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); + gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); tcg_temp_free_i32(tcg_desc); =20 return ret; @@ -310,7 +310,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); - gen_helper_mte_checkN(ret, cpu_env, tcg_desc, addr); + gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); tcg_temp_free_i32(tcg_desc); =20 return ret; --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779328; cv=none; d=zohomail.com; s=zohoarc; b=itRW2D+6WWiuEnTXOxA+EAIzFnJpCWeyhg7jpHMPfUyE2LhBOA+st8f0XhUZbIxwLihQo2gHLoBA0R+Hcy56K8vbqe3VdP8ic53b7K9Us9FtHhJ6d4tukRFmHZhueFCfkrcn1/fsNSM5fGlnS5rc3IaHoHdC4ahlrJ7IlVYDMe4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779328; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rtj3JyD1LQVW/DZxj158TPK3xXuViQZ2hQy3eH6UaFU=; b=Nzd6Hj8q7c67MfrXh/L39B5in9WJ0Wit0JVux7pc1jvMsXx2KnGOhEtsuwLWLQxzGL h2CtQKLdMCJx98V7pC3KKIsYZqS0mvgaAJ8Ecg9mZ0SH7AXAFShF0Iap8F/Z1glDh+wJ mddZGIGJPHLuv3EDKZeV7QmaVuQWb+ZFWKJqY3oyKXpVSg78M3VF+iG0JkipMZZz94+d z4yxF1j0MPRygXfE8kbPrMsmAJTOjn99hTsbC7sAlUbEWDF8mjICrXqHaJkpEMd3glEo 5hbAE4NDUj1LNRJQwIrw6+T1M1pqkbioPLr1nWmHDXojOamGY6rvRvEymFOiUe2nwNKz xjgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rtj3JyD1LQVW/DZxj158TPK3xXuViQZ2hQy3eH6UaFU=; b=EXUjqvcsGE9UEUmgfZHoukYp7vobXcWBdM1Jl6ENYL/Z3O6MST9JLZMr1OY8reDHBH n+AOH0UhRZSRWUZEYkj9/nvPUwDoDPnCDLlLW+CE0m14xRAbdbApkoGlpqmXCnQOkDES /lKeMWD8lA4nJiuzE2tjhiiBEiYPXd/07zHWX2CeZaxsf/YSO++Ik/pMZWwj3NbAhONc rg0CUvwZUr9A5eZPCqYK7odQWiSnJCGMleLJS7lqRqEhTNbbyJR8Zze4AszlHMCNi7zH 2djWhw1WtH5QLyyXiFccIHBvw/g/27H4YDFvegV8jSTi6SEE44hBW5qPZxhUMPmyUpMF 2qpw== X-Gm-Message-State: AOAM531yV4tdqDKYWtsmBCI/1l4qZxfyeOsOrSPb6LQDwTyPK4JNK7fv T7OOp2EH7AkSqSd9cRQFJB9L/2Zht21jJTEb X-Google-Smtp-Source: ABdhPJxgmZYzYEbqyFX1abZ3feO4b9gtGcSPfavByhqjEujDz/5KDGHouzYIKRxOTVzOujv6Z7RBgg== X-Received: by 2002:adf:d1c3:: with SMTP id b3mr5832215wrd.367.1619778886167; Fri, 30 Apr 2021 03:34:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe Date: Fri, 30 Apr 2021 11:34:03 +0100 Message-Id: <20210430103437.4140-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson For consistency with the mte_check1 + mte_checkN merge to mte_check, rename the probe function as well. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 +- target/arm/mte_helper.c | 6 +++--- target/arm/sve_helper.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index af1db2cd9c9..886db56b580 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1145,7 +1145,7 @@ FIELD(MTEDESC, TCMA, 6, 2) FIELD(MTEDESC, WRITE, 8, 1) FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ =20 -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); +bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra); =20 static inline int allocation_tag_from_addr(uint64_t ptr) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c91d561ce33..a6fccc6e69e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -121,7 +121,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, * exception for inaccessible pages, and resolves the virtual address * into the softmmu tlb. * - * When RA =3D=3D 0, this is for mte_probe1. The page is expected to = be + * When RA =3D=3D 0, this is for mte_probe. The page is expected to be * valid. Indicate to probe_access_flags no-fault, then assert that * we received a valid page. */ @@ -808,12 +808,12 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t= desc, uint64_t ptr) } =20 /* - * No-fault version of mte_check1, to be used by SVE for MemSingleNF. + * No-fault version of mte_check, to be used by SVE for MemSingleNF. * Returns false if the access is Checked and the check failed. This * is only intended to probe the tag -- the validity of the page must * be checked beforehand. */ -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) +bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr) { uint64_t fault; int ret =3D mte_probe_int(env, desc, ptr, 0, &fault); diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index b63ddfc7f91..982240d1045 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4869,7 +4869,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, /* Watchpoint hit, see below. */ goto do_fault; } - if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { + if (mtedesc && !mte_probe(env, mtedesc, addr + mem_off)) { goto do_fault; } /* @@ -4919,7 +4919,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, & BP_MEM_READ)) { goto do_fault; } - if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { + if (mtedesc && !mte_probe(env, mtedesc, addr + mem_off)) { goto do_fault; } host_fn(vd, reg_off, host + mem_off); @@ -5588,7 +5588,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, } if (mtedesc && arm_tlb_mte_tagged(&info.attrs) && - !mte_probe1(env, mtedesc, addr)) { + !mte_probe(env, mtedesc, addr)) { goto fault; } =20 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779337; cv=none; d=zohomail.com; s=zohoarc; b=SBeM4KUbtZokhc1gyVpo/OAl0ZvhyOvItfrOkLPHwUNqimpXxtAgevT5hGDXsq6YdAp/JtVrt3T+JpiiviUm8A58QdnxcsK9xFQSRiwIPHCNarAqYFiywtwgNyL1/htPbtkZ1H1mdCsn0D/hQYZ+oPLwNek1xO2xXAsSCTkaK60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779337; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mmfnH2S2yk1KeR+3dCAlnuQBKmBSrJWVyKjVPASMqZQ=; b=SQN4OzPQJbGHjWlI7iUC0Kq4qu9nnAAVelvfV0yqXBksTF+FXgF/nzZCAOrLHmEUITQDmAk/p66dHRXe9E/DYF5FcWZR2KRbGewVU5I38pq+k9SNt9H/fxdDTjOaVzGQjF/3OJjbHdz4ItJX5KfhRync+0ZqFhsq+bWdAZLLiEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779337705908.3396502611441; Fri, 30 Apr 2021 03:42:17 -0700 (PDT) Received: from localhost ([::1]:45382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQbA-0007kB-7V for importer@patchew.org; Fri, 30 Apr 2021 06:42:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33534) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTz-0007PQ-Jp for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:51 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:43891) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTw-0001EN-BH for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:51 -0400 Received: by mail-wr1-x431.google.com with SMTP id x7so69945866wrw.10 for ; Fri, 30 Apr 2021 03:34:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mmfnH2S2yk1KeR+3dCAlnuQBKmBSrJWVyKjVPASMqZQ=; b=zY8NR5V+KAR1PeSlut3vYl0wsnm9qe2HL2muNy6cwu2Zyw0ZmsAIf/dXQxYS/JpeIe VJMS8bFuu5O7+ptUUIxIkGnrkCJ2IDfeoqhZjO8KUH1dNwfCrf1l0N46v94YK1uqQ1Uj GcQT1+FoQs2INrt3xGG6WbjEqmQDCj4B39aonVG0R1z0jQtXo52F7pk2Xl71mt8cIH8C RgTKc8p0HOrMOsgc0ygUVDHLVbCiysyIGgm8k9a43Ah7lbSNC+VpvzvyeBHeq4VUEtvC cs6pROPaJPk74tzv4U1WfR1XofAOQxICYAWOSR63pa69VY0BdFqDlroiaYbwb57u/aCE SIrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mmfnH2S2yk1KeR+3dCAlnuQBKmBSrJWVyKjVPASMqZQ=; b=Gak6CRzPmvwORf/0ysZYjJZMnbIdOBht+HjzNhf8oqihgZuBsthYn0/cS0+4r9zK/k REAMpJDLjIhPQ1577aEpj19ikqZSgJgbzg6tcQt8uU+eYbwjmmbXJQZQAyBDO1Jdkxd0 iQLrMjshrMXrJOQPbDYs2XfRH4x9/reAzIafabb68n+ikYTVOW91lsdctpj47y//NnWE 78oGzI02cHqJJ3kMlq709Whw/eCETi9T4lB7/rsFGl2sFmlWsBfcZ3yIhUA76+thZBPY XZlK8fkroR3e0gBQzEEZv8OemkgXJkepIucvj5bwO4ElkEiuSpBgBXkjPDAz24ObAdvw aVBg== X-Gm-Message-State: AOAM530kTforWNvnliTiqiDRPMlhGCqPQbr10I642pTiZGN93XM/RJV6 uswX7jsl+K+BuPbqypHZ9Uq3HgGkjJIaznfp X-Google-Smtp-Source: ABdhPJxoCepawdKD9ayftII7KF5nWGACL6RlLxmE/yXBTPVxK5yY2SGH7bzfaqj93Oeum1iL8c9M1Q== X-Received: by 2002:a5d:5110:: with SMTP id s16mr5861892wrt.337.1619778886925; Fri, 30 Apr 2021 03:34:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/43] target/arm: Simplify sve mte checking Date: Fri, 30 Apr 2021 11:34:04 +0100 Message-Id: <20210430103437.4140-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Now that mte_check1 and mte_checkN have been merged, we can merge sve_cont_ldst_mte_check1 and sve_cont_ldst_mte_checkN. Which means that we can eliminate the function pointer into sve_ldN_r and sve_stN_r, calling sve_cont_ldst_mte_check directly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve_helper.c | 84 +++++++++++++---------------------------- 1 file changed, 26 insertions(+), 58 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 982240d1045..c068dfa0d57 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4382,13 +4382,9 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *i= nfo, CPUARMState *env, #endif } =20 -typedef uint64_t mte_check_fn(CPUARMState *, uint32_t, uint64_t, uintptr_t= ); - -static inline QEMU_ALWAYS_INLINE -void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, int esiz= e, - int msize, uint32_t mtedesc, uintptr_t ra, - mte_check_fn *check) +static void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, int e= size, + int msize, uint32_t mtedesc, uintptr_t= ra) { intptr_t mem_off, reg_off, reg_last; =20 @@ -4405,7 +4401,7 @@ void sve_cont_ldst_mte_check_int(SVEContLdSt *info, C= PUARMState *env, uint64_t pg =3D vg[reg_off >> 6]; do { if ((pg >> (reg_off & 63)) & 1) { - check(env, mtedesc, addr, ra); + mte_check(env, mtedesc, addr, ra); } reg_off +=3D esize; mem_off +=3D msize; @@ -4422,7 +4418,7 @@ void sve_cont_ldst_mte_check_int(SVEContLdSt *info, C= PUARMState *env, uint64_t pg =3D vg[reg_off >> 6]; do { if ((pg >> (reg_off & 63)) & 1) { - check(env, mtedesc, addr, ra); + mte_check(env, mtedesc, addr, ra); } reg_off +=3D esize; mem_off +=3D msize; @@ -4431,30 +4427,6 @@ void sve_cont_ldst_mte_check_int(SVEContLdSt *info, = CPUARMState *env, } } =20 -typedef void sve_cont_ldst_mte_check_fn(SVEContLdSt *info, CPUARMState *en= v, - uint64_t *vg, target_ulong addr, - int esize, int msize, uint32_t mte= desc, - uintptr_t ra); - -static void sve_cont_ldst_mte_check1(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, uint32_t mtedes= c, - uintptr_t ra) -{ - sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_check); -} - -static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, uint32_t mtedes= c, - uintptr_t ra) -{ - sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_check); -} - - /* * Common helper for all contiguous 1,2,3,4-register predicated stores. */ @@ -4463,8 +4435,7 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const = target_ulong addr, uint32_t desc, const uintptr_t retaddr, const int esz, const int msz, const int N, uint32_t mtedesc, sve_ldst1_host_fn *host_fn, - sve_ldst1_tlb_fn *tlb_fn, - sve_cont_ldst_mte_check_fn *mte_check_fn) + sve_ldst1_tlb_fn *tlb_fn) { const unsigned rd =3D simd_data(desc); const intptr_t reg_max =3D simd_oprsz(desc); @@ -4493,9 +4464,9 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const = target_ulong addr, * Handle mte checks for all active elements. * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. */ - if (mte_check_fn && mtedesc) { - mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, - mtedesc, retaddr); + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); } =20 flags =3D info.page[0].flags | info.page[1].flags; @@ -4621,8 +4592,7 @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, ta= rget_ulong addr, mtedesc =3D 0; } =20 - sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn, - N =3D=3D 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_ch= eckN); + sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn); } =20 #define DO_LD1_1(NAME, ESZ) \ @@ -4630,7 +4600,7 @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *v= g, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, 0, \ - sve_##NAME##_host, sve_##NAME##_tlb, NULL); \ + sve_##NAME##_host, sve_##NAME##_tlb); \ } \ void HELPER(sve_##NAME##_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -4644,22 +4614,22 @@ void HELPER(sve_##NAME##_le_r)(CPUARMState *env, vo= id *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ - sve_##NAME##_le_host, sve_##NAME##_le_tlb, NULL); \ + sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ } \ void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ - sve_##NAME##_be_host, sve_##NAME##_be_tlb, NULL); \ + sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ } \ void HELPER(sve_##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ + target_ulong addr, uint32_t desc) \ { \ sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ } \ void HELPER(sve_##NAME##_be_r_mte)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ + target_ulong addr, uint32_t desc) \ { \ sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ @@ -4693,7 +4663,7 @@ void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *= vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, 0, \ - sve_ld1bb_host, sve_ld1bb_tlb, NULL); \ + sve_ld1bb_host, sve_ld1bb_tlb); \ } \ void HELPER(sve_ld##N##bb_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -4707,13 +4677,13 @@ void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *en= v, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ - sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb, NULL); \ + sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \ } \ void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ - sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb, NULL); \ + sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \ } \ void HELPER(sve_ld##N##SUFF##_le_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -5090,8 +5060,7 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target= _ulong addr, uint32_t desc, const uintptr_t retaddr, const int esz, const int msz, const int N, uint32_t mtedesc, sve_ldst1_host_fn *host_fn, - sve_ldst1_tlb_fn *tlb_fn, - sve_cont_ldst_mte_check_fn *mte_check_fn) + sve_ldst1_tlb_fn *tlb_fn) { const unsigned rd =3D simd_data(desc); const intptr_t reg_max =3D simd_oprsz(desc); @@ -5117,9 +5086,9 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target= _ulong addr, * Handle mte checks for all active elements. * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. */ - if (mte_check_fn && mtedesc) { - mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, - mtedesc, retaddr); + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); } =20 flags =3D info.page[0].flags | info.page[1].flags; @@ -5233,8 +5202,7 @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, ta= rget_ulong addr, mtedesc =3D 0; } =20 - sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn, - N =3D=3D 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_ch= eckN); + sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_= fn); } =20 #define DO_STN_1(N, NAME, ESZ) \ @@ -5242,7 +5210,7 @@ void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, vo= id *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, 0, \ - sve_st1##NAME##_host, sve_st1##NAME##_tlb, NULL); \ + sve_st1##NAME##_host, sve_st1##NAME##_tlb); \ } \ void HELPER(sve_st##N##NAME##_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -5256,13 +5224,13 @@ void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *en= v, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ - sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb, NULL); \ + sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \ } \ void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ - sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb, NULL); \ + sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \ } \ void HELPER(sve_st##N##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779520; cv=none; d=zohomail.com; s=zohoarc; b=HTS7q+FZsKton9j25PqD7HE/PM6Y8rw2qeUJbUIaJAm5CaMnhYdO4J+3Rztp+Dl7nCLEBmo/a6jPhaZv+Tv0OGKqvWEALzRHL7f/9EixjCZg1zq0ZmYJwudbqwjRXff2sFivOWeZPyI14H/raFLw449herpaikwNwZ7dZMSEBHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779520; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nLzZ4/18hku2V8u9s3HUEscNlgpZzXbguvwT6XkaP6Y=; b=KZItodnOYb/hQbJDRQOegzCTGMBtg/vdWiKBNtDcvI3jImXOr7umuJjx6Qz+gQmF07gxnbaz8WryAesdcoBz5DpPZ8RB3xUQWPn0SsCmDrEle6eTbNHDBkO8EoPHyNYMNAYVoRIDXo2DtTyi3KwkhtDA0WqsuoJkJNlQgdG6Pp0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779520962512.0551859558036; Fri, 30 Apr 2021 03:45:20 -0700 (PDT) Received: from localhost ([::1]:53688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQe7-0002m0-S1 for importer@patchew.org; Fri, 30 Apr 2021 06:45:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQTz-0007Oo-Ad for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:51 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:33462) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTx-0001F4-8n for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:50 -0400 Received: by mail-wr1-x429.google.com with SMTP id n2so16824754wrm.0 for ; Fri, 30 Apr 2021 03:34:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nLzZ4/18hku2V8u9s3HUEscNlgpZzXbguvwT6XkaP6Y=; b=sHjTRKFfEL26xKQcn79qXGGKJbEOJnFKEX2dvXv5bkd7L9s42nRIWMGsSdm0FR04Su kwBWtbdfwFn4ui9yMLaliJpwKWEW/0qT7vSE0bLb6vtivbALpOJKwhQFAUVUiloFn5gn lXcB3D2oWkq//jSBbTjPdLY6GVwtTbkJ399ZhnKl2kMwbAC1ToHcGFqC0+K16eum1grS nw9fSn2izniORUyJ92mqLUsJgXXqx9GU8tiiGKHXLifn4I/W1TMe7ZGC5HJIeFmK8BMe h2/OFFBCNOgdYqs5hrQGiXYgaN7DTcGr/SOjXNEwMpL2zZx+X4ASNodqCzViGHgzc6aB w33w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nLzZ4/18hku2V8u9s3HUEscNlgpZzXbguvwT6XkaP6Y=; b=qnaxJBl2Y5mxvGVZcKsoc47PlWfJKTzZwWoTY2JGVttstLyrMLIVVIDcV8reWTTFhm LdSm5W8ybPZ7dfnS4pqUheNUYwOj3XLLuTTDhwhqhwJ58rJVl8RFIfuoCmLrkk+kjUja lE12y9eF3Ure7nzcHKSciECkvY9OhNpHkv7EwTVEx00eh7ZdNfvctDQH+y3mO7CktRTK x4ZzU+mUGzf+rbAcXf2Vu+UZL4qbRD23411KAbVp15aPN4Sezem/c9mWFv/QFVimQMaa nonS/VYrPkGDfMyvLPiCqVnQIY/6fVGkF+XbQl0WR42wgeSZL+Fig9GKlI9sKQXV6wup 3wsg== X-Gm-Message-State: AOAM530zpTAJQVH5fVzzqMYxZEObfixqULcMLUM1kTuGvlXiE+sSlLsU EQ1G6amz31SHzDx4nMcYi+YL5gE0B1HwGOCW X-Google-Smtp-Source: ABdhPJy+80eaxdzX0DwVWWyk8fkOR+rC2JG8FJ0fmZoTRH9Vux80KXR7mkDGA3t1MhZF5s+IxOxW1A== X-Received: by 2002:a05:6000:1ac5:: with SMTP id i5mr5849911wry.412.1619778887658; Fri, 30 Apr 2021 03:34:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN Date: Fri, 30 Apr 2021 11:34:05 +0100 Message-Id: <20210430103437.4140-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The log2_esize parameter is not used except trivially. Drop the parameter and the deferral to gen_mte_check1. This fixes a bug in that the parameters as documented in the header file were the reverse from those in the implementation. Which meant that translate-sve.c was passing the parameters in the wrong order. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20210416183106.1516563-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.h | 2 +- target/arm/translate-a64.c | 15 +++++++-------- target/arm/translate-sve.c | 4 ++-- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 3668b671ddb..868d3550486 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -44,7 +44,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int count, int log2_esize); + bool tag_checked, int size); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a68d5dd5d13..f35a5e81746 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -295,9 +295,9 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr,= bool is_write, * For MTE, check multiple logical sequential accesses. */ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int log2_esize, int total_size) + bool tag_checked, int size) { - if (tag_checked && s->mte_active[0] && total_size !=3D (1 << log2_esiz= e)) { + if (tag_checked && s->mte_active[0]) { TCGv_i32 tcg_desc; TCGv_i64 ret; int desc =3D 0; @@ -306,7 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); @@ -315,7 +315,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, =20 return ret; } - return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); + return clean_data_tbi(s, addr); } =20 typedef struct DisasCompare64 { @@ -2965,8 +2965,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) } =20 clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn !=3D 31) && !set_tag, - size, 2 << size); + (wback || rn !=3D 31) && !set_tag, 2 << si= ze); =20 if (is_vector) { if (is_load) { @@ -3713,7 +3712,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) * promote consecutive little-endian elements below. */ clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - size, total); + total); =20 /* * Consecutive little-endian elements from a single register @@ -3866,7 +3865,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) tcg_rn =3D cpu_reg_sp(s, rn); =20 clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, - scale, total); + total); =20 tcg_ebytes =3D tcg_const_i64(1 << scale); for (xs =3D 0; xs < selem; xs++) { diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5179c1f8363..584c4d047c8 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4264,7 +4264,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); tcg_temp_free_i64(dirty_addr); =20 /* @@ -4352,7 +4352,7 @@ static void do_str(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); tcg_temp_free_i64(dirty_addr); =20 /* Note that unpredicated load/store of vector/predicate registers --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779558; cv=none; d=zohomail.com; s=zohoarc; b=IdeOQwggi2AbMyu2CJ5FleZkX+sj8sofv28yZwaP/9bP23241UGv5Tdi3UxCa+llQ07rmxk8wvYdz0MR1wztoLEx98Hnjvo79Kt31oWwhCKGyevcA6wri/C4g3Uxq+q7CHWguu7KCBpQCz8cXUDukvty2JMucQplqYTjjn6yTFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779558; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QwgC2LRCCGx4j46qUDfFTi9+GYO+7HwI5AJVYUxUdkI=; b=Kb1tfQgUJkmafQdaNRy2ziTzPQPv9kf1oQj+kJqpBHLNrKfnh0mfdOkgRRP6AkFCMB fOF8lH+63LpLmYh30P9TD3o70eW0Etwe9dybEL2tMk3+/tNzsc0zsU9aiaZxE6QD6FoB O8uB0Zs0OvtYldkCOel1POaWSA5oDXkMeMjhYSFRnyCF5ghqkOScf+NOm5eY5a/w3cls UvSjKjD4wpsoXAg3zlpDslLy/lBZehFZRzo3Y6xXlx2FlvVxpGfV5SzA4jP8lU/ZY/KO yw0YvpZMPDFPyYjt+VAMxY0xP0wDtM48BFORamBzigFIMRR8meGlUxyy4sBagvMPhKuK ea8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QwgC2LRCCGx4j46qUDfFTi9+GYO+7HwI5AJVYUxUdkI=; b=s/LsmhWz6FNVD/b6fQ8xEBdaE01KBQi5qEdLjM3aFCv5C2aWgYKWKLueFrpvnfThTa mRaPYAesy/+agO70dyUWPuv9yKYMFFYYQXBWv/RNamNN/Z9Vgtx8sOyk+yqO8iLO03Oi 0zxHMY5FM5Ub9YXcOuUb9lYhCosPGMAtsX9qP+0kDXNrbktyBxluGYMB6Dweea0nun/N FC5WJcjscqwLzRT2h1etNO010PgwNW7mxrx5hx0tBAOoUGszYJFaZzqUyEV4Ej+4uWXu 9YoJEKtgZktR8NWdGdc9YxvcIvOxWGEBFZXxI42aAgDqFn3+RRVeO5UZXL7XVmZpg6sb bYnQ== X-Gm-Message-State: AOAM530MtCL00Gw0xshdf4cP2jni0uR8X3Pmq062CjIROAlb/gqk/v9a Ags/BdANN5BpcjJ9ng1CmJIGdnq08plhd9Ix X-Google-Smtp-Source: ABdhPJzQ0s+5TyAnSAbj5BoYJKbY7e8eRIWhdSpcib0RF53jUxTXxJim2z6G0hnD7EdCbw9g/SjtHQ== X-Received: by 2002:adf:dd52:: with SMTP id u18mr5880160wrm.32.1619778888675; Fri, 30 Apr 2021 03:34:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/43] target/arm: Fix decode of align in VLDST_single Date: Fri, 30 Apr 2021 11:34:06 +0100 Message-Id: <20210430103437.4140-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The encoding of size =3D 2 and size =3D 3 had the incorrect decode for align, overlapping the stride field. This error was hidden by what should have been unnecessary masking in translate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/neon-ls.decode | 4 ++-- target/arm/translate-neon.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode index c17f5019e31..0a2a0e15db5 100644 --- a/target/arm/neon-ls.decode +++ b/target/arm/neon-ls.decode @@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 = t:1 a:1 rm:4 \ =20 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4= \ vd=3D%vd_dp size=3D0 stride=3D1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4= \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm= :4 \ vd=3D%vd_dp size=3D1 stride=3D%imm1_5_p1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4= \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm= :4 \ vd=3D%vd_dp size=3D2 stride=3D%imm1_6_p1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index f6c68e30ab2..0e5828744bb 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -606,7 +606,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) switch (nregs) { case 1: if (((a->align & (1 << a->size)) !=3D 0) || - (a->size =3D=3D 2 && ((a->align & 3) =3D=3D 1 || (a->align & 3= ) =3D=3D 2))) { + (a->size =3D=3D 2 && (a->align =3D=3D 1 || a->align =3D=3D 2))= ) { return false; } break; @@ -621,7 +621,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) } break; case 4: - if ((a->size =3D=3D 2) && ((a->align & 3) =3D=3D 3)) { + if (a->size =3D=3D 2 && a->align =3D=3D 3) { return false; } break; --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779674; cv=none; d=zohomail.com; s=zohoarc; b=WrDyswHUDKptG3iqGJKyPfn3pKXAe+s76ZhtzXVG7/i0cubyY72S5H/ZhJwi1XQgQsRMGG6iqLFtAFZHAY92f8GrFBu5cNwGMA/KI5n0+44t4rvpNIjgcr9TgZvV4cVbV3XhrYsJeIY0+/vOHXvU7RO339V2kXG7x/Ta0en6G3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779674; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tx1KqMlpbKJTay1wgKZV7vrwjIu05gATaQsruPdTpKU=; b=UAkdB8oTAhldwsd3YCEvr5oi6BoK5WL95zBsPaR60QYON1f35mNjdO9bSoQKfz/ygkiTGvtr1ZWRpUdkgiEWhQf74II8eIN+pqRVW4BahxSI6zURMI1vxB33LbA2WJU+puqRoLo+PkpZZMq409PpBDoDqIofKJ/VzYQ6AEW+c0A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779674034160.52757945945018; Fri, 30 Apr 2021 03:47:54 -0700 (PDT) Received: from localhost ([::1]:34214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQga-0006O7-Mp for importer@patchew.org; Fri, 30 Apr 2021 06:47:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU0-0007Sk-RR for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:52 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTy-0001Ft-Rp for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:52 -0400 Received: by mail-wr1-x42a.google.com with SMTP id l14so149432wrx.5 for ; Fri, 30 Apr 2021 03:34:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tx1KqMlpbKJTay1wgKZV7vrwjIu05gATaQsruPdTpKU=; b=ytOfALO7bTb1dIgPzN/4c2Ip9xrHcXM/GdG3wLGP/sGje3ZriX1xrLPZUWmLf3PTbp XATL3BxPhQ2ovusxNoed7X+uSUnppmQJ8kQ0I5gmqhy9QgEohGGNl0IB10COUeGnygUg 3c34W+JJoJXz9h7X2gCYYmsFzsZ9dXKnkdkBmawwk5yjteN51hnhQW8F2zs9KGk21cjW S7bxjDZiScMuoifD3WGf8/gvP4r4B5hatAAgtUshGIhAU0sZIx7UK0J77QIGEj7f0H/2 +3mqYCVbWJPAl0SVEySA9WBKQJoCOXT80W00Z7gs5p6Bv9eTDSwNz5fdpIZke0COBx0A Ggjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tx1KqMlpbKJTay1wgKZV7vrwjIu05gATaQsruPdTpKU=; b=Ey3BcEoMDF3Sg8t/i6TADqmdOcoUkGmbBsU8eXMyoqefNUUu/5LBfVKgd3khzqDLRV Vfh3s9XnODWC/QEuLZ6Z9WHKobYXQW8v2/bvmWztuyH11hozA+bCt4JLBl5Z3XSG+Iei XMoo3EF+fH+dhHtQdI+OCv39+VYRsEFeHTzempRIZQ0ZkJ7yKaBQWQ412Q+6HLLEAwl/ Imy9N39d3EtnKb4FRgD/aWFmvFJCtjBNslh4v/IMmYxrvvDESTzk6g+EC/deYhw58TD4 65TCmhT6NVyAgarugRhXnn0BDvMEwfwTmuJIj4tvFsP/XZgu42IvFYN7nXj7gOB36r0f c0yw== X-Gm-Message-State: AOAM530oHGAoU6Qq19a4tfoq4aD9CKQJ+oii0yLhqzyxU6IZbkLy76Sm K3tRnLGV9vvu/njxLpJ9969zpHDltP4F67fV X-Google-Smtp-Source: ABdhPJy86vJrf0besTl0gXob4SQIcgTtqCHbmDZ8iSEZoaNtWLwXqjb6rlNjpUG03ytTLEZeRqEs4w== X-Received: by 2002:a5d:4707:: with SMTP id y7mr5967933wrq.137.1619778889387; Fri, 30 Apr 2021 03:34:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B Date: Fri, 30 Apr 2021 11:34:07 +0100 Message-Id: <20210430103437.4140-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We're about to rearrange the macro expansion surrounding tbflags, and this field name will be expanded using the bit definition of the same name, resulting in a token pasting error. So SCTLR_B -> SCTLR__B in the 3 uses, and document it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- target/arm/helper.c | 2 +- target/arm/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fa..304e0a6af30 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3423,7 +3423,7 @@ FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached= . */ */ FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. = */ -FIELD(TBFLAG_A32, SCTLR_B, 15, 1) +FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) /* * Indicates whether cp register reads and writes by guest code should acc= ess diff --git a/target/arm/helper.c b/target/arm/helper.c index d9220be7c5a..556b9d4f0ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13003,7 +13003,7 @@ static uint32_t rebuild_hflags_common_32(CPUARMStat= e *env, int fp_el, bool sctlr_b =3D arm_sctlr_b(env); =20 if (sctlr_b) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1); } if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); diff --git a/target/arm/translate.c b/target/arm/translate.c index 68809e08f09..2de42529530 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8895,7 +8895,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); - dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B); dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779337; cv=none; d=zohomail.com; s=zohoarc; b=X9pGkS6LAXyLmnN8Zz55iwCd14PZStpxJCreUYQg/Qos4KpKgrvoqL1pMw8NJktSJf9SYWz7rXcac5pL169tBQmInYDK6jzxlP4DiDJAe3MEqrrtEB+WBynovq+lCdgPKwLRa6e+o3fyV8ttplLl7qaTOqPWOgzGMlCa4fPg1fo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779337; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i+MUZfR51udbEhU7g/6KNDdoa1+wGw6qynj0bMKCyjI=; b=hwDUiiC27D9w5ZFeuaQGcCpJdWkUkxDg7Pybu4Oxic7kEbBPJ+oVQ9yF0cnrcfISBg3ZDh9iR+Q5lEBKZ4JuJdXwhhrZ2Bj4UPNhqkEeBwUtZxzkCBj74g+iVWDHOoFCoMEG4+DmGZHTnSZB2PgQjsCRw+WaZpv8qvkstWeVYbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779337645108.78940500793124; Fri, 30 Apr 2021 03:42:17 -0700 (PDT) Received: from localhost ([::1]:45426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQbA-0007lM-CR for importer@patchew.org; Fri, 30 Apr 2021 06:42:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU1-0007UM-L0 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:53 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:43886) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQTz-0001GH-Mz for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:53 -0400 Received: by mail-wr1-x42b.google.com with SMTP id x7so69946007wrw.10 for ; Fri, 30 Apr 2021 03:34:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=i+MUZfR51udbEhU7g/6KNDdoa1+wGw6qynj0bMKCyjI=; b=wnirDwXZcGjcjnQP+6SjhgbAhHoA8Yl+0ofZMOewMnFw7uzLpnK/3r1AZUWnajTAji Mj3RqEbwtMet/rn2JCQDU8eR7EdBcAl23Hu6YqbNXL2dd32DwngGdK+Br1NnMfDtkvNI mynZgb8yH/DQxQwGkVQ02VsWSfkhCEi4JUWO96pgAltk5YnXjbsXcJdKZ1+c1zynyUbM vwbGigWPcFR9yWvqc3LLOsgIgCU7R7w3LzCxehQ1anG8LZKpGllMmU+8SDjaybzlx1qj wNLL2iaSUSaIme7YVtVuhIDYgEAgwzfg+BKos/JFy8deU0pz/frm/g263EzKXk8M6ui6 Cbkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i+MUZfR51udbEhU7g/6KNDdoa1+wGw6qynj0bMKCyjI=; b=NvjHSAZdj8dUg+F2B1PWJeRiR1fR6vn+uLNmveYfQcuXV1zDWBQI9iO0XO+8gPaj8Z eHze1XaLuMVOqV31FSFHwB4m0xzrFpjI1PspF4Nm6C7VF8h1cC1MvMj1ane/t8aOEWu/ Fjh14cBQ0R48lkuckyj7geAo9oGlkrXPVoNsdEFmo7tg3L6WAwaCjsw6WMmOYdO1Telx G0DDYBkL5+MwhNcNhVIcZNlr/0G7HeNC2hLjvUN+Z7MdUufe1iszjSHtZZF3ND8/cNps bLiEfeLtqP3xROVqVn8sPBBxhwRdLGSA9De/IGMMRxa0Ic206bRXf5f61k1YXSiB1Plc h8nQ== X-Gm-Message-State: AOAM531IpELb1ntA3zKwOQipWaPSeyixHDdH0NYik+u9pp1cecgDGwb+ 97A6+BnKvxXEwaMb1+UwhlX3lBuDSV/cSHLT X-Google-Smtp-Source: ABdhPJycpBfjftMLb2d7Tk2Yckr6IrgrA4YYvUB/LoYzLBem/Hq5hqVBZaUlcvDycEk2hIDGA6qmfQ== X-Received: by 2002:a5d:47cb:: with SMTP id o11mr5749070wrc.378.1619778890071; Fri, 30 Apr 2021 03:34:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS Date: Fri, 30 Apr 2021 11:34:08 +0100 Message-Id: <20210430103437.4140-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We're about to rearrange the macro expansion surrounding tbflags, and this field name will be expanded using the bit definition of the same name, resulting in a token pasting error. So PSTATE_SS -> PSTATE__SS in the uses, and document it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 304e0a6af30..4cbf2db3e34 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3396,7 +3396,7 @@ typedef ARMCPU ArchCPU; */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */ FIELD(TBFLAG_ANY, BE_DATA, 28, 1) FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 556b9d4f0ae..cd8dec126fa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13333,11 +13333,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending - * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. + * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. */ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); + flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1); } =20 *pflags =3D flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f35a5e81746..64b3a5200c2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14733,7 +14733,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, * end the TB */ dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); + dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); dc->is_ldex =3D false; dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_= EL); =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 2de42529530..271c53dadbc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8925,7 +8925,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) * end the TB */ dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); + dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); dc->is_ldex =3D false; =20 dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779526; cv=none; d=zohomail.com; s=zohoarc; b=YELRJlRj9SzARnPc1dBOSPQYUxtnrE+aA7NNnSSS1KjE8qUiDgkF7n6u9/95x8lhLO9SPwIKfJhnRt8zVj7uLLzoj4wNueOKs42QrTU9LN//bZxpi7jseA8J9USDWWrz5oAgIHDqMgJiDy0ULTbX2T0pBhyp//Iq8lAowUqdqsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779526; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oxXBIhODnR9/QyXIS4N/dsHxayOk2olKmeaxF6on8gw=; b=EIfvUiP4ALZElQ3yfxK74H7Bo7pIeDHvchTtbzlk8b+4AAWYNyuKFQo1is0RUDk1uQ DYXsXUf5gDnGzRR3RzX3cbEP7rrgxb85pw0Afq0wrnihQIpBM0MOL9rsFkqKx3wqeCtc RS4OpEMRvO9WZ0TFF5xCM5lXx9+z75LT+4k7E0zQ1RuzBSXFQJfP2J2Cg/8cTXvVWH32 hRjLfoxIcEW/l1RHs741O53TS/KOzKIAH9uDbWAHZR+6XzAejSuZRLCqPx5wcz2STUTQ 3SW7UEmziBiS83Fou8OUjTqGLAAkPHPLn6EGbStEhLNOmQS/RETauH+vR9HSKnQm4auT GBcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oxXBIhODnR9/QyXIS4N/dsHxayOk2olKmeaxF6on8gw=; b=heMWJC+sQcrz56p0Vi+6agxAS9Ax19mgmzlUVQUDBcvHSjdRlcPUKt0ZV0JSYC6kCk 1fZUb/nlbNUV150Xri/DfrZeJylI216nGfwjUjAqaGYkbAlCBjwPJP7d9hhaNHeCrbFf vPwyD0RAqE6rqqgDiR7Y+g3I8DyE+jDSWjR+C4YG1dOukqUP3hJOCJznK+4M5Zf4sUfh f/aFVQgnUG2PMqFRUj5O2WpR/TE7xjUqcjCtjJ6pHs0nWKxvJ4Y7IDMEP9vswP9dRpFK p1mwhNv6wixMCm5t6JcbUhOQ40dtG4SF+orPchPUMURf2ngAEoWr510bcSIYEfh98Gmw ++Ag== X-Gm-Message-State: AOAM5303KSaCoErcGdY4QKEkwoRfoo9awDvWUYb6PbHw/WqIYGFKzLCJ ASq4LjZEhDNNUqoIAzZgGMoikvwIUQeBgU/+ X-Google-Smtp-Source: ABdhPJzBZVhcRZluXeShour9AisrRU3/7arXn+WxIn4c3Q8v2CMlw8tZMwonMq5qjS7K1UGIH5tNYw== X-Received: by 2002:a1c:4b0e:: with SMTP id y14mr2771571wma.108.1619778891004; Fri, 30 Apr 2021 03:34:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags Date: Fri, 30 Apr 2021 11:34:09 +0100 Message-Id: <20210430103437.4140-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We're about to split tbflags into two parts. These macros will ensure that the correct part is used with the correct set of bits. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 22 +++++++++- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 85 +++++++++++++++++--------------------- target/arm/translate-a64.c | 36 ++++++++-------- target/arm/translate.c | 48 ++++++++++----------- 5 files changed, 101 insertions(+), 92 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4cbf2db3e34..b798ff81150 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3462,6 +3462,26 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) =20 +/* + * Helpers for using the above. + */ +#define DP_TBFLAG_ANY(DST, WHICH, VAL) \ + (DST =3D FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) +#define DP_TBFLAG_A64(DST, WHICH, VAL) \ + (DST =3D FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) +#define DP_TBFLAG_A32(DST, WHICH, VAL) \ + (DST =3D FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) +#define DP_TBFLAG_M32(DST, WHICH, VAL) \ + (DST =3D FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) +#define DP_TBFLAG_AM32(DST, WHICH, VAL) \ + (DST =3D FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) + /** * cpu_mmu_index: * @env: The cpu environment @@ -3472,7 +3492,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) */ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) { - return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); + return EX_TBFLAG_ANY(env->hflags, MMUIDX); } =20 static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 061c8ff846c..9cc3b066e28 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1020,7 +1020,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) * the hflags rebuild, since we can pull the composite TBII field * from there. */ - tbii =3D FIELD_EX32(env->hflags, TBFLAG_A64, TBII); + tbii =3D EX_TBFLAG_A64(env->hflags, TBII); if ((tbii >> extract64(new_pc, 55, 1)) & 1) { /* TBI is enabled. */ int core_mmu_idx =3D cpu_mmu_index(env, false); diff --git a/target/arm/helper.c b/target/arm/helper.c index cd8dec126fa..2769e6fd355 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12987,12 +12987,11 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); - flags =3D FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, - arm_to_core_mmu_idx(mmu_idx)); + DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); + DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); =20 if (arm_singlestep_active(env)) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); } return flags; } @@ -13003,12 +13002,12 @@ static uint32_t rebuild_hflags_common_32(CPUARMSt= ate *env, int fp_el, bool sctlr_b =3D arm_sctlr_b(env); =20 if (sctlr_b) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1); + DP_TBFLAG_A32(flags, SCTLR__B, 1); } if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + DP_TBFLAG_ANY(flags, BE_DATA, 1); } - flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); =20 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } @@ -13019,7 +13018,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env= , int fp_el, uint32_t flags =3D 0; =20 if (arm_v7m_is_handler_mode(env)) { - flags =3D FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); + DP_TBFLAG_M32(flags, HANDLER, 1); } =20 /* @@ -13030,7 +13029,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env= , int fp_el, if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags =3D FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); + DP_TBFLAG_M32(flags, STACKCHECK, 1); } =20 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -13040,8 +13039,7 @@ static uint32_t rebuild_hflags_aprofile(CPUARMState= *env) { int flags =3D 0; =20 - flags =3D FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, - arm_debug_target_el(env)); + DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } =20 @@ -13051,12 +13049,12 @@ static uint32_t rebuild_hflags_a32(CPUARMState *e= nv, int fp_el, uint32_t flags =3D rebuild_hflags_aprofile(env); =20 if (arm_el_is_aa64(env, 1)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + DP_TBFLAG_A32(flags, VFPEN, 1); } =20 if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1); + DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } =20 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -13071,14 +13069,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, uint64_t sctlr; int tbii, tbid; =20 - flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); =20 /* Get control bits for tagged addresses. */ tbid =3D aa64_va_parameter_tbi(tcr, mmu_idx); tbii =3D tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); =20 - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + DP_TBFLAG_A64(flags, TBII, tbii); + DP_TBFLAG_A64(flags, TBID, tbid); =20 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el =3D sve_exception_el(env, el); @@ -13093,14 +13091,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, } else { zcr_len =3D sve_zcr_len_for_el(env, el); } - flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); + DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); } =20 sctlr =3D regime_sctlr(env, stage1); =20 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + DP_TBFLAG_ANY(flags, BE_DATA, 1); } =20 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { @@ -13111,14 +13109,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, * The decision of which action to take is left to a helper. */ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); } } =20 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ if (sctlr & (el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); + DP_TBFLAG_A64(flags, BT, 1); } } =20 @@ -13130,7 +13128,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: @@ -13141,7 +13139,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, * gated by HCR_EL2. =3D=3D '11', and so is LDTR. */ if (env->cp15.hcr_el2 & HCR_TGE) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + DP_TBFLAG_A64(flags, UNPRIV, 1); } break; default: @@ -13159,24 +13157,23 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, * 4) If no Allocation Tag Access, then all accesses are Unchecked. */ if (allocation_tag_access_enabled(env, el, sctlr)) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, ATA, 1); + DP_TBFLAG_A64(flags, ATA, 1); if (tbid && !(env->pstate & PSTATE_TCO) && (sctlr & (el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); } } /* And again for unprivileged accesses, if required. */ - if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) + if (EX_TBFLAG_A64(flags, UNPRIV) && tbid && !(env->pstate & PSTATE_TCO) && (sctlr & SCTLR_TCF0) && allocation_tag_access_enabled(env, 0, sctlr)) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); + DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); } /* Cache TCMA as well as TBI. */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, TCMA, - aa64_va_parameter_tcma(tcr, mmu_idx)); + DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); } =20 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -13272,10 +13269,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, *cs_base =3D 0; assert_hflags_rebuild_correctly(env); =20 - if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc =3D env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { *pc =3D env->regs[15]; @@ -13284,7 +13281,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.secure) { - flags =3D FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); + DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); } =20 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && @@ -13296,12 +13293,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * active FP context; we must create a new FP context befo= re * executing any FP insn. */ - flags =3D FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED= , 1); + DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); } =20 bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags =3D FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); + DP_TBFLAG_M32(flags, LSPACT, 1); } } else { /* @@ -13309,21 +13306,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * Note that VECLEN+VECSTRIDE are RES0 for M-profile. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); + DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); } else { - flags =3D FIELD_DP32(flags, TBFLAG_A32, VECLEN, - env->vfp.vec_len); - flags =3D FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, - env->vfp.vec_stride); + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + DP_TBFLAG_A32(flags, VFPEN, 1); } } =20 - flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); - flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b= its); + DP_TBFLAG_AM32(flags, THUMB, env->thumb); + DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); } =20 /* @@ -13335,9 +13329,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && - (env->pstate & PSTATE_SS)) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1); + if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { + DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 *pflags =3D flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 64b3a5200c2..05d83a5f7a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14684,28 +14684,28 @@ static void aarch64_tr_init_disas_context(DisasCo= ntextBase *dcbase, !arm_el_is_aa64(env, 3); dc->thumb =3D 0; dc->sctlr_b =3D 0; - dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; + dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; dc->condexec_mask =3D 0; dc->condexec_cond =3D 0; - core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + core_mmu_idx =3D EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx =3D core_to_aa64_mmu_idx(core_mmu_idx); - dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); - dc->tbid =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBID); - dc->tcma =3D FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); + dc->tbii =3D EX_TBFLAG_A64(tb_flags, TBII); + dc->tbid =3D EX_TBFLAG_A64(tb_flags, TBID); + dc->tcma =3D EX_TBFLAG_A64(tb_flags, TCMA); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); - dc->sve_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); - dc->sve_len =3D (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; - dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); - dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); - dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); - dc->unpriv =3D FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); - dc->ata =3D FIELD_EX32(tb_flags, TBFLAG_A64, ATA); - dc->mte_active[0] =3D FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); - dc->mte_active[1] =3D FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); + dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); + dc->sve_len =3D (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; + dc->pauth_active =3D EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); + dc->bt =3D EX_TBFLAG_A64(tb_flags, BT); + dc->btype =3D EX_TBFLAG_A64(tb_flags, BTYPE); + dc->unpriv =3D EX_TBFLAG_A64(tb_flags, UNPRIV); + dc->ata =3D EX_TBFLAG_A64(tb_flags, ATA); + dc->mte_active[0] =3D EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); + dc->mte_active[1] =3D EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; @@ -14732,10 +14732,10 @@ static void aarch64_tr_init_disas_context(DisasCo= ntextBase *dcbase, * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); + dc->ss_active =3D EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); + dc->pstate_ss =3D EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex =3D false; - dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_= EL); + dc->debug_target_el =3D EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); =20 /* Bound the number of insns to execute to those left on the page. */ bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 271c53dadbc..5c21e98d243 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8864,46 +8864,42 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB); - dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; - condexec =3D FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC); + dc->thumb =3D EX_TBFLAG_AM32(tb_flags, THUMB); + dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; + condexec =3D EX_TBFLAG_AM32(tb_flags, CONDEXEC); dc->condexec_mask =3D (condexec & 0xf) << 1; dc->condexec_cond =3D condexec >> 4; =20 - core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + core_mmu_idx =3D EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; dc->be_data =3D MO_TE; - dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER); + dc->v7m_handler_mode =3D EX_TBFLAG_M32(tb_flags, HANDLER); dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK= ); - dc->v8m_fpccr_s_wrong =3D - FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG); + dc->v8m_stackcheck =3D EX_TBFLAG_M32(tb_flags, STACKCHECK); + dc->v8m_fpccr_s_wrong =3D EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed =3D - FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED); - dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT); + EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact =3D EX_TBFLAG_M32(tb_flags, LSPACT); } else { - dc->be_data =3D - FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; - dc->debug_target_el =3D - FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); - dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B); - dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); - dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); - dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + dc->debug_target_el =3D EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); + dc->sctlr_b =3D EX_TBFLAG_A32(tb_flags, SCTLR__B); + dc->hstr_active =3D EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); + dc->ns =3D EX_TBFLAG_A32(tb_flags, NS); + dc->vfp_enabled =3D EX_TBFLAG_A32(tb_flags, VFPEN); if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->c15_cpar =3D EX_TBFLAG_A32(tb_flags, XSCALE_CPAR); } else { - dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->vec_len =3D EX_TBFLAG_A32(tb_flags, VECLEN); + dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); } } dc->cp_regs =3D cpu->cp_regs; @@ -8924,8 +8920,8 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); + dc->ss_active =3D EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); + dc->pstate_ss =3D EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex =3D false; =20 dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; @@ -9364,11 +9360,11 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb, int max_insns) DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; =20 - if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) { + if (EX_TBFLAG_AM32(tb->flags, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) { ops =3D &aarch64_translator_ops; } #endif --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779854; cv=none; d=zohomail.com; s=zohoarc; b=nhTI5j+mRAQFjqd9PJVoMoALWHhN87bvdgxkteJ0zjpzCQ3sdrdrPgsqh2dqCgs9zmkQhO75X22Rmi+vW/XRyjInsSjA5HQ8eum5JpND49wvCFiKbYuh5f+OATueaaonaoPWXvQg/gQoBz9Q+E8kG2A3rBzh+hyaU2vHNcFVcoY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779854; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sZqTSVg6Wco6ezIrG0NPW/QcxBST5odGK5H+TyAOwLg=; b=mkLZfdbBtLYiKxFEOYELCOEI8RUP4RykDwDS054naQxPFUHqlwmVAzQLo2ZwSeq9k6JFCwp7oi1TqtEMmofm88mIquQx0BJ0vIn1wFHTKqYb+ZDF8zxJC08LI7//+t62KbiKROoSxS5JKSi/HfdJIwM59NadCvdg62vMCzrl5Io= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779854339678.2832111657966; Fri, 30 Apr 2021 03:50:54 -0700 (PDT) Received: from localhost ([::1]:42864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQjU-0001WK-AV for importer@patchew.org; Fri, 30 Apr 2021 06:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU3-0007ZP-TV for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:55 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:38880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU1-0001Hf-AH for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:55 -0400 Received: by mail-wr1-x42d.google.com with SMTP id l14so149570wrx.5 for ; Fri, 30 Apr 2021 03:34:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sZqTSVg6Wco6ezIrG0NPW/QcxBST5odGK5H+TyAOwLg=; b=en6+acGSySFdbnu8PqO2kMi0tRF/aNv2aSAR4i0wxJRhJSnmEBs4IiiIT7VWK2aGvi 691qPwXBsPU3Mz+6y5QT9WLcgtI3vqkdwkpJeD9TH02wDdMrKMMKRICMJbR6y4S0QeXX xPGt0z/bV08UPAIyQODzh5QcMSOXRBdvnSpAfen+fTMXadMJw1IC0cPkyyXab6pQM2s0 XtPIqfEPhiRmT3CyEVsMA8ZweH/QpTA48ssyrsmhTCvm+L6dFMlWlWU+EMFCGbnAo0gk tLEDoIVjvnj3HbynKa0tYsXZUvwerAVwjRqX9y7VZxU13qvwmpBNyN4JG5IscC6Hq9Cf a56A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sZqTSVg6Wco6ezIrG0NPW/QcxBST5odGK5H+TyAOwLg=; b=OF6rdFfsoP1cEhLUvqyQcAUusTmYxUkpoo1SnZdwCEMecHh6TQAfLsge2RZJwI2dcz BfXKsmtzB466HsZ6WK/DRy7kOeShb3ZWUmGdeXeKeoSspEbUSnAVGqrodoIULS476sIU wm2wmfz+1Xr0DHWCUcS0FUAcBBBvtidp4gUOWJfP6JhepUyDDmbqXsCWi5YlGvW/eaOE tsO6BpurfazwPl0cIEYnWWbDfPnw6HyW5pO5p7su+KlPUYoPHFHFaDaX1bKKAbyogNe6 8AYBapP7+2XROCr0AJG+Lypk6tM+Y+/m1D1H4zQDh5L7h5SnCaSwLEIeYAixjVTG/so3 xysA== X-Gm-Message-State: AOAM532v5d+cItcFknRpoURteXn8acrx1bbxj2LtnRVFh4TIqliZqNMW ZdDqwdx3st+dFwzSE7zZsjoZj63rd1DOpbL8 X-Google-Smtp-Source: ABdhPJxghr51E5yMiOHJvTLdok/4iqVSNNWOaKf3hpHp3MhO4evgclnEmZ4PVqs0RyY2tmzZfqj9vw== X-Received: by 2002:adf:e906:: with SMTP id f6mr6079621wrm.200.1619778891867; Fri, 30 Apr 2021 03:34:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/43] target/arm: Introduce CPUARMTBFlags Date: Fri, 30 Apr 2021 11:34:10 +0100 Message-Id: <20210430103437.4140-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson In preparation for splitting tb->flags across multiple fields, introduce a structure to hold the value(s). So far this only migrates the one uint32_t and fixes all of the places that require adjustment to match. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 26 ++++++++++++--------- target/arm/translate.h | 11 +++++++++ target/arm/helper.c | 48 +++++++++++++++++++++----------------- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 7 +++--- 5 files changed, 57 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b798ff81150..79af9a7c628 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -225,6 +225,10 @@ typedef struct ARMPACKey { } ARMPACKey; #endif =20 +/* See the commentary above the TBFLAG field definitions. */ +typedef struct CPUARMTBFlags { + uint32_t flags; +} CPUARMTBFlags; =20 typedef struct CPUARMState { /* Regs for current mode. */ @@ -253,7 +257,7 @@ typedef struct CPUARMState { uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.n= RW */ =20 /* Cached TBFLAGS state. See below for which bits are included. */ - uint32_t hflags; + CPUARMTBFlags hflags; =20 /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access @@ -3466,21 +3470,21 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) * Helpers for using the above. */ #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST =3D FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) =20 -#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) =20 /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df0..f30287e5546 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -394,6 +394,17 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TC= Gv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); =20 +/** + * arm_tbflags_from_tb: + * @tb: the TranslationBlock + * + * Extract the flag values from @tb. + */ +static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) +{ + return (CPUARMTBFlags){ tb->flags }; +} + /* * Enum for argument to fpstatus_ptr(). */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2769e6fd355..f564e59084a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12984,8 +12984,9 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif =20 -static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, + CPUARMTBFlags flags) { DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); @@ -12996,8 +12997,9 @@ static uint32_t rebuild_hflags_common(CPUARMState *= env, int fp_el, return flags; } =20 -static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, + CPUARMTBFlags flags) { bool sctlr_b =3D arm_sctlr_b(env); =20 @@ -13012,10 +13014,10 @@ static uint32_t rebuild_hflags_common_32(CPUARMSt= ate *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) { - uint32_t flags =3D 0; + CPUARMTBFlags flags =3D {}; =20 if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -13035,18 +13037,18 @@ static uint32_t rebuild_hflags_m32(CPUARMState *e= nv, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) { - int flags =3D 0; + CPUARMTBFlags flags =3D {}; =20 DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } =20 -static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) { - uint32_t flags =3D rebuild_hflags_aprofile(env); + CPUARMTBFlags flags =3D rebuild_hflags_aprofile(env); =20 if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); @@ -13060,10 +13062,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *e= nv, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_e= l, + ARMMMUIdx mmu_idx) { - uint32_t flags =3D rebuild_hflags_aprofile(env); + CPUARMTBFlags flags =3D rebuild_hflags_aprofile(env); ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; @@ -13179,7 +13181,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 -static uint32_t rebuild_hflags_internal(CPUARMState *env) +static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) { int el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, el); @@ -13208,6 +13210,7 @@ void HELPER(rebuild_hflags_m32_newel)(CPUARMState *= env) int el =3D arm_current_el(env); int fp_el =3D fp_exception_el(env, el); ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); } =20 @@ -13250,12 +13253,12 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env,= int el) static inline void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG - uint32_t env_flags_current =3D env->hflags; - uint32_t env_flags_rebuilt =3D rebuild_hflags_internal(env); + CPUARMTBFlags c =3D env->hflags; + CPUARMTBFlags r =3D rebuild_hflags_internal(env); =20 - if (unlikely(env_flags_current !=3D env_flags_rebuilt)) { + if (unlikely(c.flags !=3D r.flags)) { fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08= x)\n", - env_flags_current, env_flags_rebuilt); + c.flags, r.flags); abort(); } #endif @@ -13264,10 +13267,11 @@ static inline void assert_hflags_rebuild_correctl= y(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags =3D env->hflags; + CPUARMTBFlags flags; =20 *cs_base =3D 0; assert_hflags_rebuild_correctly(env); + flags =3D env->hflags; =20 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc =3D env->pc; @@ -13333,7 +13337,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 - *pflags =3D flags; + *pflags =3D flags.flags; } =20 #ifdef TARGET_AARCH64 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 05d83a5f7a9..b32ff566669 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14670,7 +14670,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D env_archcpu(env); - uint32_t tb_flags =3D dc->base.tb->flags; + CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); int bound, core_mmu_idx; =20 dc->isar =3D &arm_cpu->isar; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5c21e98d243..6a15e5d16c1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8852,7 +8852,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D env_archcpu(env); - uint32_t tb_flags =3D dc->base.tb->flags; + CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); uint32_t condexec, core_mmu_idx; =20 dc->isar =3D &cpu->isar; @@ -9359,12 +9359,13 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb, int max_insns) { DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; + CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(tb); =20 - if (EX_TBFLAG_AM32(tb->flags, THUMB)) { + if (EX_TBFLAG_AM32(tb_flags, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) { ops =3D &aarch64_translator_ops; } #endif --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779522; cv=none; d=zohomail.com; s=zohoarc; b=MIw0SNRl4O8I+CaI8QK8X2S63Gy/kw8+2qHv3ZOHP5Xz2uTZQQPOm2U7IQcDpxiGDCpJGcGUvbLhbMfJqdLavjVKu5Z+d0Kx2TRqwRa+IsnEnvAruACkHlIZy0p8E/12bmDI2lKDbb+OJ6YYGEq6xQwvg5GTjWylejeHQKHj3jI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779522; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qxfeJ+r48PTlYS71pSASDOPU4fkG5/jwNghgVWaWz5o=; b=at2b9+j7eHeEefirNlASKx9/BDKgrFeVVDF9fQh1WtlMNLRQfXr1tTlT5VYDOYaZ2N eZzvWDoVQwTU9/cPZYU5i72cWS8SK9W0u+7Z3nq420Kz+sJ+eulvPQqpgXV6DS9Ez2GB Db9Onmh17c+FGiVOFXhU2Bv6uXV9qm1+b8opgUU3ol65yi979cIHXwDGb5KJi3/eZMnS Cs1zCUN12JhWYIDLPRoqb7+RPpTe0m5FTLCbBEyU/59858g/Hgw5/FmI+gvdTJojtHYy gbEQe09VNw3ZE1fCqTTROrV5g3AavizH3a7zh1aHI+MPKJI/B0w1QbZZlTrBGHNqNf1A RYEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qxfeJ+r48PTlYS71pSASDOPU4fkG5/jwNghgVWaWz5o=; b=RjFI5hI0HyPaloJLbwevnVFlnkipe0s7yzyLUdXPNROgEAd7LNPEOH0jx4C3mHuMcM 72rJLjAQPvUdf2wBnlCi3l1FS5H9OF8TgdhNZnEI3sxSit6L1n5SWjknOv8ZwJCdolNK K45G8+hrjVyKDsYX4rlhdsskLqnEW1oLDd5bjHQ2qz6fqDyUrEToHGu1SlZINhJZs1mt gLv84lAwwwYnFE2G5V3LpIbSzmy5IfzzUFavbvFbn56iVQeLcNERnD8Vtp10lpjcDqjg nucB53SKcYILCDzg7yARv3VkBVLt4heCZUv+suhhmIo161R7tsuV68KovovBiGAs5IGT r/SQ== X-Gm-Message-State: AOAM530k9uwjl3fwoMDZ6KGFJ88ZvNN+51BI1/W6NE2h+FZWeJaP1Lho chmO41R22LqYbEeVhHCC2V+l6BcIL9oZoK5b X-Google-Smtp-Source: ABdhPJx9RK6fw8gweCfRD2tz+532PMKSB13AEyo8mcoIWqfVW7IAgKWZTc2S2QLKzGHYysjzwXzIvw== X-Received: by 2002:a7b:c5c1:: with SMTP id n1mr15598854wmk.83.1619778892792; Fri, 30 Apr 2021 03:34:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base Date: Fri, 30 Apr 2021 11:34:11 +0100 Message-Id: <20210430103437.4140-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Now that we have all of the proper macros defined, expanding the CPUARMTBFlags structure and populating the two TB fields is relatively simple. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 49 ++++++++++++++++++++++++------------------ target/arm/translate.h | 2 +- target/arm/helper.c | 10 +++++---- 3 files changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 79af9a7c628..a8da7c55a6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -228,6 +228,7 @@ typedef struct ARMPACKey { /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { uint32_t flags; + target_ulong flags2; } CPUARMTBFlags; =20 typedef struct CPUARMState { @@ -3381,20 +3382,26 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" =20 /* - * Bit usage in the TB flags field: bit 31 indicates whether we are - * in 32 or 64 bit mode. The meaning of the other bits depends on that. - * We put flags which are shared between 32 and 64 bit mode at the top - * of the word, and flags which apply to only one mode at the bottom. + * We have more than 32-bits worth of state per TB, so we split the data + * between tb->flags and tb->cs_base, which is otherwise unused for ARM. + * We collect these two parts in CPUARMTBFlags where they are named + * flags and flags2 respectively. * - * 31 20 18 14 9 0 - * +--------------+-----+-----+----------+--------------+ - * | | | TBFLAG_A32 | | - * | | +-----+----------+ TBFLAG_AM32 | - * | TBFLAG_ANY | |TBFLAG_M32| | - * | +-----------+----------+--------------| - * | | TBFLAG_A64 | - * +--------------+-------------------------------------+ - * 31 20 0 + * The flags that are shared between all execution modes, TBFLAG_ANY, + * are stored in flags. The flags that are specific to a given mode + * are stores in flags2. Since cs_base is sized on the configured + * address size, flags2 always has 64-bits for A64, and a minimum of + * 32-bits for A32 and M32. + * + * The bits for 32-bit A-profile and M-profile partially overlap: + * + * 18 9 0 + * +----------------+--------------+ + * | TBFLAG_A32 | | + * +-----+----------+ TBFLAG_AM32 | + * | |TBFLAG_M32| | + * +-----+----------+--------------+ + * 14 9 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3472,19 +3479,19 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) + (DST.flags2 =3D FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) + (DST.flags2 =3D FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) + (DST.flags2 =3D FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST.flags =3D FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) + (DST.flags2 =3D FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) =20 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHIC= H) =20 /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index f30287e5546..50c2aba0667 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -402,7 +402,7 @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i= 64, TCGArg, MemOp); */ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) { - return (CPUARMTBFlags){ tb->flags }; + return (CPUARMTBFlags){ tb->flags, tb->cs_base }; } =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index f564e59084a..4aa7650d3a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13256,9 +13256,11 @@ static inline void assert_hflags_rebuild_correctly= (CPUARMState *env) CPUARMTBFlags c =3D env->hflags; CPUARMTBFlags r =3D rebuild_hflags_internal(env); =20 - if (unlikely(c.flags !=3D r.flags)) { - fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08= x)\n", - c.flags, r.flags); + if (unlikely(c.flags !=3D r.flags || c.flags2 !=3D r.flags2)) { + fprintf(stderr, "TCG hflags mismatch " + "(current:(0x%08x,0x" TARGET_FMT_lx ")" + " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", + c.flags, c.flags2, r.flags, r.flags2); abort(); } #endif @@ -13269,7 +13271,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, { CPUARMTBFlags flags; =20 - *cs_base =3D 0; assert_hflags_rebuild_correctly(env); flags =3D env->hflags; =20 @@ -13338,6 +13339,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } =20 *pflags =3D flags.flags; + *cs_base =3D flags.flags2; } =20 #ifdef TARGET_AARCH64 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779677; cv=none; d=zohomail.com; s=zohoarc; b=N6k8fmbbpp9lNcq426s1XMzMf0HIM2iHBQhew0KJNSO4pIVSrLpRRV2GvDUlXwJkwWQZ4yZsox70iMNNJ+LNeQueXfFFl9X4igoSiRtHHXByzMmdzik+VTkz13n7hjE3oSA5iA/0JWTYfZ1vcLYDopW77PG/nymkvdVUa4Tni/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779677; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XelyLsE4aJXExt//pcxleFAQzG0HTjHRhGLlyhd1Bgo=; b=xoNA/8WPXoO3+WMM3hfIGFi4J2+DkEhSavVetUJpWp9v4V40JKQxpO9kzHv/Zj3PdF pTT2BbPhLwp3Ziy4fF9qQyIVbFXuVlAsEa4Z96zvlwzixcsOdV3fV9WqehXEJeEaKg/F /qjhrp1gpDo8U2B73CrP1LD/cAcmc/EFveFrXHYitOrfGo/1z5uhW8kWOHq/xNxVkNtu 285rANW6F4ciVAs5VgV+WF8C5yVRfJm77ddlUe9LQuVyKJwzVwx2r1vVU6PLc1yitmT7 1dgg6D5nPUsD3WSoZGVR9A4nMGTxHx8XnmhnAdsAzZAk/PzkARBNgwa3DPIGOExmGomO 2iAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XelyLsE4aJXExt//pcxleFAQzG0HTjHRhGLlyhd1Bgo=; b=EqMTTJ4tuj1cEdOmBnsos1SCulJDrDOkwOYSEfFQ5bCOScR7pJc5ulXZQp+7YJsPol 433k7BXVljc3amq1O/AAazVjJNzNim9B4luYF4FTYwAJg8C8g20L3nH5ZMZ7TkHSo767 hviHurwld7YiELEGFqfo8YnmWgkBIYe8WcmX13KxObXmimEERt7Z3gLSEE8YsloWQhae Dfoc9Fj3K7/H2Lp65yqInVzm8RJAOKnSe6zq2lJuJEqThyzCN5Smtcnk8efzH0xts1od eNRZqLjv3YCAoZWOM+8grE2vYVKmanhv61MCVHDo2csmQJdgF9kmjmGZINoRdgo4L5Qm RO8A== X-Gm-Message-State: AOAM531hSb6J4ZOV6auJ6fcq7pQIB1mZ6Mi5uyVq32BzoXmbl5IYRrsX l/FvfboLisoeHpZ99roO8XPolGU54Hgn48FA X-Google-Smtp-Source: ABdhPJzrVOex7zkkFbd9WBxhwLaS+6OAZrrIeT+axVLw+BXwZiTmnIZNBGyDfin7KYR8K62XwtwSfA== X-Received: by 2002:a05:600c:35d1:: with SMTP id r17mr5321073wmq.71.1619778893417; Fri, 30 Apr 2021 03:34:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top Date: Fri, 30 Apr 2021 11:34:12 +0100 Message-Id: <20210430103437.4140-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Now that these bits have been moved out of tb->flags, where TBFLAG_ANY was filling from the top, move AM32 to fill from the top, and A32 and M32 to fill from the bottom. This means fewer changes when adding new bits. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8da7c55a6b..15104e14409 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3395,13 +3395,13 @@ typedef ARMCPU ArchCPU; * * The bits for 32-bit A-profile and M-profile partially overlap: * - * 18 9 0 - * +----------------+--------------+ - * | TBFLAG_A32 | | - * +-----+----------+ TBFLAG_AM32 | - * | |TBFLAG_M32| | - * +-----+----------+--------------+ - * 14 9 0 + * 31 23 11 10 0 + * +-------------+----------+----------------+ + * | | | TBFLAG_A32 | + * | TBFLAG_AM32 | +-----+----------+ + * | | |TBFLAG_M32| + * +-------------+----------------+----------+ + * 31 23 5 4 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3418,44 +3418,44 @@ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) /* * Bit usage when in AArch32 state, both A- and M-profile. */ -FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ -FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ +FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ =20 /* * Bit usage when in AArch32 state, for A-profile only. */ -FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) -FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. = */ -FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ -FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) +FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ +FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ +FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) /* * Indicates whether cp register reads and writes by guest code should acc= ess * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 17, 1) +FIELD(TBFLAG_A32, NS, 10, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. */ /* Handler (ie not Thread) mode */ -FIELD(TBFLAG_M32, HANDLER, 9, 1) +FIELD(TBFLAG_M32, HANDLER, 0, 1) /* Whether we should generate stack-limit checks */ -FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +FIELD(TBFLAG_M32, STACKCHECK, 1, 1) /* Set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ /* Set if we must create a new FP context */ -FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ /* Set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ =20 /* * Bit usage when in AArch64 state --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779737; cv=none; d=zohomail.com; s=zohoarc; b=BwFvpxXut+i7eRDVjXRMaBI+BfIUBrnwyPk41L7EYGqkVyq+GFTmXPBBbIuCXekkkQ8RUTmJz4UJqUBGk3G3UJktwBumcqc0YHfbY603gOjCxOXNCvao3r4oxviODapqLxQ19C/jgm1WrHCFtp445fFRv35ZjS9HKzwrodOik8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779737; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vz1LJCMv6JjuUN7yQ6ggOJnEC1TZC23JtEoNMy6u2go=; b=aR71EcS/HwHBYmlTN4h8J9P4APKeqQzCrEButq2Wds+MXC3Q+hp6s8ziJrMaA+ZR7GHaQ4F4PRC+/paDbXwqnlcfat+DgPu7746u43r04PLAYqWuyLzB0Kc8nztgVHzOB3HJTlY9SP+3xtxF+BcdmvnL8dy+izn0pwY7y+3y84E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779737268548.6823401181329; Fri, 30 Apr 2021 03:48:57 -0700 (PDT) Received: from localhost ([::1]:37494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQhb-0007lJ-3N for importer@patchew.org; Fri, 30 Apr 2021 06:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU5-0007cH-FI for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:57 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55172) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU3-0001Iy-LU for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:57 -0400 Received: by mail-wm1-x32c.google.com with SMTP id k128so37547622wmk.4 for ; Fri, 30 Apr 2021 03:34:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vz1LJCMv6JjuUN7yQ6ggOJnEC1TZC23JtEoNMy6u2go=; b=QE/iKHeo9GII4WN7i8C1a4toSu7n8MEWqX79Q5yVMKSeaYz6qZz3DJQwMR5J3YBUrt uiC/PLbZoJt0T4+FfGkOdOL+DBLg5aGwGE/knMW45gx2sTR3DDX5RmVpMVwJsDhJ+8QM plwQCf0GRBaCqDPjHC02bDFQqxk3OAbtYgiYSbRJ6CVRlUyKQGlxC568pFqDIc2Q+fge +uQKQKWKESN7FnLafLtkT+YPCh5TASV0Airyckm0EjFL4VlaQpY9G7Bt2TDRw8MO6w8e Wp/VWaHkPn2J6dTaSD1x7Tuo2Hmi27u3Kp9p1Fo4Wkd3qH8iU7ySuHvDVATAekzNok2u R5UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vz1LJCMv6JjuUN7yQ6ggOJnEC1TZC23JtEoNMy6u2go=; b=fZqyp4Krun6WLP6Li3KpiO8b+wKPUiXNJGiDRs/7HSLe6w3pbs9EKTxwlGoWJcohBR vVo3VX4zKkrBwRrwhoym781Su/wkO6fFqLMUe3dmUd52h0rTYqXCOCSZLo4AS7/dQJJ5 dpkPTMDfb6/H9/GlAUlHnwB6c9/PckZ8B24QuxMdrIVkozZZsIBd1E/K+g5b/Bq6FiAl odrapd58WzabShSYxNFN86LsyP/zzmScbRvaV3RcFZHLtHvNICPc8joFmDM3eHg2LeQy KtgX04wiewtE/z1WRg3c8kLjBdX9p8Cmj4plALq8PhWyLGuijw4vKtk8we4BE4MuIkKa vsCg== X-Gm-Message-State: AOAM530iRQmDRGRUZROx3QY4cer18h0timiu6KUluECHUfNhJC+2z+/3 nbUHVtHXMVGq1QS8Fvoo0PcjYuKl2FcB5BgW X-Google-Smtp-Source: ABdhPJx7tRfwKSBnLejf+FJtpHJDoi6o04/6YUUK6lE5Ux7+k+GhxuAIXwF+iskwIAjgF+md/T9unw== X-Received: by 2002:a1c:540b:: with SMTP id i11mr15937312wmb.40.1619778894001; Fri, 30 Apr 2021 03:34:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom Date: Fri, 30 Apr 2021 11:34:13 +0100 Message-Id: <20210430103437.4140-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Now that other bits have been moved out of tb->flags, there's no point in filling from the top. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15104e14409..5e0131be1a2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3405,15 +3405,15 @@ typedef ARMCPU ArchCPU; * * Unless otherwise noted, these bits are cached in env->hflags. */ -FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) -FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */ -FIELD(TBFLAG_ANY, BE_DATA, 28, 1) -FIELD(TBFLAG_ANY, MMUIDX, 24, 4) +FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) +FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) +FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 3, 1) +FIELD(TBFLAG_ANY, MMUIDX, 4, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) +FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779682; cv=none; d=zohomail.com; s=zohoarc; b=HTr+ppdNvml1hEVNmEDBvIDgJvJUrL7eaxxiwqjjBGKgIuDDPjWuNck412YfjgRcfS6+ZZEgnUqUnbniT3biVw4JkPatQgXtEno0FOrJlokF6ua+WaRjHAU0YCotMBLgqW5VpyjrlkqxQjynY8MgwA4HBYed6WdtOQnNWFac5FQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779682; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9HWrWug8jmPoHYTE2hJ7tPtwvHTlCshBAknL7qWDnXA=; b=GLfIq14G3+fcDVjg2o08M6c6ngy3sICxD9rcrAZs1x2oD8BH4qPF+8tmAmxvsxAdcbB8B9HN+KmaekGogmHHUSD5Xaw6vUdGTVi5PCPy+tzPhJby0J6XN85gSwXf5cZx+Vjugdk/36M7P3V054UTK5pG3qnokq2yCJg4moIoAoQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779682182868.0789546617278; Fri, 30 Apr 2021 03:48:02 -0700 (PDT) Received: from localhost ([::1]:34836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQgj-0006dH-5z for importer@patchew.org; Fri, 30 Apr 2021 06:48:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU6-0007e1-6U for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:58 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU4-0001Ji-70 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:57 -0400 Received: by mail-wr1-x432.google.com with SMTP id m9so57258800wrx.3 for ; Fri, 30 Apr 2021 03:34:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9HWrWug8jmPoHYTE2hJ7tPtwvHTlCshBAknL7qWDnXA=; b=nVrLIgtFHbam7kZr+pJcxzlqSRbV7xsXB/4IPH1r+NZMxHTSy6X2+2q3MJ7EoM+yM/ LQAJehYFRsWWS7yV7WP8zVo3sDL5h2kuX80BMl+1Oc7p0lJMOvXCiOEeLoXgZOwTMnCB EuiLlVCscKENPSZW5wmaIrRCZY2on0UrIaytqW38g3yxWntwVFVJq5ubjBxDeifwozeE +nlub+IcG/3XJ/59c3iC1xslecs6GwNHIeY+ThXWPg+e8dkJpuSuLx90DE3gt7MR9NUh EXWryLkU1htgMnW7yzZ0BI/r3T003ODGOh2ry7jssPw2PEaeWIEwkEbPOGDqnPM8cxyj E2Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9HWrWug8jmPoHYTE2hJ7tPtwvHTlCshBAknL7qWDnXA=; b=uIa7gSEQC0CQfN5XsgaWoa+XDYll640lNLmYthur1fZ6imW2hyuA2C7ao8h2HdP/YZ 2NoT2J40KUWHynwj6QYuXF9d0Jc950gEK8rMGwPeMWPKGl7+/zRC5Cxm6sGO1Lfxib5E SCJuO5/T7G/oYls2H8qfiDvfvzGr1Vxo65KTxB5Agu9MUslT/tpSw4K2P8IobVxB9uXa 9Qgq0cDXfp3ykd3k5P9pl9UfsbedpvK8GTkbSIPT/5EiMv7naxeHbMwN/qI8spIR/I88 So+Fbgxhs/r2iI/hREJyPVZobrgHWLbHs8KOz0DTfL8GxRGXp7W8aCpn0HTqwe1VjUTY 25GA== X-Gm-Message-State: AOAM5306G9dPX7K+eld34CNw0E2dCVJvAlZ+Oix+salKRIVO3qOMBKKT CjLdW/Ekcrin+Qi0ZHrlaZWDwyzBxY+kLUJB X-Google-Smtp-Source: ABdhPJw8QQfdnXALACTtg2wOFUVNJ5KylHZKlZCv789X9vzXcug3nS7VQ/wDpH5aIX/tyP1agmuyHQ== X-Received: by 2002:adf:f241:: with SMTP id b1mr2377689wrp.150.1619778894787; Fri, 30 Apr 2021 03:34:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY Date: Fri, 30 Apr 2021 11:34:14 +0100 Message-Id: <20210430103437.4140-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use this to signal when memory access alignment is required. This value comes from the CCR register for M-profile, and from the SCTLR register for A-profile. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++-- target/arm/translate-a64.c | 1 + target/arm/translate.c | 7 +++---- 5 files changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e0131be1a2..616b3932534 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3414,6 +3414,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 4, 4) FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ +FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 50c2aba0667..b185c14a035 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -87,6 +87,8 @@ typedef struct DisasContext { bool bt; /* True if any CP15 access is trapped by HSTR_EL2 */ bool hstr_active; + /* True if memory operations require alignment */ + bool align_mem; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 4aa7650d3a7..9b1b98705f9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13018,6 +13018,12 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMStat= e *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags =3D {}; + uint32_t ccr =3D env->v7m.ccr[env->v7m.secure]; + + /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ + if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } =20 if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -13030,7 +13036,7 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState= *env, int fp_el, */ if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { DP_TBFLAG_M32(flags, STACKCHECK, 1); } =20 @@ -13049,12 +13055,17 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMSta= te *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags =3D rebuild_hflags_aprofile(env); + int el =3D arm_current_el(env); + + if (arm_sctlr(env, el) & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } =20 if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); } =20 - if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && + if (el < 2 && env->cp15.hstr_el2 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } @@ -13099,6 +13110,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMStat= e *env, int el, int fp_el, =20 sctlr =3D regime_sctlr(env, stage1); =20 + if (sctlr & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { DP_TBFLAG_ANY(flags, BE_DATA, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b32ff566669..92a62b1a751 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14697,6 +14697,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->user =3D (dc->current_el =3D=3D 0); #endif dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sve_len =3D (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; dc->pauth_active =3D EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); diff --git a/target/arm/translate.c b/target/arm/translate.c index 6a15e5d16c1..970e537eae0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -933,8 +933,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 v= al, TCGv_i32 a32, { TCGv addr; =20 - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |=3D MO_ALIGN; } =20 @@ -948,8 +947,7 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 v= al, TCGv_i32 a32, { TCGv addr; =20 - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |=3D MO_ALIGN; } =20 @@ -8877,6 +8875,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->user =3D (dc->current_el =3D=3D 0); #endif dc->fp_excp_el =3D EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); =20 if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled =3D 1; --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780009; cv=none; d=zohomail.com; s=zohoarc; b=QFY594reTuhek+TwR2kOzKPwZEv0ZffPho7IQvfOXVBCb7HBm85OXkc7S/4In+sjUj8uAQwuwANGfCVoxR5gIfB5LzKWwU1rf3gfFdiaUu/1FzNXwvAVEmwE1wVBJattiyGsGOyO1vFsZVfltbzFJP0Har8yPAzMomhwGcvxTNo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619780009; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Pr3emJngQ8q9YaGb+93M0B7Old0uTo2ChY3L4kgMIaA=; b=hs0d8g5nFGgnVzpUuTJf69Dnr7R+zGX+r4BkVAclW5hs2KqRpmDPpSQ5Ck6aXIvDOv vFmtuz5LomI5vSybd9rUJLJhcUeVqcvJWCBw5IfywI7sJyo0vIZ9lTh3Vpik/YgcEIn/ 1FRZY5zzS3Qbej+A/bSPpSTkcCRz0hCnGkmYfDKcte3/Pcr2hL5POFYrIBMamI+ef54h xTZdMcft4hqk6EvtQs7fsHNtrXHySW1fF468k8SDkhMiJhPj+qArsc7m0+qRyCMoQ9eX F7jQjLvjvUtjfPNyUrMbTLI0hyhpWvZpUU2Mp6v+HnL1V/r1mnE8NJ5TmW+nRzMujHvH JGSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Pr3emJngQ8q9YaGb+93M0B7Old0uTo2ChY3L4kgMIaA=; b=uWDXvGRr8QsfRc1DzgzfED3fLyc8ybPrmLv8VuYEk0jd1DQxq30O3ME6ZAUOw88UAd n9EoeaNfGBsBHkN7wV0HjTT9iAAq65WQQMjrugS9O239XcZdgndAimOZ1rO8RIa0hBxG 1SkjpmHobVCYC8SOB0Ty3kooeCkYpnTMODlssLlDIW6p3hy7zfTRNJ1F8CwNEO376+rg 4o15JcwT07BQ/vaXyrdoot1eeXCBti2dcmFYY8f35bjsd97KdLsQ5q5aX9F6ZLSumSGT hkKvLiIIKZCzaVUl7u+lQFSZjBuTEmMxemU/Z4Gy4sutbQT/S+dgyozUInAHfFbT9Pra CR6Q== X-Gm-Message-State: AOAM533ZTRsamLTqwjvurpZSYKBKL9zrtHzn8u8tuLp2Nq9KU+4F7cBB 3u9PHSv74NFE9+SDJ79e4hWdnqfwENDvGp/i X-Google-Smtp-Source: ABdhPJxK+7aVqjyZwjpFSKVUh0BIhj9zz+77lRA/9cKE+ZuG0NU19UVGRRxwtgdAAdJ4bN2pBTT4iQ== X-Received: by 2002:a05:6000:136b:: with SMTP id q11mr5873641wrz.350.1619778895611; Fri, 30 Apr 2021 03:34:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Date: Fri, 30 Apr 2021 11:34:15 +0100 Message-Id: <20210430103437.4140-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Create a finalize_memop function that computes alignment and endianness and returns the final MemOp for the operation. Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32 so that s->be_data is not added by the callers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.h | 24 ++++++++ target/arm/translate.c | 100 +++++++++++++++++--------------- target/arm/translate-neon.c.inc | 9 +-- 3 files changed, 79 insertions(+), 54 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index b185c14a035..0c60b83b3d4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -459,4 +459,28 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour= flavour) return statusptr; } =20 +/** + * finalize_memop: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Build the complete MemOp for a memory operation, including alignment + * and endianness. + * + * If (op & MO_AMASK) then the operation already contains the required + * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally + * unaligned operation, e.g. for AccType_NORMAL. + * + * In the latter case, there are configuration bits that require alignment, + * and this is applied here. Note that there is no way to indicate that + * no alignment should ever be enforced; this must be handled manually. + */ +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +{ + if (s->align_mem && !(opc & MO_AMASK)) { + opc |=3D MO_ALIGN; + } + return opc | s->be_data; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 970e537eae0..5bf68b782a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,7 +908,8 @@ static inline void store_reg_from_load(DisasContext *s,= int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif =20 -/* Abstractions of "generate code to do a guest load/store for +/* + * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero * extended if we're a 64 bit core) and data is also * 32 bits unless specifically doing a 64 bit access. @@ -916,7 +917,7 @@ static inline void store_reg_from_load(DisasContext *s,= int reg, TCGv_i32 var) * that the address argument is TCGv_i32 rather than TCGv. */ =20 -static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) +static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { TCGv addr =3D tcg_temp_new(); tcg_gen_extu_i32_tl(addr, a32); @@ -928,47 +929,51 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCG= v_i32 a32, MemOp op) return addr; } =20 +/* + * Internal routines are used for NEON cases where the endianness + * and/or alignment has already been taken into account and manipulated. + */ +static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr =3D gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_ld_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr =3D gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_st_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; - - if (s->align_mem) { - opc |=3D MO_ALIGN; - } - - addr =3D gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i32(val, addr, index, opc); - tcg_temp_free(addr); + gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; + gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); +} =20 - if (s->align_mem) { - opc |=3D MO_ALIGN; +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ } =20 - addr =3D gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_st_i32(val, addr, index, opc); - tcg_temp_free(addr); -} - -#define DO_GEN_LD(SUFF, OPC) \ -static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} - -#define DO_GEN_ST(SUFF, OPC) \ -static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } =20 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) { @@ -6456,7 +6461,7 @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *= a, addr =3D op_addr_rr_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); =20 /* @@ -6485,7 +6490,7 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr = *a, addr =3D op_addr_rr_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); =20 @@ -6508,13 +6513,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst= _rr *a) addr =3D op_addr_rr_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt + 1, tmp); =20 /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6537,13 +6542,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst= _rr *a) addr =3D op_addr_rr_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 op_addr_rr_post(s, a, addr, -4); @@ -6608,7 +6613,7 @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *= a, addr =3D op_addr_ri_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); =20 /* @@ -6637,7 +6642,7 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri = *a, addr =3D op_addr_ri_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); =20 @@ -6653,13 +6658,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) addr =3D op_addr_ri_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, rt2, tmp); =20 /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6692,13 +6697,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) addr =3D op_addr_ri_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); =20 op_addr_ri_post(s, a, addr, -4); @@ -6924,7 +6929,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp= mop) addr =3D load_reg(s, a->rn); tmp =3D load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); =20 tcg_temp_free_i32(tmp); @@ -7080,7 +7085,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp= mop) =20 addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); =20 @@ -8264,8 +8269,7 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *= a, bool half) addr =3D load_reg(s, a->rn); tcg_gen_add_i32(addr, addr, tmp); =20 - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - half ? MO_UW | s->be_data : MO_UB); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); tcg_temp_free_i32(addr); =20 tcg_gen_add_i32(tmp, tmp, tmp); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 0e5828744bb..c82aa1412e2 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -559,8 +559,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VL= D_all_lanes *a) addr =3D tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg =3D 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); if ((vd & 1) && vec_size =3D=3D 16) { /* * We cannot write 16 bytes at once because the @@ -650,13 +649,11 @@ static bool trans_VLDST_single(DisasContext *s, arg_V= LDST_single *a) */ for (reg =3D 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); } vd +=3D a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779877; cv=none; d=zohomail.com; s=zohoarc; b=YwI9tsJ+1yTDz06jisiC3yO7jbolkBnHlca/wOQZVQLC7d2Gsox+uXEw5+qatumA6TOPpf65CtnWr/39FpGsCggsZl1R0OOhRY1+JpglW0RG9NnEKQE8m1vW8zJu0WMGaeMliSPfiEMa9OY3spxlHeTrWJxZW5MHnHoD4XCdYbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779877; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qJ11aC8SWlzdnuc2gbrgeue1Xt+Ln546lI5n8RTAtlM=; b=mEuIHzJb4leOD4ro8x2lj1FbJDqFMCKNHRab4uSR07Px+fSIiRPbgMR63gqCIJJ8N7FBPJaCgx1VXJ7TUfhqMsT4hILyFXTgcBOhG6LtRnqjEaXbfrqvbauLSykxlV2v9anN5xqUmmQ+Oz1aWPP5zgawayyFzUQBlAFUHdLe1m4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779877689677.1023909574137; Fri, 30 Apr 2021 03:51:17 -0700 (PDT) Received: from localhost ([::1]:43488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQjs-0001nY-Fm for importer@patchew.org; Fri, 30 Apr 2021 06:51:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQU7-0007hW-GC for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:59 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:55177) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU5-0001Kx-Kr for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:34:59 -0400 Received: by mail-wm1-x331.google.com with SMTP id k128so37547668wmk.4 for ; Fri, 30 Apr 2021 03:34:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qJ11aC8SWlzdnuc2gbrgeue1Xt+Ln546lI5n8RTAtlM=; b=oiCKCQEgJ7XmaPld1k4qjXBBwJ+VAWA2T9CKOabUPIz1lv/FF0edJnqDRLO49rR6ET Pw8GqaJyXux+YuSZxBStSzRTaYjFv/DgpHHVbMi6yVtPmgd09iKnFftqepAq4JT5Me4e WnX6SGWjT1/xN9w2uTrJAPgGThpAjH4ytA8c0bnEL44HK+ojfm4fhEQwqIXXT7wMIGNB Jyf9qw98kfo2lPxir/sLSOER98LZVuojtTxnBnuFhD1ulD36IMMVBUNe9+zvnumfZMnn yqgnEOuTQWTHFvh9iVMVrdNKAlX4G4mu8vlIbZYifn7KCt58vouVxzEFp/e6lrxZ4XSE EOBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qJ11aC8SWlzdnuc2gbrgeue1Xt+Ln546lI5n8RTAtlM=; b=QQjn/l0OPUaY7wskP7QbpiCkO/HKEPkijbPtgXBl+JojXIYvdNSSSug4SIH0C1iMAZ V8H2zi0IPjICJvr2dS3/Kc9Zehm0BwN3VP9pLEU3eq8AMrIsJdWtUd99kJXSmXhViRLe fVxcZKAafGdicazVAVpNsaoSQMdS6Z3W+Ed9mhubXZp3EV3sE/wH/PGERMdZ2ptE1HWO zMtYtlyOrZ0ZQ3bYZFpvjrR103MsFI2ZIwphCW3En/cbktxuoU+6l8edMwlyT/VGfB+p kr9MkikFVNBemoM3YM/qOlfkDdpPwjhYKPrvB05X7IetLl4q4G/bg9HVJe1s9MbyjNBF kJAw== X-Gm-Message-State: AOAM531s5m+ZA4972I/m2EYIQ3/qNxvpGiYaBP/yIIfeUSHePQD5dosq bBxVT0y+OzgByFV6sBGuc9Tz+hE9Rirm9UKW X-Google-Smtp-Source: ABdhPJxA+8fA8nzVaHriukTIyXHK/DOgvRVBWyVD4Q59U398gkBH9bNsYvtOrXx1wGdWchT+fym4NQ== X-Received: by 2002:a1c:2c85:: with SMTP id s127mr5313441wms.83.1619778896345; Fri, 30 Apr 2021 03:34:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Date: Fri, 30 Apr 2021 11:34:16 +0100 Message-Id: <20210430103437.4140-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the only caller. Adjust some commentary to talk about SCTLR_B instead of the vanishing function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5bf68b782a1..2f2a6d76b40 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -975,20 +975,17 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32= val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } =20 -static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) -{ - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { - tcg_gen_rotri_i64(val, val, 32); - } -} - static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i64(val, addr, index, opc); - gen_aa32_frob64(s, val); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); } =20 @@ -4987,16 +4984,13 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, TCGv_i32 tmp2 =3D tcg_temp_new_i32(); TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 - /* For AArch32, architecturally the 32-bit word at the lowest + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. That means we don't want to do a - * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if - * for an architecturally 64-bit access, but instead do a - * 64-bit access using MO_BE if appropriate and then split - * the two halves. - * This only makes a difference for BE32 user-mode, where - * frob64() must not flip the two halves of the 64-bit data - * but this code must treat BE32 user-mode like BE32 system. + * gen_aa32_ld_i64(), which checks SCTLR_B as if for an + * architecturally 64-bit access, but instead do a 64-bit access + * using MO_BE if appropriate and then split the two halves. */ TCGv taddr =3D gen_aa32_addr(s, addr, opc); =20 @@ -5056,14 +5050,15 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, TCGv_i64 n64 =3D tcg_temp_new_i64(); =20 t2 =3D load_reg(s, rt2); - /* For AArch32, architecturally the 32-bit word at the lowest + + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. Since we're going to treat this as a * single 64-bit BE store, we need to put the two halves in the * opposite order for BE to LE, so that they end up in the right - * places. - * We don't want gen_aa32_frob64() because that does the wrong - * thing for BE32 usermode. + * places. We don't want gen_aa32_st_i64, because that checks + * SCTLR_B as if for an architectural 64-bit access. */ if (s->be_data =3D=3D MO_BE) { tcg_gen_concat_i32_i64(n64, t2, t1); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780557; cv=none; d=zohomail.com; s=zohoarc; b=nZjIvNyarFlhf4IPXDs6uW4z/BgEqAYsBb2M3fElkClJY/2f138piPPABa+H2uDpDutZwBM1RuaVBXPFTex2yL+BHEtBiiiiyWzJRzAucQWniGfmEAMiyClrh3Fr5zi0P51k1TaiMGlWHBLj7an8YCfVwX4HQNtGupnRZHHbFgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619780557; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6S+nDjof/vi/mR5kh+7cKDsMYJD8jrm8Sa+giQo6P9U=; b=K7Z1+Uv0/U/mbLudHLRYiocvap+/76e8FCVYJxiP6vsVUz74cmlD/9j2iX2vOwbu6onRsBCSluga9hlyKkv1OCqm/w7MLynQk8HLQUqjkbzSB+joEnpgFuYCR++d4BttvFPJEsIu1I8favwWgh/OeSAl5sXyi+bo0+IGNVj7tZs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619780557381715.2814176960205; Fri, 30 Apr 2021 04:02:37 -0700 (PDT) Received: from localhost ([::1]:40948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQup-0004Xj-V5 for importer@patchew.org; Fri, 30 Apr 2021 07:02:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQUJ-0007pk-0E for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:11 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34635) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU6-0001LE-9a for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:09 -0400 Received: by mail-wr1-x42d.google.com with SMTP id t18so12415887wry.1 for ; Fri, 30 Apr 2021 03:34:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6S+nDjof/vi/mR5kh+7cKDsMYJD8jrm8Sa+giQo6P9U=; b=iG3HSNFsJXgNtTMcnFd1jD380i6GzyXvt+tRRwSC7eYrQfXkhmcaeqlfZWwh/WKNG/ sRpKZ4JtJb0oyYn4KbEyIgrOV4sqQ5fVQoPyoIb3Wy9Tm/gQeV8IZ79O/NrQLaqTRZTF Js5yz/0kN3Po7XLTEtRQxpJcGA/7DEBUMtX9Ny5oBtMU94nnDdguZg27644pgYVGNH/K EqzRl8s0nRXi+AZ2Zf365ogfiFDsDtzxu45reAAr6dPICnO7KUf97/pScNMra1RR4yR1 eOPIWsOy4iRIq2JtWhwjIBgTadXIUyKy5VDFfdBZ3RTyL5Lnz73lbYvpMNrhpp92rgr3 XJVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6S+nDjof/vi/mR5kh+7cKDsMYJD8jrm8Sa+giQo6P9U=; b=siDZA3Ol4736Wl9wVYSjx1lTaqX21auX8FSLB3W4pqWhW+0Ts0JKPH6zISaJ8eZenB pIZMPV6H5CVSzeGdhTFrpNclOjVFKIJTNcIXp1KGubtg5IQ5VNt8sOc2yaWoL2ASHhHC ZhaYXBjNPaivezzlzpjY62zMTC3SOhQFBnFFNBd9/YkSejofrSvmMTBCDPwKWniKRFcs MHoQ4OctVIEJo7EzGzAcZb2k2vpcH7SQL4Gd6MM0mDrySls5HmQLwKvBKnjUUealOiaZ RT+B2IRsBeh7sRpJVpad6WmMIerYxQvL6rDH7Uh2i3ClGz4bLOlZ8ZCZAKCqN5k6bMPH wavQ== X-Gm-Message-State: AOAM532f4pN/G2HjA3OdC20hNA8JIQs++JjnE+mNR230Lq59e3Hw0iML 6YNXBR7CZsL1KPkdidxRnfh6jHns0YQ9o2Oj X-Google-Smtp-Source: ABdhPJwr9Emuma2sQJf4iDWCSFjopehhyKHjzz+3jNS/xDKF8uiAWEaCWl/iYSVSr7kFKI98kaQRyw== X-Received: by 2002:adf:e40f:: with SMTP id g15mr5940168wrm.392.1619778897058; Fri, 30 Apr 2021 03:34:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Date: Fri, 30 Apr 2021 11:34:17 +0100 Message-Id: <20210430103437.4140-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Just because operating on a TCGv_i64 temporary does not mean that we're performing a 64-bit operation. Restrict the frobbing to actual 64-bit operations. This bug is not currently visible because all current users of these two functions always pass MO_64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f2a6d76b40..e99c0ab5cb9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 v= al, TCGv_i32 a32, tcg_gen_qemu_ld_i64(val, addr, index, opc); =20 /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { tcg_gen_rotri_i64(val, val, 32); } =20 @@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64= val, TCGv_i32 a32, TCGv addr =3D gen_aa32_addr(s, a32, opc); =20 /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_rotri_i64(tmp, val, 32); tcg_gen_qemu_st_i64(tmp, addr, index, opc); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619779858; cv=none; d=zohomail.com; s=zohoarc; b=KwplR43p3ZfZM6zxDHiFBv1rIIedUYI82mML+KqMAn0V1KfmdJmVs9uCBpI8QORgnhE38JN/kK+Cy7cf/FroRXB9xjWy8qCh67+WetvdHUluvGTKKjJytNJBsOiZ1P0fcCuk+As7NtkboxotTw6NMmqc1csNIq1luQW1aHlwOCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619779858; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+fKmruWs1pZlntzyS0MXpNQCjVub/4BvghmzxXmwOv8=; b=RGvbE7lLelRjWqSlCIo4Hpq+4/Pi49W3XN38wgYBz968hEAbfNYYabcocBWH44Qjg0cBR7UnQujDXQoo1blfVXncCGUZKA8b0iybhJl8R6sHZpHU8BjOlySUZrmoul95J9eXXFCT79zuMoyEg2rI9OoI0G9z1y9bqDY7iLXC9FA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619779858428162.1223852427704; Fri, 30 Apr 2021 03:50:58 -0700 (PDT) Received: from localhost ([::1]:43062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQjW-0001az-NY for importer@patchew.org; Fri, 30 Apr 2021 06:50:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQUA-0007lg-Lu for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:03 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:42725) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQU7-0001LO-1N for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:02 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 4-20020a05600c26c4b0290146e1feccd8so1394278wmv.1 for ; Fri, 30 Apr 2021 03:34:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+fKmruWs1pZlntzyS0MXpNQCjVub/4BvghmzxXmwOv8=; b=PbRj4criJZwGJ7K70EWxF7vbVJzsEGQylbbWqiwmplxonZMmOCn1/rK+8L2cS00wqE OshWNda3cH9TUteLy3L2xgEzn9M1dDo2grp/k3iZF7dTCzQnvqP25zkiIYJXwI65AAbz ql6WvYpExMOfuZJ7Ft0iqhlXBLsOgMo/iel5CM6TUdfuLOf85aOHj47IcwphN1u7XKDF SViD1HgHcTjAR9NEGGObday8VCljxFldTrgd7DOAEKuofp4JcskhXAFuAsFOq58pnAs2 hrJu5WqlUB5tRwMxZT5hxMarooDMd4+ui5K2R0iYR6vdcbkCN0c+brxRYDXOIRYjlOqz tX4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+fKmruWs1pZlntzyS0MXpNQCjVub/4BvghmzxXmwOv8=; b=nKrNJ6L/Kt9hS3K2DDU+BwHGlRGInMmEpmk1eQvMYgDKKQCU9w/EGvGTNiZoRaCX7R ZGrQKprXKbaUuXXHWFiocuu1r0Cu54RgKa9QI+R+vEC91+afUNnSKlxAdTUrqbQtamen KRpUMHgW2KJPItcSJlrbO8CMwXugA2U15dV5AUBxLuTWRiH08Krhn9s1EmWDilZlTbvL lVSNK3jpAxc9q/Rk1snzn15bSHrBp9hTzTOqw8dm6gzxqmdMG/V/gMbzFcHtmFHyhojY akWnLbB7q8mHIYuAH4V9us9BrxXc/ZJcHk1wTS3f6DM8ZDIzv9726dQKeK6fOw5y0iZL 5E3Q== X-Gm-Message-State: AOAM531w6dXMJQBrQvlpNM8IhLhB4/gAV99AlvstGWkHwDF00mqdatuK iYA92OYP/2JzyxdjaEdpBfCjjT1sBsDmLeT1 X-Google-Smtp-Source: ABdhPJyHMx+SRWbU1Ocy2FmLgE7ghTRM91WBQlniGcVJbJrNptefm4DGDe5/dyDqik2xOMT2knVRSQ== X-Received: by 2002:a05:600c:3581:: with SMTP id p1mr15481777wmq.35.1619778897738; Fri, 30 Apr 2021 03:34:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Date: Fri, 30 Apr 2021 11:34:18 +0100 Message-Id: <20210430103437.4140-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Adjust the interface to match what has been done to the TCGv_i32 load/store functions. This is less obvious, because at present the only user of these functions, trans_VLDST_multiple, also wants to manipulate the endianness to speed up loading multiple bytes. Thus we retain an "internal" interface which is identical to the current gen_aa32_{ld,st}_i64 interface. The "new" interface will gain users as we remove the legacy interfaces, gen_aa32_ld64 and gen_aa32_st64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 78 +++++++++++++++++++-------------- target/arm/translate-neon.c.inc | 6 ++- 2 files changed, 49 insertions(+), 35 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e99c0ab5cb9..21b241b1ced 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, = TCGv_i32 val, tcg_temp_free(addr); } =20 +static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr =3D gen_aa32_addr(s, a32, opc); + + tcg_gen_qemu_ld_i64(val, addr, index, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr =3D gen_aa32_addr(s, a32, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + tcg_gen_rotri_i64(tmp, val, 32); + tcg_gen_qemu_st_i64(tmp, addr, index, opc); + tcg_temp_free_i64(tmp); + } else { + tcg_gen_qemu_st_i64(val, addr, index, opc); + } + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { @@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 = val, TCGv_i32 a32, gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } =20 +static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + +static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + #define DO_GEN_LD(SUFF, OPC) \ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ @@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i3= 2 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } =20 -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr =3D gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i64(val, addr, index, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { - tcg_gen_rotri_i64(val, val, 32); - } - - tcg_temp_free(addr); -} - static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data); -} - -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr =3D gen_aa32_addr(s, a32, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_rotri_i64(tmp, val, 32); - tcg_gen_qemu_st_i64(tmp, addr, index, opc); - tcg_temp_free_i64(tmp); - } else { - tcg_gen_qemu_st_i64(val, addr, index, opc); - } - tcg_temp_free(addr); + gen_aa32_ld_i64(s, val, a32, index, MO_Q); } =20 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); + gen_aa32_st_i64(s, val, a32, index, MO_Q); } =20 DO_GEN_LD(8u, MO_UB) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index c82aa1412e2..18d90421306 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg= _VLDST_multiple *a) int tt =3D a->vd + reg + spacing * xs; =20 if (a->l) { - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size= ); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size= ); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Buglink: https://bugs.launchpad.net/qemu/+bug/1905356 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 21b241b1ced..4b0dba9e778 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6520,13 +6520,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst= _rr *a) addr =3D op_addr_rr_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt, tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt + 1, tmp); =20 /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6549,13 +6549,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst= _rr *a) addr =3D op_addr_rr_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); =20 op_addr_rr_post(s, a, addr, -4); @@ -6665,13 +6665,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) addr =3D op_addr_ri_pre(s, a); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt, tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, rt2, tmp); =20 /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6704,13 +6704,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) addr =3D op_addr_ri_pre(s, a); =20 tmp =3D load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); =20 op_addr_ri_post(s, a, addr, -4); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.34.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ryF9vI2/O0RAnXW5HYdjAy7sWkmeRezyz+rPnbZz7Qg=; b=NwzDxJGIVVLmWV+v3/dKFfFfbOF6HcYjmIf1bTuHZL/za/ff+qpj36FK7R09QvLJy6 DaQvtwxwWxKdVcdT+5JHL8nJND7EPtRw48a8G85hgo3BytXULDeweC2yWH5Xfj9l7Czd pOypd6P0EuVrfb9hm34qeUkMKCMHfEUssi548+fCu0qkUuTRp2GvCudk1bpHmyzpqbd9 GNgF1V7n9U8pyX34vLA+Y1bBLr9SMmLOgE64t7NthGfBCt+RKpADDvRKgv+DjWRl7Fiv r56iSylXGWKNBHbEDC1Bae9OaV4XO5Scdi1WYCoNMjQeuLkCRze/5PR+3FNmbEnElG2N Ugig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ryF9vI2/O0RAnXW5HYdjAy7sWkmeRezyz+rPnbZz7Qg=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4b0dba9e778..f5a214e35e5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6936,7 +6936,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp= mop) addr =3D load_reg(s, a->rn); tmp =3D load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); =20 tcg_temp_free_i32(tmp); @@ -7092,7 +7092,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp= mop) =20 addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); =20 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780573; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f5a214e35e5..9095c4a86f3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7884,7 +7884,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) } else { tmp =3D load_reg(s, i); } - gen_aa32_st32(s, tmp, addr, mem_idx); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); =20 /* No need to add after the last transfer. */ @@ -7959,7 +7959,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) } =20 tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, mem_idx); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); if (user) { tmp2 =3D tcg_const_i32(i); gen_helper_set_user_reg(cpu_env, tmp2, tmp); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780836; cv=none; d=zohomail.com; s=zohoarc; b=FSJxnnHVN0kNaB93iY3qSbVycw8mVJysh8FPX8DaYG/2zGI46N6MFNZ27Tty3eiDoxFXUudc4rqYZ9POStlsDv/xa81ZaHdh4IOPRguLouNHuj5vpJZ65T/cMvA1wqRkctMHtuRPJTEFu07TSkcWt2+bgRljr6WasvWr4isulu4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9095c4a86f3..b8704d2504b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8357,10 +8357,10 @@ static bool trans_RFE(DisasContext *s, arg_RFE *a) =20 /* Load PC into tmp and CPSR into tmp2. */ t1 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t1, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_gen_addi_i32(addr, addr, 4); t2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t2, addr, get_mem_index(s), MO_UL | MO_ALIGN); =20 if (a->w) { /* Base writeback. */ --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780476; cv=none; d=zohomail.com; s=zohoarc; b=Ikyw0+5qvfKlSw2KQphLvcuwqyz/hhMk+fb4SxoDM9yx9JYYeKW5QwEVhQq00rgqNeU51FldJt7tXTj1hjQPoySZ/2UWCecSDy7bezPngntwexmsRV5FLl/XmruOtKtOg2sfwXvrjmAJhJNU+EaotTqpzs2G4jJt0MyZXmgxUHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b8704d2504b..3b071012cae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5200,11 +5200,11 @@ static void gen_srs(DisasContext *s, } tcg_gen_addi_i32(addr, addr, offset); tmp =3D load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tmp =3D load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780332; cv=none; d=zohomail.com; s=zohoarc; b=XzDSHViuBsAaG4v/VZ3nYIX4Poxh1HoOKMFm/2UVvM5Jgrk62fhTZ2Ll+dVo7eLCgKKNKISUtMJDzZy3mX/pGP5Q3YhNLr6ZJJZi7WO0M9YyNybMmy7bysinwWOwt5v33kvEoV8xBxBroFJvR0KkwBLCzp5S/s3sLw9GAv8BaaU= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rsbKj+4V5FpXcPArGe9kv1/8TdlDga2eaABwTD55lB8=; b=du1CkkyLakdGn3642gcT7578tb767NovD1+3YdFnfrw0JZF8W9N+98XxgKOxGYJ6YW uIUpS6UOLAS7QuBfMAPAyntGZOEhURpzhrW6/7ZEgE1g7L7MgAOpPsTqzgdIZZxEu3ko 12n33JvXVjl0pbyP5b8RQatu/4Owvifto/HHg2eJIisWaWl4LCekyku5to4F355eUZeY 6D/+xjuL2g4yxg9mJXDkXzJZyc1qcGvkuSqT4ylgWRQxlYqlYN8dJnHJbo9ULpL6ZATc oUK1Dts1Pj3FIamzE5vE8xvoiTOWeyw0IoUTX4Evx0WXxCu2ZtvCWCrR8BMEzIwma4RF PSUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rsbKj+4V5FpXcPArGe9kv1/8TdlDga2eaABwTD55lB8=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 10766f210c1..f50afb23e74 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1503,12 +1503,12 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg= _VLDM_VSTM_sp *a) for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALI= GN); vfp_store_reg32(tmp, a->vd + i); } else { /* store */ vfp_load_reg32(tmp, a->vd + i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALI= GN); } tcg_gen_addi_i32(addr, addr, offset); } @@ -1586,12 +1586,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg= _VLDM_VSTM_dp *a) for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIG= N_4); vfp_store_reg64(tmp, a->vd + i); } else { /* store */ vfp_load_reg64(tmp, a->vd + i); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIG= N_4); } tcg_gen_addi_i32(addr, addr, offset); } --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Vfktx2mvMGyTDBMyqJAZUhm98L0pQAwM5pYq0/74ZqY=; b=UaTISmfX9sPr3ZEGqQnqmC9I5kYwT2JNtqeL9OgW5OVmkQ9qlchTrod8WNKvFFQzlR UHFUvkBk6P9WpfbtPzglyw9R4sC/JdEGAuFTEXU9tQiSIodeyT4LyqvNkfcLC46fFoVV MdQ2Nstmkeu19hJ/3vg0280lYl5/ZuXhwGW38BuZeI46ZbepuY/yB1qc9BwpClB/6sQh mDFUn2tJFKvNsblXw21RM1U0E6p5DSW3wCVvXU2+25BEJksvoYTLn2DvpjOf4xxywoUN VuePyt0RzrhkQZX/FoNNkQ2VJtnMVaxfWuNa4F/ZE49sL+Tf5H5gzZlSRMaJ6KWqwpBD jJNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vfktx2mvMGyTDBMyqJAZUhm98L0pQAwM5pYq0/74ZqY=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index f50afb23e74..e20d9c7ba66 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1364,11 +1364,11 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg= _VLDR_VSTR_sp *a) addr =3D add_reg_for_lit(s, a->rn, offset); tmp =3D tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1398,11 +1398,11 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg= _VLDR_VSTR_sp *a) addr =3D add_reg_for_lit(s, a->rn, offset); tmp =3D tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1439,11 +1439,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg= _VLDR_VSTR_dp *a) addr =3D add_reg_for_lit(s, a->rn, offset); tmp =3D tcg_temp_new_i64(); if (a->l) { - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd); } else { vfp_load_reg64(tmp, a->vd); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); } tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780338; cv=none; d=zohomail.com; s=zohoarc; b=D1CixVXvZ3XLCTBIcdl17K972giuoUqw6D2iPmAqWrniOpg8VY9NBGkfv4gzBgmdRCPzo+7GhcY4uCp01QZM7pYwbPaTWqnAaaVQKInx5BcVyN5fN+9AJXK5qBNk/VdJ5VJkbt04TkODnssIt+ORi4EOB+rRfQq8wpu8LpV9WBY= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nQvJbV+I+IeHC4QJnyxqPSfqlbl9dQYnMWXa36K8Yjs=; b=azkBZBEYn0Jbf1/EAyDg5t5t92PEaOPTrKEKSf8kzPSON9bGYtam6vmqEIb9UszI+z LEiFsLAxtAerTiogQC88GPo5fV4sMxuhboveJ+9cLJQmPJyU2b53NTWHtgCISWJ3hr/j 6fk3pNBJefnLohM1n10mOnJyJFrEik3nhx1H6CWPBrSn5OUOki3tI5CR3rptBOZ6P+dI fVoqtQpSGxT8WnOkif1IqHdubhImq+glCX/qDZlgosz+agQR0UEuO1Dph6eHbj82KEuP HgHqbWU6QZyAZ1OmwHGnhgBuG4DXhE6ZxHfTGgnVBGEGmPF24B74rGOQNDI7WSJE3MWj JL3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nQvJbV+I+IeHC4QJnyxqPSfqlbl9dQYnMWXa36K8Yjs=; b=bU5Mp6rHsPNW4kC86PZiVAdz0VLUzL2dNavrM6S2aAtrFsZesnQg0R/pm+TF8jHRYn 6AlCNZNFF2aSaF8r1MafMqm35M5fNEz6PoVU9CCCEwR2RrC0IB8E2XsM5ksqx2i/pOlf 04J8c3WkOtpOZecWZRc6hinWRiTMPZfeNw6Yk0TnZ3OrAu/Rda8rDYdW2H/NHP0okNu1 ttGS6rVdLikBe1xQnHSctXTd5bgR28FDvBuY1tubjPCSR5WWSQ4q5xO4zSI4lJjAXSV2 hjYzrjW9cWL1a+QkrdMK1zgU9VFWx0XAkuyvmNvVFmf3QqSuR8fzPCu6muT12kWFi0Dz z3Gg== X-Gm-Message-State: AOAM5300Ccn3+/0/HeIUe3JUoayTl9xla0KgOw1EOmnSwK0NPLkfVv/0 Pff6coJPkvUmASsv24ttTkz7jqrXdl7zsGEr X-Google-Smtp-Source: ABdhPJyUVGefsVRLfFl+iA8icVqAUT58crOBHt/9eHi390Saeh8H4XRxhdoVWO9O1Soa7DHKT3hFuA== X-Received: by 2002:a5d:4707:: with SMTP id y7mr5969150wrq.137.1619778902947; Fri, 30 Apr 2021 03:35:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes) Date: Fri, 30 Apr 2021 11:34:26 +0100 Message-Id: <20210430103437.4140-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.h | 1 + target/arm/translate.c | 15 +++++++++++++ target/arm/translate-neon.c.inc | 37 +++++++++++++++++++++++++-------- 3 files changed, 44 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 0c60b83b3d4..ccf60c96d84 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,7 @@ void arm_test_cc(DisasCompare *cmp, int cc); void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); +MemOp pow2_align(unsigned i); =20 /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3b071012cae..43ff0d4b8ac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,6 +908,21 @@ static inline void store_reg_from_load(DisasContext *s= , int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif =20 +MemOp pow2_align(unsigned i) +{ + static const MemOp mop_align[] =3D { + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, + /* + * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such + * that 256-bit alignment (MO_ALIGN_32) cannot be supported: + * see get_alignment_bits(). Enforce only 128-bit alignment for no= w. + */ + MO_ALIGN_16 + }; + g_assert(i < ARRAY_SIZE(mop_align)); + return mop_align[i]; +} + /* * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 18d90421306..9c2b0760278 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -522,6 +522,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VL= D_all_lanes *a) int size =3D a->size; int nregs =3D a->n + 1; TCGv_i32 addr, tmp; + MemOp mop, align; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -532,18 +533,33 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_= VLD_all_lanes *a) return false; } =20 + align =3D 0; if (size =3D=3D 3) { if (nregs !=3D 4 || a->a =3D=3D 0) { return false; } /* For VLD4 size =3D=3D 3 a =3D=3D 1 means 32 bits at 16 byte alig= nment */ - size =3D 2; - } - if (nregs =3D=3D 1 && a->a =3D=3D 1 && size =3D=3D 0) { - return false; - } - if (nregs =3D=3D 3 && a->a =3D=3D 1) { - return false; + size =3D MO_32; + align =3D MO_ALIGN_16; + } else if (a->a) { + switch (nregs) { + case 1: + if (size =3D=3D 0) { + return false; + } + align =3D MO_ALIGN; + break; + case 2: + align =3D pow2_align(size + 1); + break; + case 3: + return false; + case 4: + align =3D pow2_align(size + 2); + break; + default: + g_assert_not_reached(); + } } =20 if (!vfp_access_check(s)) { @@ -556,12 +572,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_= VLD_all_lanes *a) */ stride =3D a->t ? 2 : 1; vec_size =3D nregs =3D=3D 1 ? stride * 8 : 8; - + mop =3D size | align; tmp =3D tcg_temp_new_i32(); addr =3D tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg =3D 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); if ((vd & 1) && vec_size =3D=3D 16) { /* * We cannot write 16 bytes at once because the @@ -577,6 +593,9 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VL= D_all_lanes *a) } tcg_gen_addi_i32(addr, addr, 1 << size); vd +=3D stride; + + /* Subsequent memory operations inherit alignment */ + mop &=3D ~MO_AMASK; } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780066; cv=none; d=zohomail.com; s=zohoarc; b=K9dy3B+NkQEPhe9MwfZz/ggVME/Hm740JHZv2AYbQnRoniI+iGOYuETJlcfduYdOApETX1cJQmub2kvpJ/dOiIg2dp4a1vVwKhxzxug9BRp2y1M/Pg+lSnSDR5csbEY2sRY8b+M2ASHhyxtx5+85cw6/BUPZuu5cRSV0rgu/Cww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619780066; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k/QNncVOfgNFtyff4VhYfFUA9Rr1T2/8onXFCTv7J8I=; b=dm7IyB0zpzxK09WSJ2J2rkVTnuRYKze8opE5oEZblnx/Mjsb1C2k3u9UD16Q6k0rR7AbA1o5+iN2mV36rec28I3echfBw/KNiTBUbQnm3DeHJ5x0Jxxpp/HneQawOLmCHzi51Y1sTmgqMvFYgDKV0cmYNH+2+BQijbZCkbovieE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619780066176735.782252325163; Fri, 30 Apr 2021 03:54:26 -0700 (PDT) Received: from localhost ([::1]:52268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcQmv-0005ks-52 for importer@patchew.org; Fri, 30 Apr 2021 06:54:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQUN-0007rj-E9 for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:17 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:45853) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQUD-0001OF-9Y for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:15 -0400 Received: by mail-wm1-x32b.google.com with SMTP id s5-20020a7bc0c50000b0290147d0c21c51so490242wmh.4 for ; Fri, 30 Apr 2021 03:35:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=k/QNncVOfgNFtyff4VhYfFUA9Rr1T2/8onXFCTv7J8I=; b=kH/1u7Kh6YjjVBmzvdggPkA5ZxDtrEq5+QVJQF7QXl9RDUORjZ493g9vDyZYR4XzFE mUAqP1+nfgsmRsdJsboZm2jPibJ96Wdfx+pVlK3ucSJpkSzarTNwbXOIPgbPjRq4x/fQ 7XyBTXV+2dsd4DRnPm/4yR/GjVVzxooOBjzH0CmMxaTE+O4q9FhAZn9fJlwbUL3t/tdA /HnKLgPiP/dlP0DeZnH3Wcm/aOex2YsNMOtVeRbERl8gmQg1up8sUe1zlkQZc2A1IH+F K0SZXUXOrwaPzhpXSi4NG+6P+0h2eaeFLILp+Bpvgjn7JzX8+xKe2ozrbhq6YNxB/Opv lQBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k/QNncVOfgNFtyff4VhYfFUA9Rr1T2/8onXFCTv7J8I=; b=iFNdXJ9k4cbdca+p0am7Zuvs47XoihsH5V11g8EkArFZ0ZuquD14Wo82CBCWW72diP l8weJ8Yk2trS8A6ZbDE80AoSteYUEvB4vdhsmej27erT4u5S/scXztj/lq8mdpXVn83R Mabme723IyjhUjEXelCcwrRWXWQB/E523F/b/DEO516LE5V5vIYUQgDIHh9ANBEixYmr BhxCtud9NwtfJF4wXhYff0l2hFh/wFf0tLuhOzXmlKkX8dm5qBIIcVRLvc57qKH8rpDi dZGIEXexdGmR2tf3M/0NSxAZTLcR5p8TqdU0WHY4uLnwxvnkJmxvY+0VoEwBIG9PUoN1 Fbrg== X-Gm-Message-State: AOAM533cac/Vm3v8fMruAKdLHU/GADsr3yvmf8KVTCeFPb8crj/h6Jz6 qje2uC+zlGRHr7j9AGuPMSl/3E6/0dSTgkBJ X-Google-Smtp-Source: ABdhPJykpCsQyXn/ZZSNe4FOx/UDilfL4xON7xszCX7xphZY3vVvvdJ2TujE+tyCLuexljQ0szHAnA== X-Received: by 2002:a1c:f708:: with SMTP id v8mr16122319wmh.133.1619778903560; Fri, 30 Apr 2021 03:35:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple) Date: Fri, 30 Apr 2021 11:34:27 +0100 Message-Id: <20210430103437.4140-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-neon.c.inc | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 9c2b0760278..e706c37c80a 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -429,7 +429,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) { /* Neon load/store multiple structures */ int nregs, interleave, spacing, reg, n; - MemOp endian =3D s->be_data; + MemOp mop, align, endian; int mmu_idx =3D get_mem_index(s); int size =3D a->size; TCGv_i64 tmp64; @@ -473,20 +473,36 @@ static bool trans_VLDST_multiple(DisasContext *s, arg= _VLDST_multiple *a) } =20 /* For our purposes, bytes are always little-endian. */ + endian =3D s->be_data; if (size =3D=3D 0) { endian =3D MO_LE; } + + /* Enforce alignment requested by the instruction */ + if (a->align) { + align =3D pow2_align(a->align + 2); /* 4 ** a->align */ + } else { + align =3D s->align_mem ? MO_ALIGN : 0; + } + /* * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ if (interleave =3D=3D 1 && endian =3D=3D MO_LE) { + /* Retain any natural alignment. */ + if (align =3D=3D MO_ALIGN) { + align =3D pow2_align(size); + } size =3D 3; } + tmp64 =3D tcg_temp_new_i64(); addr =3D tcg_temp_new_i32(); tmp =3D tcg_const_i32(1 << size); load_reg_var(s, addr, a->rn); + + mop =3D endian | size | align; for (reg =3D 0; reg < nregs; reg++) { for (n =3D 0; n < 8 >> size; n++) { int xs; @@ -494,15 +510,16 @@ static bool trans_VLDST_multiple(DisasContext *s, arg= _VLDST_multiple *a) int tt =3D a->vd + reg + spacing * xs; =20 if (a->l) { - gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, - endian | size); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, mop); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, - endian | size); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop); } tcg_gen_add_i32(addr, addr, tmp); + + /* Subsequent memory operations inherit alignment */ + mop &=3D ~MO_AMASK; } } } --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780998; cv=none; d=zohomail.com; s=zohoarc; b=eqFgiOgfzs0y6peeYALQRWldegDd4rXgoT9ZLfHlUwAKIfHp1lgMT/PUNu11pyY9xnICLiZMAfK6cdJV5Otht2Lhfph5hLQ1qykCydq8wPP8NqGQiUjREUnKVcP53tfoSsCak1HM5BtT074TlTSl+Z/esrXP4dHC4iWbX9ZR9gA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619780998; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xv8sD118HVsdOFITYFq6DC+q9hManJBUC0l6aIfLdv4=; b=co+3abqgnEB2esKeG6/YX/v9lpHRNhBPCXV2vQWLgKBEaO6XBZG3y6IB+vUwj2PY08lmn70WI3Xg5Ue+inQutB+ezprHcIpeSsYeUDvOGqpb5JFHswrjxmXzZ1p7kqcpekC0EVu9Xj1omR/zvsrRHOiXfQH4wu0jKvLwVyGLgVo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619780998429130.13582447772194; Fri, 30 Apr 2021 04:09:58 -0700 (PDT) Received: from localhost ([::1]:58090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcR1x-0003PE-Am for importer@patchew.org; Fri, 30 Apr 2021 07:09:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQUR-0007sa-DR for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:21 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:44648) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQUE-0001OP-7B for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:19 -0400 Received: by mail-wm1-x330.google.com with SMTP id 82-20020a1c01550000b0290142562ff7c9so1392575wmb.3 for ; Fri, 30 Apr 2021 03:35:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-neon.c.inc | 48 ++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index e706c37c80a..a02b8369a1d 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -629,6 +629,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) int nregs =3D a->n + 1; int vd =3D a->vd; TCGv_i32 addr, tmp; + MemOp mop; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -678,23 +679,58 @@ static bool trans_VLDST_single(DisasContext *s, arg_V= LDST_single *a) return true; } =20 + /* Pick up SCTLR settings */ + mop =3D finalize_memop(s, a->size); + + if (a->align) { + MemOp align_op; + + switch (nregs) { + case 1: + /* For VLD1, use natural alignment. */ + align_op =3D MO_ALIGN; + break; + case 2: + /* For VLD2, use double alignment. */ + align_op =3D pow2_align(a->size + 1); + break; + case 4: + if (a->size =3D=3D MO_32) { + /* + * For VLD4.32, align =3D 1 is double alignment, align =3D= 2 is + * quad alignment; align =3D 3 is rejected above. + */ + align_op =3D pow2_align(a->size + a->align); + } else { + /* For VLD4.8 and VLD.16, we want quad alignment. */ + align_op =3D pow2_align(a->size + 2); + } + break; + default: + /* For VLD3, the alignment field is zero and rejected above. */ + g_assert_not_reached(); + } + + mop =3D (mop & ~MO_AMASK) | align_op; + } + tmp =3D tcg_temp_new_i32(); addr =3D tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); - /* - * TODO: if we implemented alignment exceptions, we should check - * addr against the alignment encoded in a->align here. - */ + for (reg =3D 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); + gen_aa32_ld_internal_i32(s, tmp, addr, get_mem_index(s), mop); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); + gen_aa32_st_internal_i32(s, tmp, addr, get_mem_index(s), mop); } vd +=3D a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); + + /* Subsequent memory operations inherit alignment */ + mop &=3D ~MO_AMASK; } tcg_temp_free_i32(addr); tcg_temp_free_i32(tmp); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6XTX/ivISDuqZQtLc7u0559fCih8oM9emc0tB4mriTY=; b=RIA50XW9EndQOZcZppiCCoPzSrAyX+PuDQEDUvyBoZOcf7DSkExJN7gUHMqkkmH5HZ qDXYmXSMm8i8BPSF3N3J5PvYVVY/gV0nWMUu4hVYiqm1JoGHoVwAraPdDziMEbEkXilu U7NjYkxtekWtTHspZe/Lnb4q1QzqxwzKJD0M3jhYHc+yNDtXxsfi5ve6Hze4bGP97fkj CxEQR4JpnqoHxWTsUJmdndwbQzxPXUIz256Ix67GG5XUJN54O1a/4qUSx2V1mZ/r+BY7 +rAsDdoGB3EhNZGOCe0IyJ5TCWoUbEWanIuXdgNdqxc6wAFKKDkCk2x+2uHVWKizoW/n hUNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6XTX/ivISDuqZQtLc7u0559fCih8oM9emc0tB4mriTY=; b=oFUCyq3DMjTGXr0OMCSTfD6pvZNiIkpQsQeBxAV7GkWwoFG9ykE2MGdYD6UWf/79Ir 9eElviGDijjOY+2r/exFJBOyYb0sQAIsBRa5mvEtnHnh9B364RktCL1Uf3Z5JUIbb9UI YSU5wiwX/ufVRbcznK7h11JIGZfwHSKDEaXqZ97HBvNuKatmBffxBJZOTRDUod0YeK/0 d70JeZDGswcYNiLlMPaKyNXs9GTSs9mF+VwigFd8mfLDI6BlP8Iy0Oqj65da9v8QJdDH L8IfXwiKCn/XtYtt5vItjBRQ67CfvJ9aCkYyg4sGTgR/I9HMmlHAbJzQ41u4uFTpK3Iw dqZg== X-Gm-Message-State: AOAM5323nlHkTwheOUNQMsATXZJIgyOOG/QOAnnC/OwiC2IhyNrUxMDA 8EkYUZb17HTLHa2J8sVuYl/ay4NuFk/4nYNB X-Google-Smtp-Source: ABdhPJx0Ya1Nka+6O9YcGrW/+mTqwKsS8ltmQyVZsC62r5sPiCdS1z1CPQM6wq9FHhneMLFDLhYb3g== X-Received: by 2002:adf:f241:: with SMTP id b1mr2378596wrp.150.1619778905007; Fri, 30 Apr 2021 03:35:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store Date: Fri, 30 Apr 2021 11:34:29 +0100 Message-Id: <20210430103437.4140-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson In the case of gpr load, merge the size and is_signed arguments; otherwise, simply convert size to memop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 78 ++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 45 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 92a62b1a751..f2995d2b74d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -886,19 +886,19 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i6= 4 t0, TCGv_i64 t1) * Store from GPR register to memory. */ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, - TCGv_i64 tcg_addr, int size, int memidx, + TCGv_i64 tcg_addr, MemOp memop, int memidx, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - g_assert(size <=3D 3); - tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); + memop =3D finalize_memop(s, memop); + tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop); =20 if (iss_valid) { uint32_t syn; =20 syn =3D syn_data_abort_with_iss(0, - size, + (memop & MO_SIZE), false, iss_srt, iss_sf, @@ -909,37 +909,28 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i6= 4 source, } =20 static void do_gpr_st(DisasContext *s, TCGv_i64 source, - TCGv_i64 tcg_addr, int size, + TCGv_i64 tcg_addr, MemOp memop, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), + do_gpr_st_memidx(s, source, tcg_addr, memop, get_mem_index(s), iss_valid, iss_srt, iss_sf, iss_ar); } =20 /* * Load from memory to GPR register */ -static void do_gpr_ld_memidx(DisasContext *s, - TCGv_i64 dest, TCGv_i64 tcg_addr, - int size, bool is_signed, - bool extend, int memidx, +static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_= addr, + MemOp memop, bool extend, int memidx, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - MemOp memop =3D s->be_data + size; - - g_assert(size <=3D 3); - - if (is_signed) { - memop +=3D MO_SIGN; - } - + memop =3D finalize_memop(s, memop); tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); =20 - if (extend && is_signed) { - g_assert(size < 3); + if (extend && (memop & MO_SIGN)) { + g_assert((memop & MO_SIZE) <=3D MO_32); tcg_gen_ext32u_i64(dest, dest); } =20 @@ -947,8 +938,8 @@ static void do_gpr_ld_memidx(DisasContext *s, uint32_t syn; =20 syn =3D syn_data_abort_with_iss(0, - size, - is_signed, + (memop & MO_SIZE), + (memop & MO_SIGN) !=3D 0, iss_srt, iss_sf, iss_ar, @@ -957,14 +948,12 @@ static void do_gpr_ld_memidx(DisasContext *s, } } =20 -static void do_gpr_ld(DisasContext *s, - TCGv_i64 dest, TCGv_i64 tcg_addr, - int size, bool is_signed, bool extend, +static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, + MemOp memop, bool extend, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, - get_mem_index(s), + do_gpr_ld_memidx(s, dest, tcg_addr, memop, extend, get_mem_index(s), iss_valid, iss_srt, iss_sf, iss_ar); } =20 @@ -2717,7 +2706,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) } clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2830,8 +2819,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; =20 - do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + false, true, rt, iss_sf, false); } tcg_temp_free_i64(clean_addr); } @@ -2989,11 +2978,11 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) /* Do not modify tcg_rt before recognizing any exception * from the second load. */ - do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, - false, 0, false, false); + do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN, + false, false, 0, false, false); tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, - false, 0, false, false); + do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN, + false, false, 0, false, false); =20 tcg_gen_mov_i64(tcg_rt, tmp); tcg_temp_free_i64(tmp); @@ -3124,8 +3113,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, - is_signed, is_extended, memidx, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_= SIGN, + is_extended, memidx, iss_valid, rt, iss_sf, false); } } @@ -3229,9 +3218,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size, - is_signed, is_extended, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, true, rt, iss_sf, false); } } } @@ -3314,8 +3302,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, true, rt, iss_sf, false); } } } @@ -3402,7 +3390,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, * full load-acquire (we only need "load-acquire processor consist= ent"), * but we choose to implement them as full LDAQ. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3475,7 +3463,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, is_wback || rn !=3D 31, size); =20 tcg_rt =3D cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, + do_gpr_ld(s, tcg_rt, clean_addr, size, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); =20 @@ -3560,8 +3548,8 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) * Load-AcquirePC semantics; we implement as the slightly more * restrictive Load-Acquire. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, - true, rt, iss_sf, true); + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIG= N, + extend, true, rt, iss_sf, true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } } --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pE35k+HSXb8cWECR+1jQBqhx6b1poxCQLSIjdyuQBlk=; b=tkAxEKhrVHdSrByfhKlXiaxjhW1yBIA0LGlvOLZRJ772XesLwJSQycudUJqlJIVqYk 48y1UirpQrafW6eYacZFjtyxacKJbE65EWXPaahR6Auk/bOwca4iNJ69SzJuE9cGjGt8 osm7ZAPGi+RMv1l/cIV8BrOlTv0PEThFFWu5wNWopTubodHI5oiFwRcZNTV5+g2bzn/I nayUESwOUdYR+f2anj/EPTj7hQvpfhkrMkWqlYPZzCX/J9d3qKXjZUKkPfQ/qqDPsdy8 LzDb3OZ0bHgwozM0+Dvq2DqAzvYZ8dhe9PMpuYuf8BrcukYslMJRj9sYmb/FTYyRDiAd bbwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pE35k+HSXb8cWECR+1jQBqhx6b1poxCQLSIjdyuQBlk=; b=LQstxGkI92jcsunvTf8eitltRkexZ+yNvYoJLvoSfbQWjphM/+WxmtpRiy+mIVt2K5 lZUUaU7pvhi1cuI4SvQ+7SZbXeWVLM4jKaIzWZa8K5A8hz+VKG52wX6XrNCchqWxZgha Od2DNR6wEV2avYvLeIhiFicVN6QObgoG5isB8dnJWh/eFXvEEqIOTjR45a6+bTZkgdYY VwLnQWDOiVp0opZsjkpsriW7HfKQgimKQelY2dpVK0TQpaLFcqM9yidTNjNRXtjdKx7j C5j23LMHYDm8qUwu0rbiONvOGje6dLMFC1VfMylFYfxmKKqDZHkJ7xEGdsy19f++w3RR p1Zw== X-Gm-Message-State: AOAM530kqPN5E8hF+DJJAYmHXwgSZg81A6hG9xLuN60Wgi7vm6JjnLXi Ee+lbmcM9QaArnL6rKuiLPAxWnBrooCO3myc X-Google-Smtp-Source: ABdhPJzuF7DiZ1pMhWMnmPonRygrMrRm1dVwrSG7cqIu7GWoHBaf+JMHLbqmu31AXhh2IMkjCMMCZQ== X-Received: by 2002:a5d:4c87:: with SMTP id z7mr6010135wrs.144.1619778905601; Fri, 30 Apr 2021 03:35:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store Date: Fri, 30 Apr 2021 11:34:30 +0100 Message-Id: <20210430103437.4140-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson For 128-bit load/store, use 16-byte alignment. This requires that we perform the two operations in the correct order so that we generate the alignment fault before modifying memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f2995d2b74d..b90d6880e78 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -963,25 +963,33 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest,= TCGv_i64 tcg_addr, static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int s= ize) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ - TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + TCGv_i64 tmplo =3D tcg_temp_new_i64(); + MemOp mop; + + tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + if (size < 4) { - tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), - s->be_data + size); + mop =3D finalize_memop(s, size); + tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { bool be =3D s->be_data =3D=3D MO_BE; TCGv_i64 tcg_hiaddr =3D tcg_temp_new_i64(); + TCGv_i64 tmphi =3D tcg_temp_new_i64(); =20 + tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); + + mop =3D s->be_data | MO_Q; + tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), + mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index= (s), - s->be_data | MO_Q); - tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); - tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index= (s), - s->be_data | MO_Q); + tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr, + get_mem_index(s), mop); + tcg_temp_free_i64(tcg_hiaddr); + tcg_temp_free_i64(tmphi); } =20 - tcg_temp_free_i64(tmp); + tcg_temp_free_i64(tmplo); } =20 /* @@ -992,10 +1000,11 @@ static void do_fp_ld(DisasContext *s, int destidx, T= CGv_i64 tcg_addr, int size) /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D NULL; + MemOp mop; =20 if (size < 4) { - MemOp memop =3D s->be_data + size; - tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); + mop =3D finalize_memop(s, size); + tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { bool be =3D s->be_data =3D=3D MO_BE; TCGv_i64 tcg_hiaddr; @@ -1003,11 +1012,12 @@ static void do_fp_ld(DisasContext *s, int destidx, = TCGv_i64 tcg_addr, int size) tmphi =3D tcg_temp_new_i64(); tcg_hiaddr =3D tcg_temp_new_i64(); =20 + mop =3D s->be_data | MO_Q; + tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), + mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_ind= ex(s), - s->be_data | MO_Q); - tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_ind= ex(s), - s->be_data | MO_Q); + tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr, + get_mem_index(s), mop); tcg_temp_free_i64(tcg_hiaddr); } =20 --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619781008; cv=none; d=zohomail.com; s=zohoarc; b=TKBFteT1i1AxnjoKdd7rbVG+CiW7xkO/yZAZgAUfm2x8PjhlUDH/1TbjlJ8FmGL4bPExQ+TQh9emzzuP5//5avQBvhDWGreOkpYcKsZPiiyAukugUvJ2Z4lSp1hUJbdcIaQLmKHWIcQ1+qgNTJkWBJXbvXwhQk4/ydaAWN+r/DE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619781008; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Bf/imavd9eUjfb3z2UO3I9eaVsDiw1wTDTip+/KNxIU=; b=C+JaoLCetXBiJcvN7xUN3I4Jx7hc4CsJDkbwy5GLiRWJiANkj0XBB5l2qE8gt5Zsar+XoxjwcwLVUDCa5mDWMAlD+NxL8yyKeat0UTbzGb//XB9ud1U2s1aR8LaWO8OXoO3HJ5hBnK1y7dzr05MH6/y9nsLw2ictd3ZOoZi8HGE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161978100819727.616034682978807; Fri, 30 Apr 2021 04:10:08 -0700 (PDT) Received: from localhost ([::1]:58506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcR26-0003aF-Ep for importer@patchew.org; Fri, 30 Apr 2021 07:10:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQUX-0007wj-Oh for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:25 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQUF-0001Oh-NL for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:25 -0400 Received: by mail-wr1-x436.google.com with SMTP id l2so17690174wrm.9 for ; Fri, 30 Apr 2021 03:35:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b90d6880e78..ac60dcf7602 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2699,7 +2699,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, size); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2716,8 +2717,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) } clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, t= rue, + rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; =20 @@ -3505,15 +3507,18 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; bool is_store =3D false; - bool is_signed =3D false; bool extend =3D false; bool iss_sf; + MemOp mop; =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { unallocated_encoding(s); return; } =20 + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + mop =3D size | MO_ALIGN; + switch (opc) { case 0: /* STLURB */ is_store =3D true; @@ -3525,21 +3530,21 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) unallocated_encoding(s); return; } - is_signed =3D true; + mop |=3D MO_SIGN; break; case 3: /* LDAPURS* 32-bit variant */ if (size > 1) { unallocated_encoding(s); return; } - is_signed =3D true; + mop |=3D MO_SIGN; extend =3D true; /* zero-extend 32->64 after signed load */ break; default: g_assert_not_reached(); } =20 - iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + iss_sf =3D disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) !=3D 0, opc= ); =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); @@ -3552,13 +3557,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) if (is_store) { /* Store-Release semantics */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, t= rue); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, tr= ue); } else { /* * Load-AcquirePC semantics; we implement as the slightly more * restrictive Load-Acquire. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIG= N, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, extend, true, rt, iss_sf, true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619781333; cv=none; d=zohomail.com; s=zohoarc; b=BW3ebw72lF97GQvgMJTblr0RC0qLJTZVq9nKugPdq3sp9QMDgZ2PuVni1hzFvoiBeTZTmdf5byiuJZhDiatQ+bx/ecz6QH8OYCgzDnueRysyNwGe0d2wR602ymDby3NeZjQbiFCHgy24Mvqt51srPj4Lu7+2rnI8IALDFP45F2E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ac60dcf7602..d3bda16ecd8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1146,24 +1146,24 @@ static void write_vec_element_i32(DisasContext *s, = TCGv_i32 tcg_src, =20 /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, - TCGv_i64 tcg_addr, int size, MemOp endian) + TCGv_i64 tcg_addr, MemOp mop) { TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 - read_vec_element(s, tcg_tmp, srcidx, element, size); - tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size= ); + read_vec_element(s, tcg_tmp, srcidx, element, mop & MO_SIZE); + tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); =20 tcg_temp_free_i64(tcg_tmp); } =20 /* Load from memory to vector register */ static void do_vec_ld(DisasContext *s, int destidx, int element, - TCGv_i64 tcg_addr, int size, MemOp endian) + TCGv_i64 tcg_addr, MemOp mop) { TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size= ); - write_vec_element(s, tcg_tmp, destidx, element, size); + tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); + write_vec_element(s, tcg_tmp, destidx, element, mop & MO_SIZE); =20 tcg_temp_free_i64(tcg_tmp); } @@ -3734,9 +3734,9 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) for (xs =3D 0; xs < selem; xs++) { int tt =3D (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, clean_addr, size, endian); + do_vec_st(s, tt, e, clean_addr, size | endian); } else { - do_vec_ld(s, tt, e, clean_addr, size, endian); + do_vec_ld(s, tt, e, clean_addr, size | endian); } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } @@ -3885,9 +3885,9 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); + do_vec_ld(s, rt, index, clean_addr, scale | s->be_data); } else { - do_vec_st(s, rt, index, clean_addr, scale, s->be_data); + do_vec_st(s, rt, index, clean_addr, scale | s->be_data); } } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GWTmkHcg1lj0lJMlmsVGKQ2xkh2uHeIaya8Gpbk3GKs=; b=EReAoqZC6lt8CJHRuUUf1NWo/TYjIe9zvTxtqHhkh+vvxIKvcdUNS6au/wfoRGX4Dk ApbD/c06VoGQFVDcNjLNqGk9DtatDK2Mx5myFUmrnpBi5rPOe+tlD2J2SEQR0iT6D5QI tIPtIYyr/lHctdb7FUP3xEf6c48sIqVdf9bGBeph4NTrMLmEx1zcG/VUF8RhFYvbS5nD vcGcAyahv3Ayqc88CalIyTCCpb9KOxW1+zJ88qIHKoxx7QGJSfl/CaZHf9IDiUPfVs6F 9S+2gxQah2FrNGz8hslZ/ib8B73jXz+vigFoTJXCLthLbSNnPbn3PormiikM9dvFESnf OthA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GWTmkHcg1lj0lJMlmsVGKQ2xkh2uHeIaya8Gpbk3GKs=; b=uUIlcpuWVihNbPDICqb7DXauChg8QWx+eUXXAoUIxsaoUZ5ScZBs0OxvXu6gfW1q3c WeLkDXBCT1J9WRFdu2EWC8IIZPUYinh6BU8C+jL2Tkz+gBT/+deyXIARG9pG8AxbSf8y wrX5QU1P/XNIe7eK/wOf9eZWLt4vjFcu9H59Y673inN+ajgHsTuxJNnbG3kpik6VG02G 14AEqALW8Fe6sYzDLg15IPnBEr06YCFc3/Ho1TMmfiqH5AfEkCXA1CyLema9Ou7l2fCN EplYCrG9K/hx+S2jrCXGUiDFcJI3fak6b55JdjIXFe10xgitU5/XADl5KTVz7cyPg53Z S5jg== X-Gm-Message-State: AOAM530eghiMQ87fXJATf3U1gUPWmdyB1Qs25x/Ska/FA7XnGKHiGAWN 4ydZwj7ap14h+QU0Rt7hqZ8ulYA8KKzCOVSC X-Google-Smtp-Source: ABdhPJzxHkBWe6gaUdRLEdAGwIw1wWH/3Atcfh4wKmu8xd0ByAS3Tzx1RlFxMzBvhWarCMPZ0llHlg== X-Received: by 2002:adf:f6c5:: with SMTP id y5mr6012652wrp.121.1619778907488; Fri, 30 Apr 2021 03:35:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Date: Fri, 30 Apr 2021 11:34:33 +0100 Message-Id: <20210430103437.4140-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3bda16ecd8..2a82dbbd6d4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3635,7 +3635,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) bool is_postidx =3D extract32(insn, 23, 1); bool is_q =3D extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; - MemOp endian =3D s->be_data; + MemOp endian, align, mop; =20 int total; /* total bytes */ int elements; /* elements per vector */ @@ -3703,6 +3703,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) } =20 /* For our purposes, bytes are always little-endian. */ + endian =3D s->be_data; if (size =3D=3D 0) { endian =3D MO_LE; } @@ -3721,11 +3722,17 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ + align =3D MO_ALIGN; if (selem =3D=3D 1 && endian =3D=3D MO_LE) { + align =3D pow2_align(size); size =3D 3; } - elements =3D (is_q ? 16 : 8) >> size; + if (!s->align_mem) { + align =3D 0; + } + mop =3D endian | size | align; =20 + elements =3D (is_q ? 16 : 8) >> size; tcg_ebytes =3D tcg_const_i64(1 << size); for (r =3D 0; r < rpt; r++) { int e; @@ -3734,9 +3741,9 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) for (xs =3D 0; xs < selem; xs++) { int tt =3D (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, clean_addr, size | endian); + do_vec_st(s, tt, e, clean_addr, mop); } else { - do_vec_ld(s, tt, e, clean_addr, size | endian); + do_vec_ld(s, tt, e, clean_addr, mop); } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619781145; cv=none; d=zohomail.com; s=zohoarc; b=SPMmuV1iMnlLsDh8K8zXjD93Qf0bsM/BWXHDo0KAlZwZ7L3kXE8NgMRx+RVwnjQs4Kd6rJoM9yqn8qWbpzl2vRfNRZUaECmJA0Gy5Y5P/nOVm3CqUzqezioeXBMJhwxVI+8JLZR7q0+Z8HeU9XkqQDxCK2kOPDOE++I4gqg4oSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619781145; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CMIwZrwBPChwnGRRggA6LqI9YdKQxFLgyoTpze9RWRA=; b=IEpCD3VY29wVM17DaBjbq7UpMWdhh1Srg0b4ta4Ot1s5oY7lxa+bgirfJBw81hyq3bA2n0kuQ77tMQPqSGne2ez0/xd7nW91kAS2M6qy5tH9U/pz6RuvhCDPKoLff58HuB/swKsXFv8rQtFExEpE4guc+PDZpHBe8RtCN1hYU08= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619781145271180.89164206879025; Fri, 30 Apr 2021 04:12:25 -0700 (PDT) Received: from localhost ([::1]:38498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcR4K-0007C2-4j for importer@patchew.org; Fri, 30 Apr 2021 07:12:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcQUW-0007v2-NH for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:24 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36468) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcQUH-0001Q5-OV for qemu-devel@nongnu.org; Fri, 30 Apr 2021 06:35:23 -0400 Received: by mail-wm1-x331.google.com with SMTP id f15-20020a05600c4e8fb029013f5599b8a9so1457958wmq.1 for ; Fri, 30 Apr 2021 03:35:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2a82dbbd6d4..95897e63af0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3815,6 +3815,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) int index =3D is_q << 3 | S << 2 | size; int xs, total; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; =20 if (extract32(insn, 31, 1)) { unallocated_encoding(s); @@ -3876,6 +3877,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) =20 clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, total); + mop =3D finalize_memop(s, scale); =20 tcg_ebytes =3D tcg_const_i64(1 << scale); for (xs =3D 0; xs < selem; xs++) { @@ -3883,8 +3885,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) /* Load and replicate to all elements */ TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, - get_mem_index(s), s->be_data + scale); + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop= ); tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), (is_q + 1) * 8, vec_full_reg_size(s), tcg_tmp); @@ -3892,9 +3893,9 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, clean_addr, scale | s->be_data); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=l5ZhQNfFgRjC4VV5SPAD8p8zlfBLoisPfhThQKIBK/g=; b=ix/STAkg6e0PqMYVDFNMjvGOtuWymQBuinatoRTovzAI13Rjxy/NNBVAOYv4HAERdE 7ViGaZSTp3kkttlBvg0GsRll//6lKyssbyMfObVYGNgg7cPvqFOdAvWqeCBZlj5ceVBD Fgtqey3WWjr4SIfdrQl5pv/jhQCszHu4awMFpdtpF48GcxvZel5Be6CNhcMAzEizBm1k 8jeZkY8X4dM2GQfnYVb/DjjJSIM6dnYjQz9NBg7UXOumuHCKZL1MFGZKEWQFrWKmk7li CcO2T72B3Fj2WBgyg8tgoJiGedrRvLEXWJ6kBVkGsu07I8XtiXSAd5434i3bm2mTDeFv kn4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l5ZhQNfFgRjC4VV5SPAD8p8zlfBLoisPfhThQKIBK/g=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210419202257.161730-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 584c4d047c8..864ed669c44 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5001,7 +5001,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) clean_addr =3D gen_mte_check1(s, temp, false, true, msz); =20 tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), - s->be_data | dtype_mop[a->dtype]); + finalize_memop(s, dtype_mop[a->dtype])); =20 /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619780840; cv=none; d=zohomail.com; s=zohoarc; b=RrlgTEXcy4bOjBTu0ydmA2ntT0dbN73hPouFm6T0+nud9rupxa+KNKj+0RK1boT5VuN6hIHrsA1jWacB0FNKQ0Q/e/0XGFvdMqNX6husRYnjfezAS2bIDPQAOW3mcpy3HPQxivnUoohoTVgHVHFLSvqB70C9/hWtiCcGCsQU+bg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619780840; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gcENlcUoIW2DXr+RXZyS/ON8OhNCnCdIA9S9X9dh+SY=; b=G/KtIf0dSrYLEJfhwBkQN3t9hkjVBOfYwrxetK+DrdJuap/S9iUf/qavL55pXODzgB hE0wbhpmmpNZ8K9DwDdnjPRl+9PLGBzwZ8qs/8dymlzoHChCm2S4O15uTIaGQ7w2b+Dq a2GmqBoHdOYUTbr6slKhptMK5w7A2oyqB4mMi2BRPpt1kgTghkJyDsYMFNOSgfsJVIYk dyt7QRh+XKxuBH6A9i80ntOcH7L4omBFabKHKjJZ92+1GBrr+PLo25M+thfNdrLOk544 +tzTbrO3S3ba+MD/qH5GyAdRbnToDt/eoa3SZkPOGCdkbMVHY690G3nzypsVXgk6JGAG QS9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gcENlcUoIW2DXr+RXZyS/ON8OhNCnCdIA9S9X9dh+SY=; b=D/wjYWikKYonvhU4V+CIV3Vk3U5qcEYtbLej8QGRPqZbNQAYO/AcKa8izseoNek/xA HFzMYy/DN26VAgFbp18icU/eYVW6gs/uCez6FkPauivcWEpxphUT2d4prYN5cFLvMa7+ qtBsyxvZXJM9ZyHy8l2u4FUftRKSe9HS6eHGGVw9twQKmPuEmLSmkSb8OBMVPKHIaYKw 2whSUQAKTQvoZZBh92skRkuQoMPheznpI8Tkfl6srzwkdPz0E++TqO1KS/VhGhc7kjHZ Mr/1nk1iIxcPhj/ObkQTsQ7YfUE2B3aSivAoP+MpBDeo8vkGcwtNkSG8nyEXR5bTw6io qv2A== X-Gm-Message-State: AOAM530DGHsvwqLOVw/x4/oYIT/sijS7tRhpmJbK1y9+0pK1nsFLsWfW RbfA7HHmiyJpssSox/qzhjfeF+DCt6lpkFZq X-Google-Smtp-Source: ABdhPJzz9MK6YEwcargc2EkfRzLm9kDPcSbJmADlFkaunwDYn0KCa/vTuulTOLz+y2vZeKgSq/maVw== X-Received: by 2002:a1c:7402:: with SMTP id p2mr15865061wmc.88.1619778909450; Fri, 30 Apr 2021 03:35:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/43] hw: add compat machines for 6.1 Date: Fri, 30 Apr 2021 11:34:36 +0100 Message-Id: <20210430103437.4140-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Add 6.1 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Cornelia Huck Acked-by: Greg Kurz Message-id: 20210331111900.118274-1-cohuck@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ hw/arm/virt.c | 7 ++++++- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 14 +++++++++++++- hw/i386/pc_q35.c | 13 ++++++++++++- hw/ppc/spapr.c | 17 ++++++++++++++--- hw/s390x/s390-virtio-ccw.c | 14 +++++++++++++- 9 files changed, 70 insertions(+), 7 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index ad6c8fd5376..3d55d2bd62c 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -353,6 +353,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) =20 +extern GlobalProperty hw_compat_6_0[]; +extern const size_t hw_compat_6_0_len; + extern GlobalProperty hw_compat_5_2[]; extern const size_t hw_compat_5_2_len; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index dcf060b7918..1522a3359a9 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -197,6 +197,9 @@ bool pc_system_ovmf_table_find(const char *entry, uint8= _t **data, void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); =20 +extern GlobalProperty pc_compat_6_0[]; +extern const size_t pc_compat_6_0_len; + extern GlobalProperty pc_compat_5_2[]; extern const size_t pc_compat_5_2_len; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9f01d9041b6..fee696fb0e3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2757,10 +2757,15 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 +static void virt_machine_6_1_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(6, 1) + static void virt_machine_6_0_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) +DEFINE_VIRT_MACHINE(6, 0) =20 static void virt_machine_5_2_options(MachineClass *mc) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 40def78183a..cebcdcc3511 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -36,6 +36,9 @@ #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" =20 +GlobalProperty hw_compat_6_0[] =3D {}; +const size_t hw_compat_6_0_len =3D G_N_ELEMENTS(hw_compat_6_0); + GlobalProperty hw_compat_5_2[] =3D { { "ICH9-LPC", "smm-compat", "on"}, { "PIIX4_PM", "smm-compat", "on"}, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8a84b25a031..364816efc9d 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -96,6 +96,9 @@ #include "trace.h" #include CONFIG_DEVICES =20 +GlobalProperty pc_compat_6_0[] =3D {}; +const size_t pc_compat_6_0_len =3D G_N_ELEMENTS(pc_compat_6_0); + GlobalProperty pc_compat_5_2[] =3D { { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, }; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 46cc951073b..4e8edffeaf6 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -415,7 +415,7 @@ static void pc_i440fx_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); } =20 -static void pc_i440fx_6_0_machine_options(MachineClass *m) +static void pc_i440fx_6_1_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_machine_options(m); @@ -424,6 +424,18 @@ static void pc_i440fx_6_0_machine_options(MachineClass= *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_I440FX_MACHINE(v6_1, "pc-i440fx-6.1", NULL, + pc_i440fx_6_1_machine_options); + +static void pc_i440fx_6_0_machine_options(MachineClass *m) +{ + pc_i440fx_6_1_machine_options(m); + m->alias =3D NULL; + m->is_default =3D false; + compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); + compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); +} + DEFINE_I440FX_MACHINE(v6_0, "pc-i440fx-6.0", NULL, pc_i440fx_6_0_machine_options); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 53450190f54..458ed41c65d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -345,7 +345,7 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus =3D 288; } =20 -static void pc_q35_6_0_machine_options(MachineClass *m) +static void pc_q35_6_1_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_machine_options(m); @@ -353,6 +353,17 @@ static void pc_q35_6_0_machine_options(MachineClass *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, + pc_q35_6_1_machine_options); + +static void pc_q35_6_0_machine_options(MachineClass *m) +{ + pc_q35_6_1_machine_options(m); + m->alias =3D NULL; + compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); + compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); +} + DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, pc_q35_6_0_machine_options); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e4be00b732a..529ff056dd2 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4605,14 +4605,25 @@ static void spapr_machine_latest_class_options(Mach= ineClass *mc) type_init(spapr_machine_register_##suffix) =20 /* - * pseries-6.0 + * pseries-6.1 */ -static void spapr_machine_6_0_class_options(MachineClass *mc) +static void spapr_machine_6_1_class_options(MachineClass *mc) { /* Defaults for the latest behaviour inherited from the base class */ } =20 -DEFINE_SPAPR_MACHINE(6_0, "6.0", true); +DEFINE_SPAPR_MACHINE(6_1, "6.1", true); + +/* + * pseries-6.0 + */ +static void spapr_machine_6_0_class_options(MachineClass *mc) +{ + spapr_machine_6_1_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); +} + +DEFINE_SPAPR_MACHINE(6_0, "6.0", false); =20 /* * pseries-5.2 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 2972b607f36..56b52d2d309 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -795,14 +795,26 @@ bool css_migration_enabled(void) } = \ type_init(ccw_machine_register_##suffix) =20 +static void ccw_machine_6_1_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_6_1_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE(6_1, "6.1", true); + static void ccw_machine_6_0_instance_options(MachineState *machine) { + ccw_machine_6_1_instance_options(machine); } =20 static void ccw_machine_6_0_class_options(MachineClass *mc) { + ccw_machine_6_1_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); } -DEFINE_CCW_MACHINE(6_0, "6.0", true); +DEFINE_CCW_MACHINE(6_0, "6.0", false); =20 static void ccw_machine_5_2_instance_options(MachineState *machine) { --=20 2.20.1 From nobody Tue May 21 10:45:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619781178; cv=none; d=zohomail.com; s=zohoarc; b=DFX9TUHSu5eEGSQkSIZJvRdDrqAt8R3kJLAgaMXSE4di4vngQAviyIDzuj2Fwp4vnZVE9rQe4ST7jrBeEKXB5/KY52FrV1dxFEDtVTmeo39xSdvRW2KwTULv+vBdH/OhrdvFLRwFgL+yeomPxUZgYDhX3xyO5aBlEv1cTZZYxVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619781178; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 18sm12997817wmo.47.2021.04.30.03.35.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 03:35:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sdqS0yyWxOc4e8zr39heD6oB/Twh6FeMcv9FfbnuPVY=; b=W8pSxENSFL7sZyrHOTdLmdObzjMpk4jpsQPZc8lxO34xFm63a+QUFP+BJI0yJQU5gd XUXhYQrFmM68I37eXa5RcTL3JB9T0RCcL+tt4j5zfrEcaCNK7e/ir06voGFovmTcw91j YLG9NWCyUANni5fuvF+swc454duBAPHhvyrO0QjSJki75QpakH49q7bL5jsktHwMKzFA Lc8vgjnjxU4ppXvbkTdRlAaN2m9DYtaGy54WAalH2V+rNiyDikwB9nQaxQgWwgNe25y+ SR1cnzGdYhdG6jrsTi5nWMnGF6KKRbWr63xPUiBodLmcWzbOo6yNZPJt85+eCC7GIRF6 4Rlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sdqS0yyWxOc4e8zr39heD6oB/Twh6FeMcv9FfbnuPVY=; b=OfDk9ewE2zeviDHzE1w8mIo/z1h44K6FeS6ZtZGTu+/ERGKhCSACw/fHkFpqem79Mq NEf/fIC8WCkzc3CuFsVadjwhvJ83RlN4IsuA+y4pjpIFD4I+Tcob3KXBp+Bt5D9XH9EP IW1+jOVS8LU7vZC+NDO3YiJBVrOA14LMQuS8QBq1STs8fpuikLVOanr/hvD4AcYICWRy 0KP2yxynPX1Pb/Ul0EtKLjjunT/ISEgVHmnRZU7RMP3arPYocSfgRSV7nE5caYmR4mUG s8zcQZ/v20UAl3l+cf1qS9ODxKCvjHSLCqmBxRzXyH8t1Nze8GYwjr0qe4wpozcIStjl WHfg== X-Gm-Message-State: AOAM533Rcbl4AxYXzgTM2CaHXFHx1ebwqtXyxttwthKeoCCVrcGa7QuZ dACfMKhmqlMtRyJuEajE+MGEEbjvT2FoNaT5 X-Google-Smtp-Source: ABdhPJw+/YGZ6stgUlDNjfZHmdWF5HT7s9pQ6/fJWVIPyQqGR2Gjk7k62RHSND7kE/lmgdwCkpi3Ag== X-Received: by 2002:a1c:7e45:: with SMTP id z66mr5341299wmc.126.1619778910160; Fri, 30 Apr 2021 03:35:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows Date: Fri, 30 Apr 2021 11:34:37 +0100 Message-Id: <20210430103437.4140-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org> References: <20210430103437.4140-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently the gpex PCI controller implements no special behaviour for guest accesses to areas of the PIO and MMIO where it has not mapped any PCI devices, which means that for Arm you end up with a CPU exception due to a data abort. Most host OSes expect "like an x86 PC" behaviour, where bad accesses like this return -1 for reads and ignore writes. In the interests of not being surprising, make host CPU accesses to these windows behave as -1/discard where there's no mapped PCI device. The old behaviour generally didn't cause any problems, because almost always the guest OS will map the PCI devices and then only access where it has mapped them. One corner case where you will see this kind of access is if Linux attempts to probe legacy ISA devices via a PIO window access. So far the only case where we've seen this has been via the syzkaller fuzzer. Reported-by: Dmitry Vyukov Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Acked-by: Michael S. Tsirkin Message-id: 20210325163315.27724-1-peter.maydell@linaro.org Fixes: https://bugs.launchpad.net/qemu/+bug/1918917 Signed-off-by: Peter Maydell --- include/hw/pci-host/gpex.h | 4 +++ hw/core/machine.c | 4 ++- hw/pci-host/gpex.c | 56 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 60 insertions(+), 4 deletions(-) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index d48a020a952..fcf8b638200 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -49,8 +49,12 @@ struct GPEXHost { =20 MemoryRegion io_ioport; MemoryRegion io_mmio; + MemoryRegion io_ioport_window; + MemoryRegion io_mmio_window; qemu_irq irq[GPEX_NUM_IRQS]; int irq_num[GPEX_NUM_IRQS]; + + bool allow_unmapped_accesses; }; =20 struct GPEXConfig { diff --git a/hw/core/machine.c b/hw/core/machine.c index cebcdcc3511..0f5ce43d0c2 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -36,7 +36,9 @@ #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" =20 -GlobalProperty hw_compat_6_0[] =3D {}; +GlobalProperty hw_compat_6_0[] =3D { + { "gpex-pcihost", "allow-unmapped-accesses", "false" }, +}; const size_t hw_compat_6_0_len =3D G_N_ELEMENTS(hw_compat_6_0); =20 GlobalProperty hw_compat_5_2[] =3D { diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 2bdbe7b4561..a6752fac5e8 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -83,12 +83,51 @@ static void gpex_host_realize(DeviceState *dev, Error *= *errp) int i; =20 pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX); + sysbus_init_mmio(sbd, &pex->mmio); + + /* + * Note that the MemoryRegions io_mmio and io_ioport that we pass + * to pci_register_root_bus() are not the same as the + * MemoryRegions io_mmio_window and io_ioport_window that we + * expose as SysBus MRs. The difference is in the behaviour of + * accesses to addresses where no PCI device has been mapped. + * + * io_mmio and io_ioport are the underlying PCI view of the PCI + * address space, and when a PCI device does a bus master access + * to a bad address this is reported back to it as a transaction + * failure. + * + * io_mmio_window and io_ioport_window implement "unmapped + * addresses read as -1 and ignore writes"; this is traditional + * x86 PC behaviour, which is not mandated by the PCI spec proper + * but expected by much PCI-using guest software, including Linux. + * + * In the interests of not being unnecessarily surprising, we + * implement it in the gpex PCI host controller, by providing the + * _window MRs, which are containers with io ops that implement + * the 'background' behaviour and which hold the real PCI MRs as + * subregions. + */ memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX); memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024); =20 - sysbus_init_mmio(sbd, &pex->mmio); - sysbus_init_mmio(sbd, &s->io_mmio); - sysbus_init_mmio(sbd, &s->io_ioport); + if (s->allow_unmapped_accesses) { + memory_region_init_io(&s->io_mmio_window, OBJECT(s), + &unassigned_io_ops, OBJECT(s), + "gpex_mmio_window", UINT64_MAX); + memory_region_init_io(&s->io_ioport_window, OBJECT(s), + &unassigned_io_ops, OBJECT(s), + "gpex_ioport_window", 64 * 1024); + + memory_region_add_subregion(&s->io_mmio_window, 0, &s->io_mmio); + memory_region_add_subregion(&s->io_ioport_window, 0, &s->io_ioport= ); + sysbus_init_mmio(sbd, &s->io_mmio_window); + sysbus_init_mmio(sbd, &s->io_ioport_window); + } else { + sysbus_init_mmio(sbd, &s->io_mmio); + sysbus_init_mmio(sbd, &s->io_ioport); + } + for (i =3D 0; i < GPEX_NUM_IRQS; i++) { sysbus_init_irq(sbd, &s->irq[i]); s->irq_num[i] =3D -1; @@ -108,6 +147,16 @@ static const char *gpex_host_root_bus_path(PCIHostStat= e *host_bridge, return "0000:00"; } =20 +static Property gpex_host_properties[] =3D { + /* + * Permit CPU accesses to unmapped areas of the PIO and MMIO windows + * (discarding writes and returning -1 for reads) rather than aborting. + */ + DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, + allow_unmapped_accesses, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void gpex_host_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -117,6 +166,7 @@ static void gpex_host_class_init(ObjectClass *klass, vo= id *data) dc->realize =3D gpex_host_realize; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name =3D "pci"; + device_class_set_props(dc, gpex_host_properties); } =20 static void gpex_host_initfn(Object *obj) --=20 2.20.1