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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=ziqiaokong@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, Ziqiao Kong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" Thanks the review for v1 from Richard Henderson! Changes since v1: - Don't update FCS, FIP, FDS and FDP for x87 control instruction. - Also write FCS, FDS and FDP for FSTENV. - Clear FCS, FIP, FDS and FDP for FXSAVE as intel manual says. Note: During my test, I find that the implementation between some intel cpus differs on updating FDS and FDP while the AMD Ryzen always update the=20 two registers correctly. Not sure wthether it's a bug or not. Ziqiao Signed-off-by: Ziqiao Kong --- target/i386/cpu.h | 4 +++ target/i386/tcg/fpu_helper.c | 50 ++++++++++++++++++++++-------------- target/i386/tcg/translate.c | 45 +++++++++++++++++++++++++++++++- 3 files changed, 79 insertions(+), 20 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916878..ba43ceb4ad 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -705,6 +705,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_INVPCID (1U << 10) /* Restricted Transactional Memory */ #define CPUID_7_0_EBX_RTM (1U << 11) +/* Deprecates FPU CS and FPU DS values */ +#define CPUID_7_0_EBX_FCS_FDS (1U << 13) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) /* AVX-512 Foundation */ @@ -1440,7 +1442,9 @@ typedef struct CPUX86State { FPReg fpregs[8]; /* KVM-only so far */ uint16_t fpop; + uint16_t fpcs; uint64_t fpip; + uint16_t fpds; uint64_t fpdp; =20 /* emulator internal variables */ diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 60ed93520a..97cf68542b 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -766,6 +766,10 @@ void helper_fninit(CPUX86State *env) { env->fpus =3D 0; env->fpstt =3D 0; + env->fpcs =3D 0; + env->fpip =3D 0; + env->fpds =3D 0; + env->fpdp =3D 0; cpu_set_fpuc(env, 0x37f); env->fptags[0] =3D 1; env->fptags[1] =3D 1; @@ -2368,6 +2372,7 @@ static void do_fstenv(CPUX86State *env, target_ulong = ptr, int data32, { int fpus, fptag, exp, i; uint64_t mant; + uint16_t fpcs, fpds; CPU_LDoubleU tmp; =20 fpus =3D (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; @@ -2390,24 +2395,41 @@ static void do_fstenv(CPUX86State *env, target_ulon= g ptr, int data32, } } } + + /* + * If CR0.PE =3D 1, each instruction saves FCS and FDS into memory. If + * CPUID.(EAX=3D07H,ECX=3D0H):EBX[bit 13] =3D 1, the processor depreca= tes + * FCS and FDS; it saves each as 0000H. + */ + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FCS_FDS) + && (env->cr[0] & CR0_PE_MASK)) { + fpcs =3D env->fpcs; + fpds =3D env->fpds; + } else { + fpcs =3D 0; + fpds =3D 0; + } + if (data32) { /* 32 bit */ cpu_stl_data_ra(env, ptr, env->fpuc, retaddr); cpu_stl_data_ra(env, ptr + 4, fpus, retaddr); cpu_stl_data_ra(env, ptr + 8, fptag, retaddr); - cpu_stl_data_ra(env, ptr + 12, 0, retaddr); /* fpip */ - cpu_stl_data_ra(env, ptr + 16, 0, retaddr); /* fpcs */ - cpu_stl_data_ra(env, ptr + 20, 0, retaddr); /* fpoo */ - cpu_stl_data_ra(env, ptr + 24, 0, retaddr); /* fpos */ + cpu_stl_data_ra(env, ptr + 12, env->fpip, retaddr); /* fpip */ + cpu_stw_data_ra(env, ptr + 16, fpcs, retaddr); /* fpcs */ + cpu_stw_data_ra(env, ptr + 18, 0, retaddr); + cpu_stl_data_ra(env, ptr + 20, env->fpdp, retaddr); /* fpdp */ + cpu_stw_data_ra(env, ptr + 24, fpds, retaddr); /* fpds */ + cpu_stw_data_ra(env, ptr + 26, 0, retaddr); } else { /* 16 bit */ cpu_stw_data_ra(env, ptr, env->fpuc, retaddr); cpu_stw_data_ra(env, ptr + 2, fpus, retaddr); cpu_stw_data_ra(env, ptr + 4, fptag, retaddr); - cpu_stw_data_ra(env, ptr + 6, 0, retaddr); - cpu_stw_data_ra(env, ptr + 8, 0, retaddr); - cpu_stw_data_ra(env, ptr + 10, 0, retaddr); - cpu_stw_data_ra(env, ptr + 12, 0, retaddr); + cpu_stw_data_ra(env, ptr + 6, env->fpip, retaddr); + cpu_stw_data_ra(env, ptr + 8, fpcs, retaddr); + cpu_stw_data_ra(env, ptr + 10, env->fpdp, retaddr); + cpu_stw_data_ra(env, ptr + 12, fpds, retaddr); } } =20 @@ -2473,17 +2495,7 @@ void helper_fsave(CPUX86State *env, target_ulong ptr= , int data32) } =20 /* fninit */ - env->fpus =3D 0; - env->fpstt =3D 0; - cpu_set_fpuc(env, 0x37f); - env->fptags[0] =3D 1; - env->fptags[1] =3D 1; - env->fptags[2] =3D 1; - env->fptags[3] =3D 1; - env->fptags[4] =3D 1; - env->fptags[5] =3D 1; - env->fptags[6] =3D 1; - env->fptags[7] =3D 1; + helper_fninit(env); } =20 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 880bc45561..c26d343ab8 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -4486,6 +4486,11 @@ static target_ulong disas_insn(DisasContext *s, CPUS= tate *cpu) target_ulong next_eip, tval; int rex_w, rex_r; target_ulong pc_start =3D s->base.pc_next; + /* For FCS, FIP, FDS and FDP. */ + AddressParts last_addr; + TCGv ea; + bool update_fdp; + bool update_fip; =20 s->pc_start =3D s->pc =3D pc_start; s->override =3D -1; @@ -4506,6 +4511,9 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) rex_w =3D -1; rex_r =3D 0; =20 + update_fip =3D true; + update_fdp =3D false; + next_byte: b =3D x86_ldub_code(env, s); /* Collect prefixes. */ @@ -5850,7 +5858,11 @@ static target_ulong disas_insn(DisasContext *s, CPUS= tate *cpu) op =3D ((b & 7) << 3) | ((modrm >> 3) & 7); if (mod !=3D 3) { /* memory op */ - gen_lea_modrm(env, s, modrm); + update_fdp =3D true; + last_addr =3D gen_lea_modrm_0(env, s, modrm); + ea =3D gen_lea_modrm_1(s, last_addr); + gen_lea_v_seg(s, s->aflag, ea, last_addr.def_seg, s->override); + switch(op) { case 0x00 ... 0x07: /* fxxxs */ case 0x10 ... 0x17: /* fixxxl */ @@ -5976,19 +5988,23 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) break; case 0x0c: /* fldenv mem */ gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)= ); + update_fip =3D update_fdp =3D false; break; case 0x0d: /* fldcw mem */ tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); gen_helper_fldcw(cpu_env, s->tmp2_i32); + update_fip =3D update_fdp =3D false; break; case 0x0e: /* fnstenv mem */ gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)= ); + update_fip =3D update_fdp =3D false; break; case 0x0f: /* fnstcw mem */ gen_helper_fnstcw(s->tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); + update_fip =3D update_fdp =3D false; break; case 0x1d: /* fldt mem */ gen_helper_fldt_ST0(cpu_env, s->A0); @@ -5999,14 +6015,17 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) break; case 0x2c: /* frstor mem */ gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)= ); + update_fip =3D update_fdp =3D false; break; case 0x2e: /* fnsave mem */ gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip =3D update_fdp =3D false; break; case 0x2f: /* fnstsw mem */ gen_helper_fnstsw(s->tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); + update_fip =3D update_fdp =3D false; break; case 0x3c: /* fbld */ gen_helper_fbld_ST0(cpu_env, s->A0); @@ -6047,6 +6066,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0: /* fnop */ /* check exceptions (FreeBSD FPU probe) */ gen_helper_fwait(cpu_env); + update_fip =3D update_fdp =3D false; break; default: goto unknown_op; @@ -6214,9 +6234,11 @@ static target_ulong disas_insn(DisasContext *s, CPUS= tate *cpu) break; case 2: /* fclex */ gen_helper_fclex(cpu_env); + update_fip =3D update_fdp =3D false; break; case 3: /* fninit */ gen_helper_fninit(cpu_env); + update_fip =3D update_fdp =3D false; break; case 4: /* fsetpm (287 only, just do nop here) */ break; @@ -6337,6 +6359,27 @@ static target_ulong disas_insn(DisasContext *s, CPUS= tate *cpu) goto unknown_op; } } + + + if (update_fip) { + tcg_gen_movi_tl(s->T0, pc_start - s->cs_base); + tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, fpip)); + + tcg_gen_mov_tl(s->T0, cpu_seg_base[R_CS]); + tcg_gen_st16_tl(s->T0, cpu_env, offsetof(CPUX86State, fpcs)); + } + + if (update_fdp) { + if (s->override < 0) { + tcg_gen_mov_tl(s->A0, cpu_seg_base[last_addr.def_seg]); + } else { + tcg_gen_mov_tl(s->A0, cpu_seg_base[s->override]); + } + tcg_gen_st16_tl(s->A0, cpu_env, offsetof(CPUX86State, fpds)); + + ea =3D gen_lea_modrm_1(s, last_addr); + tcg_gen_st_tl(ea, cpu_env, offsetof(CPUX86State, fpdp)); + } break; /************************/ /* string ops */ --=20 2.25.1