From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629471; cv=none; d=zohomail.com; s=zohoarc; b=DdlxDUgwW7d5KWpKCpsA7HRAHL3wruCYWWDTXPrk3u0Vag2ZxWNDCnl+FcjzEwGntp2VLZ2nvtH3sjQibrlQJdEtQxE3FjqIv5NgzL6aLI/FftUNmLxitM2psjDw1ia/WsKCUiBe2eYUP8gNpXzRB38X0F99ZyTUB9jKS5dFZ7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629471; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=LyO8R+c4YVVr0Mzx051uDYvANSp28AJZBOaC9HpyPBxI5VgqNekB9KUQfLWedWEl/DkMELGZjhxZ/uG9ahHEo9h3RQJArkYbHuNnICzINNTHfSCaZeF9KvVBIFLgUj9spRfHNf4wGOnozcwh7GT5iHqvA4KXnR0n+qxQ+Zvifck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 161962947128531.406589007445973; Wed, 28 Apr 2021 10:04:31 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id h4so54788976wrt.12 for ; Wed, 28 Apr 2021 10:04:29 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id n5sm411720wrx.92.2021.04.28.10.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:04:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=GxlgsrYCVusN/Q/fwa6c60LGwupHB6Dc3VhOtigEydalOP9jT61c9XMa3paurKakRm y1MtSIckNuDdCJbPEBcw1sqp0tTDeu38iN8GEF2b8Ztjcahh72k3U3oeDQb/QW/NnrlO hnY/rgjbppTSlK/CpCErghoLYgr98aDvir7lFjL+pYnBI/dzmE8JeniQPOg6XBQncDZY KioualR7aaV957V8UN0pj1sgcHYFVDCnRS70wzH7tPUI1DVQGJfO/XfqL0FKHnorHPTV yStSGtc4eFRrlFg5fJh8aBdslt5zMAXUFKF7GsQnB1kmAfDYOEa8U9JXD+1DXkT0eZhv /oCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pi4Yqp/Ga3uNxjsupGFLY1gAQ5ebMQowaCuPTS7xonw=; b=MHiHsOTA9SF8VAHJcFo5tk/waKLCojjcOxhSfoZrxUX9qHsXQ8TRpm6LkLP8JZcFEC 23K/CmEQtWbKoKKY8l/g/hb9yDCW+TA39bNK6mauLAu36+6DcesigBZuecB7bruIu9uj Ma1P6MvA+0ye7x1hyNChOK51aAhifqb6QixKaaU82oVXZm7p8cErp5tT+RBBd6Tb4jLg n/53qnJyKmus75iPVHIKwr78wXvSS0o4KpDbAvPgVq70gRARNaR/Z4zOqnWcpX99z+2T 2vdRv6v+BEkNYyD054ipvHbXKKrBKBjNsJlkHe2eJBfucAlyclDrw+ybl+D0HOvzbxL9 r/3A== X-Gm-Message-State: AOAM5318IR3drfuQ065/I4w0lMCcFpW23MLuZUBAGAeatKnQktJKQW93 DPqeuUBidPxGMDM2hJoMSN4dmiPe5k0LSA== X-Google-Smtp-Source: ABdhPJxjQM33GzEe2r4BP3keMsKNCXfq8FWimFGRm6CU2/XjrbBk/9AzhgGe6I7XGtTSO3rEdDv+pw== X-Received: by 2002:a05:6000:1547:: with SMTP id 7mr5360614wry.388.1619629468770; Wed, 28 Apr 2021 10:04:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 01/30] target/mips: Simplify meson TCG rules Date: Wed, 28 Apr 2021 19:03:41 +0200 Message-Id: <20210428170410.479308-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We already have the mips_tcg_ss source set for TCG-specific files, use it for mxu_translate.c and tx79_translate.c to simplify a bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 3b131c4a7f6..3733d1200f7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -26,10 +26,9 @@ 'translate_addr_const.c', 'txx9_translate.c', )) -mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( +mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( +), if_false: files( 'mxu_translate.c', )) =20 --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) client-ip=209.85.128.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629475; cv=none; d=zohomail.com; s=zohoarc; b=VO1a8QAbvG1l+qGouAj0UKV2ZAoI50A8U0zOnnpIHGc4+FKNbOJXTZS3E1+wS/aGRQOgHwZCldbQ4LlJvPub6jteJjnTSDpNh0/DJyaTRgHXheGQiJvmmq381xpJEA1bm5PAN74ggGaIBRjj+gJrMgk5C7peONCNYBYbM3fH0EA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629475; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=Zk9NkLiCHMyu91RfLietTm5CkfbnBYPGTbTj/mHNyDMAcF0bYqNoPZZUnjf6tjxIpVfCK3W5J1uUnPaU3hkmcUjRBkO8uItN5MuWlfPcGxpNNz5JCHDIhOtvZO6Ksch/FTM/H1D8fcFMB+PZeQhroH+/EENJeOVJ8PbU2/fpOA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.zohomail.com with SMTPS id 1619629475803672.3854290380785; Wed, 28 Apr 2021 10:04:35 -0700 (PDT) Received: by mail-wm1-f45.google.com with SMTP id o21-20020a1c4d150000b029012e52898006so9238332wmh.0 for ; Wed, 28 Apr 2021 10:04:34 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id k188sm8964572wmf.18.2021.04.28.10.04.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=iCOTMCz3EzGzAzpcxWcX5x1G+hXKWOdrKX0sZCq7fFMkKDjwx5x9qjfhhzuR6NViiQ RqNCxDvSGD/+mM90KESVgCAxlwKLO85iy8pDi/4JLYekKRX0fkeF/eFJgkcV2Im4hRhC 19hJMlJj7+v00KHg3QmRVcrVP/KT/gvQJZSQ7yb9ofl2DinEV3pVsIa3JKQ5bkAKgu+H oxMyKF6wv4hUYTRTHa9bpRmz52Xz/uFq37hVOWO3NdXTkiEn9hFajpscc4xKIqN1dqJt xrJtOd0mExKFPYQ9FGbb7MkiNmKsjgdRK+BtxUPdrJv+DXxlXJnMfaDRHMlyBpx915hk ajew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fGOvaajXfmrpLSnOyhpIroCQXe3e+OS5MF3gQarLZWU=; b=jjISobR3YOZJt/wI5gbzUbJxgcyJuWRRgOvoAvxMkeiFeJ+2zcLTCQi6QqyLbPdnko wlCiVmuqvSk86VMrDyXyai+j741B5Yk7BYQ2chE5eezr639mlTikwJd4uHhah9EO6wu2 U730zabLgKImd+Qs+V9TFzcmzge72TTyvFIxIN7upknMaro+LPLA+aJfyaU7dbSTcJ7M 8PdZ4rjh+N5FKV3TEwJzlNyK7LLxp4q8gsebRDd/cWEF+UDZopI1v/kXJpcSO0rthco/ x3112Z1noH27dSUMXaFzuZhc9ZRrkk9uPCbSDfi/d4RgfckeYcN0YNf00bnvBSzwqqcf hn8A== X-Gm-Message-State: AOAM5339u5nW5RQ2KBAF6QDfnMmtv/VyfQfEGykE6/F79NWirO0DpyQ+ exuP4CZja82uBSli6O1toNE= X-Google-Smtp-Source: ABdhPJz9BHqN4OAeqZgyfxoORiTACduJgY4PcBwcGKVQXivPhXN8sRzO3fqwFTy9nlMvlRyUFdGAuA== X-Received: by 2002:a1c:a949:: with SMTP id s70mr5750147wme.84.1619629473525; Wed, 28 Apr 2021 10:04:33 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 02/30] target/mips: Move IEEE rounding mode array to new source file Date: Wed, 28 Apr 2021 19:03:42 +0200 Message-Id: <20210428170410.479308-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/fpu.c | 18 ++++++++++++++++++ target/mips/fpu_helper.c | 8 -------- target/mips/meson.build | 1 + 3 files changed, 19 insertions(+), 8 deletions(-) create mode 100644 target/mips/fpu.c diff --git a/target/mips/fpu.c b/target/mips/fpu.c new file mode 100644 index 00000000000..39a2f7fd22e --- /dev/null +++ b/target/mips/fpu.c @@ -0,0 +1,18 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "fpu/softfloat-helpers.h" +#include "fpu_helper.h" + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +const FloatRoundMode ieee_rm[4] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 6dd853259e2..8ce56ed7c81 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -38,14 +38,6 @@ #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL =20 -/* convert MIPS rounding mode in FCR31 to IEEE library */ -const FloatRoundMode ieee_rm[4] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 =3D 0; diff --git a/target/mips/meson.build b/target/mips/meson.build index 3733d1200f7..5fcb211ca9a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -9,6 +9,7 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'fpu.c', 'gdbstub.c', )) mips_tcg_ss =3D ss.source_set() --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629485; cv=none; d=zohomail.com; s=zohoarc; b=YymTKnns+FGjzVXdZqD1VLXcuAmrkSKO7CW40bqYrgiajS0DOa5UTyWWAy53MHTLSn8eLnO/gceKRB6Rp0Ll+zGm6ZefYJGWOAGeWCTuZ5mVv5946zgARBYq9/QrPI1fbUHtzWr2iIJdCq4kk2+WNmMyDJoP3n/tczfqV8M6Sao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629485; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=hjmSJLMZ8wDMQ6JBDAgbfV+cukAegcZZK/3zzasYyvHLcH+PNsIQs01QUwjXkpB88St6UX0NFV2tjpxv9/Ni+QJP/t81Rndfkn6adyjEzWOAte8XZu+YTN7ayp+lElGQ/vtGkXPwbtkTx0gx3k8vjA/MJWhsmOx0FgFh+3PhHMc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 161962948572751.110000287171374; Wed, 28 Apr 2021 10:04:45 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id n2so10665518wrm.0 for ; Wed, 28 Apr 2021 10:04:44 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id v18sm529775wro.18.2021.04.28.10.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:04:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=cfF7Jlr8AovFAUH5K7HDOrFtT2t6AbY2X6XAi5f7uDcSYx1Tu+m+JXHbO3TRyiFOzD LSDfP0pS6vgqGblDPJ6jLGIiE//pHJzyFL/w9JON0l6YX/yKcZmKZTcdBctgz5+64jn7 XPsgGg48Z8GAdEaH4eieB2SN9e6KlYYwHYe74HdXIhj+ZdNwkH5nBk6JUVeNldw5iO8n ozuDg3rY7r8Jbg62ZX0Fa53LJRtF4sex37uelfetbRgIlXkhbBUCxArFT2o+QJWFPB1+ iHOrBcVaXA5uSjnXN0AZwflL8pIk3nJI4WLLe5YFVKSmAaz+lUZn4AAKnXmc1KKIs8me 0evA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yMxvZRcRgCBUS8Ws91rPcuJR47xd/yHVMPRhORw6260=; b=GkeMXV5SZr3c1z4B0i9RwDGrwxfAZQ0oFbvqniT/Kh6pluCA1q8KPRXDj78cAqSuIU TBIfZtr+uBlGBGGGhck1ri8X58UAyF5zGUWFVpYKEUmZ2pnMKtES/gAdSOK/3vIlixAA ugaOdDdAaAnAUHwbyq3WXQ63aYdLdfEuEx+Mbc0oTQvbZUF3OzQBdckzGA2eOPmIUYkD nZMF5GvFL3DOYSegvFixRHaJ5bg7vOGE5tHxmMqFJJtZYanTz2c/ENUpDfZ7kLe0w6nX Q4Vo9C8bUzY09DzHJIbhvG1GTJ6fJ70U9dX+kkPyLCFZN4ZExVjhMUf2bnrE+zTZ29OP q11A== X-Gm-Message-State: AOAM530WYTKFNzvo2YZmEs9Fjkfg8MYObqR/GTYBfivgNM/Bpbur1uNT 8OVAsmZOpWmmkk7uD4FBU3c= X-Google-Smtp-Source: ABdhPJxR6I5VPh70jEMTzOFjYk9xqCwpMaal72854dpTdThpbCSNj7zEb6BZjHHPrjZyK+4uT6+fcw== X-Received: by 2002:adf:dd52:: with SMTP id u18mr4954667wrm.32.1619629483498; Wed, 28 Apr 2021 10:04:43 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 03/30] target/mips: Move msa_reset() to new source file Date: Wed, 28 Apr 2021 19:03:43 +0200 Message-Id: <20210428170410.479308-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/msa.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/mips/msa_helper.c | 36 ------------------------ target/mips/meson.build | 1 + 3 files changed, 61 insertions(+), 36 deletions(-) create mode 100644 target/mips/msa.c diff --git a/target/mips/msa.c b/target/mips/msa.c new file mode 100644 index 00000000000..61f1a9a5936 --- /dev/null +++ b/target/mips/msa.c @@ -0,0 +1,60 @@ +/* + * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. + * + * Copyright (c) 2014 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "fpu/softfloat.h" +#include "fpu_helper.h" + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 4caefe29ad7..04af54f66d1 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); #endif } - -void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* - * MSA CSR: - * - non-signaling floating point exception mode off (NX bit is 0) - * - Cause, Enables, and Flags are all 0 - * - round to nearest / ties to even (RM bits are 0) - */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/meson.build b/target/mips/meson.build index 5fcb211ca9a..daf5f1d55bc 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -11,6 +11,7 @@ 'cpu.c', 'fpu.c', 'gdbstub.c', + 'msa.c', )) mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629490; cv=none; d=zohomail.com; s=zohoarc; b=YBWlY2/4S7VflypRjRgXneOxSQjmvBk1nVrElcwsCibuMGNuvfVOQMTENAlx/9yVmo7JeB0Vt0FMA2jBazXsJzsjWjx5Mtm7ISqve1tbEiZxMvb7wlgljzonATlMbahV9q0z+H+62A6dePPIvztQhfPCIjk1cVJ1Q40+jYR3QVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629490; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u8QpgoHSjUQHQmnKwhaHEWBPun3v2yiMKRzyi8Uhl6w=; b=FxOGMg796g1sHuYF3R2Ql6g4W0uiNjopsqNvqU5wqHFsnaoa57ACkR0gws5N4cm+Jp/JfAMOrwKJ8GZexVOKmlhXOLDeNu6LvMjttRaKCLfed6Ogd/ft0UsbjmbNhJqVoc3r1/Hilu5MI6+5DaIvS5695BX7GwuGbt9wgcUbkHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1619629490213993.7347582662742; Wed, 28 Apr 2021 10:04:50 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id a4so63851227wrr.2 for ; Wed, 28 Apr 2021 10:04:49 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id k16sm312004wmi.44.2021.04.28.10.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:04:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u8QpgoHSjUQHQmnKwhaHEWBPun3v2yiMKRzyi8Uhl6w=; b=CJItHyxsybT6+hSmpDa6CAOE0p1J9EsQspjITXQYpTI9JLnOq5uouuG7ABXKiO7uHH 1pZ6prIb1PGDLgSeSb5JQ1W024SSceI6Al1r9fU1xXcUGELJpgzjHGkhh8OGpv6GKbG1 mAW8CC0BNnYlSysLVVIu8QtZR7tchWFbsTiF+3gL7jDP7g+aAdvC7lqj+t+GwoUUV2C9 9bmoNJlGxs/+Y0xYKaajR23XinlIJKSblRgCGHozW8OvgOyTiOympm2hHJZIJeHYkt3K YCtgz14EZQHaiiCn7KiCi3PDI8dOw7ECWsHUIiizXTUZq59rISLwthcu0RPt0qCQb7r8 tCvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=u8QpgoHSjUQHQmnKwhaHEWBPun3v2yiMKRzyi8Uhl6w=; b=Pv6RL50w5absWR27RBuSDGE7GFMwqfLjl6mX1lO+i73Mcryv/XH6Cof2Y4kHuATo1i NhfYX61RRNmn6bffVRTAWjiP8D5DtAW//2vpL5VnrU8R0T8FmfC0EC+jR7sfKCjpWMbD 3PgJV+gLqwHAP4CV9h4STycPKW0EDvGBofGfmuyetq3F30HqUkt4AM7COR/AvgypvUoq xhkRRHtVuRG3b9mlQjLbLrYPd5AXZHNx7bjF9svrnBu96f0Y5ndTR2n3O8oItYflBRLr tnUwN5UJAG8crZRlhNtFSWACMk9Hm1DDSHGqEiWft47zM20+0BikVBc5PAgd3kJ1R4vJ +hXw== X-Gm-Message-State: AOAM533eGdsHLkOssrkIRXB8QgUFQ5/AfzwKk3QjcVhwnOJwS5DjnST7 mfauH2WTUBdUm5ymlw3YBgk= X-Google-Smtp-Source: ABdhPJyeyYh1mkfciZhY+vPNTyPHsYgOiSL5FOo+i+GnPGJPuguu/cV9nGC4cMTivDjRIOnMbw3idg== X-Received: by 2002:adf:f40f:: with SMTP id g15mr37546430wro.46.1619629488259; Wed, 28 Apr 2021 10:04:48 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 04/30] target/mips: Make CPU/FPU regnames[] arrays global Date: Wed, 28 Apr 2021 19:03:44 +0200 Message-Id: <20210428170410.479308-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CPU/FPU regnames[] arrays is used in mips_tcg_init() and mips_cpu_dump_state(), which while being in translate.c is not specific to TCG. To be able to move mips_cpu_dump_state() to cpu.c, which is compiled for all accelerator, we need to make the regnames[] arrays global to target/mips/ by declaring them in "internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 3 +++ target/mips/cpu.c | 7 +++++++ target/mips/fpu.c | 7 +++++++ target/mips/translate.c | 14 -------------- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 99264b8bf6a..a8644f754a6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,6 +71,9 @@ struct mips_def_t { int32_t SAARP; }; =20 +extern const char * const regnames[32]; +extern const char * const fregnames[32]; + extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bde..f354d18aec4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,13 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 +const char * const regnames[32] =3D { + "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; + #if !defined(CONFIG_USER_ONLY) =20 /* Called for updates to CP0_Status. */ diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 39a2f7fd22e..1447dba3fa3 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_up, float_round_down }; + +const char * const fregnames[32] =3D { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", +}; diff --git a/target/mips/translate.c b/target/mips/translate.c index 0e90d8cace6..8d686e90954 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32]; #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 =20 -static const char * const regnames[] =3D { - "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", -}; - static const char * const regnames_HI[] =3D { "HI0", "HI1", "HI2", "HI3", }; @@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] =3D { "LO0", "LO1", "LO2", "LO3", }; =20 -static const char * const fregnames[] =3D { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", -}; - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629495; cv=none; d=zohomail.com; s=zohoarc; b=YBPilHmffuQ/AcwWG6H240Oov8L093S0KGrs11rum/by8mFCxbRf0oGgICEt4FNGXgVxTSSAGfzvHMUdSnty0O9+jk0lv7zl1BH8F5Ghiuw0K2Zy1/HMaPZbZ41+Y9FtcLDBW5ChrISc906bERBtg5Vcm9XNvvS7rTsSezyVSao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629495; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zi+fMglV6U1JmHUHb3YXn7uEOGSf74nTOit2v0a7sNQ=; b=d35IKj5VnGu5K4wyyougowqv+zr5GZ0BIIgxGMXR77PNm5dLjY+z89F2bUz9l8oDNgmaLu2veSaCvs5Ij2kKtktYDJQGEODSDygS8olVyXz7HnSMNRHndRmASMiKap5OWFhejSFg2Sp/bJxi8F6rUfM/2zw+JY1BiHgN16vc8Nk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1619629495126631.8172556308498; Wed, 28 Apr 2021 10:04:55 -0700 (PDT) Received: by mail-wr1-f47.google.com with SMTP id n2so10666069wrm.0 for ; Wed, 28 Apr 2021 10:04:54 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id d2sm459430wrs.10.2021.04.28.10.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:04:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zi+fMglV6U1JmHUHb3YXn7uEOGSf74nTOit2v0a7sNQ=; b=OhdCaowZukSejyWHHTwiBU3vCNNzRMbR8phqbi1YrGLVUUuKLlnQzpSAEsvrwNTNKZ W4log242zRp8WwP3VKYYFo/icDxuzMeW5aqdVpxfsMw6QYURTyoPq5Qdrb+kA7/zu5Qf hDwwwQJ4/XzMLQimsoCyWgJ0sPp/zkTOK5iYwnIBjAdMtYmcgDLLW2ck1uT4c6PjXApf YLhp4BgDITIirGM6mP0J97mewAKvxCiWFOwd8nZgEd1tUmh7sN5jUnrK0eMyFAaQPMoD kQAZsiN5/LgKmQmtWDu3nnkZQlldPYsEBWVnt0c5PnMi/UNTdeLtwf9OivteFQqDgcAA fTIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zi+fMglV6U1JmHUHb3YXn7uEOGSf74nTOit2v0a7sNQ=; b=SJE0AYPT0Ft7PW8XOZTGhFfYZ260qIzfEIaTVYWXe+QXwz9Tgz+6vdU+Q8l7TfqA1/ I2g0/kOG+kBSTeP7R40q7y7PGI9rx/4dsNjwKscPxMUsPW7kqfGIwVwy7QgDha2in+QO yaOVH14zucxxQOZXEAAA6dk3Mc8LS4CxwFY1K1a/92GnvBsTZdpxfTpHzp3H38r51JP0 trODFddsNBYDRKAC1gitokpokElS4qbcwWm3FiVwZIe54iUSE2bUpLDb4Utmn/clpr9l TKODocNMrNsvxVcrVJxZGReT0smW6Kbgv8wqO2wpfySuJFrRbLCnSQrowZwzHErITEIh J42w== X-Gm-Message-State: AOAM531c0Ws15TZxUMLS/wHmSPxj8pR63TW3J7RB1UnSo3Z/3rwSD0sP OTBjhHYeNX6+9x428/P14dI= X-Google-Smtp-Source: ABdhPJzpwG5Oy7kNx/2gMYAV64qWVoKZSGEcalo284rI9OCFWjoXjwRjRtLuBormQrTI0BxUObGRLQ== X-Received: by 2002:a05:6000:1846:: with SMTP id c6mr315746wri.129.1619629492848; Wed, 28 Apr 2021 10:04:52 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 05/30] target/mips: Optimize CPU/FPU regnames[] arrays Date: Wed, 28 Apr 2021 19:03:45 +0200 Message-Id: <20210428170410.479308-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since all entries are no more than 4 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 4 const char. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 4 ++-- target/mips/cpu.c | 2 +- target/mips/fpu.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index a8644f754a6..37f54a8b3fc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,8 +71,8 @@ struct mips_def_t { int32_t SAARP; }; =20 -extern const char * const regnames[32]; -extern const char * const fregnames[32]; +extern const char regnames[32][4]; +extern const char fregnames[32][4]; =20 extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f354d18aec4..ed9552ebeb7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,7 +35,7 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 -const char * const regnames[32] =3D { +const char regnames[32][4] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 1447dba3fa3..c7c487c1f9f 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -17,7 +17,7 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_down }; =20 -const char * const fregnames[32] =3D { +const char fregnames[32][4] =3D { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619629500; cv=none; d=zohomail.com; s=zohoarc; b=GFzfLMgbQSbsCJ+IJIzcGZLLF2Zfa0j+fmKrsIOxberiXwLHlFhurhbJdJUYLqoBNCfsX2pz2OdvyMEGb+7fK1wsT4I3+riTcbdfKLw0ru+6/WKsMgNQFXZTYuw5GiGVKbUBJT84w+pieO/uo5A0Hv3JhdPHhUWw0T+ZDU8WBV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629500; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4PMaVU/rULsBIbK+fWQHt+kTaSUIcMpx29k+kaC3g04=; b=hYFm/7pajyqnZ/F86pW89WpFOlNqUbkjzF/A2OELRAEW2ig8xNlhRxhK5aXLb8Q4p3Qna1VkjSqO3L18PQhOW5eu6LpkcQ4Foe+qXiFS4OvomLnpxgZVJ9McAd5Ez+Ls7e1kifCHSUmTFyL8M44NnPuRlLhu9wBAx3PYGWKhkZY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 1619629500104987.1200485801121; Wed, 28 Apr 2021 10:05:00 -0700 (PDT) Received: by mail-wm1-f46.google.com with SMTP id n84so7050437wma.0 for ; Wed, 28 Apr 2021 10:04:58 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id k15sm353527wro.87.2021.04.28.10.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:04:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4PMaVU/rULsBIbK+fWQHt+kTaSUIcMpx29k+kaC3g04=; b=O3dgw1aR8HXd6W6F5fRMptSZNZgzpUxAu62q6JxIGlKuwVPfn1O668in3swXJk1kLa ciuU2FshXphykD9nyzZ7qsl4Pi7sk5EeMZPfYjZIWJ16hL6xVdm8T1zCaIptyGMhcg00 Ghbtu0LfR3zN7xeg8aq1FKC1NF8aTNYII7PWbFdnXgr3paSsN9BETIunLbt8QfmvLHKu 6J+plrTLnzuws58azKLKEBxcjs3L2QgqqGBKhMaJx+AsbGrxA1rwYO07LGb/tI24vbqZ j2gX+vgBJnRiz403f80Gvov2T0PkS5u9HaIj/FMDJrWYLKkJ2VQ1Vl2Xpr6ryAnCKav8 UR0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4PMaVU/rULsBIbK+fWQHt+kTaSUIcMpx29k+kaC3g04=; b=mwvMdJVizHtPEGfCDLDg1edplVmqeyZyixQlpAnHb1YujbMTQ07noPmQGkVGzh0Ecp 9FZoDx61vsccYEy/bkRqqB5leUvOc4+cQexkYt9ji7pfdWH7TbDWKmn/P9K9Dd0s6qoB BFyKbr4kqkZtpsYs7WiFOgDbjZWS4nYK8S5HfbRraz5L28UPvgWYbj6nl0POh9tYm/// TX4KhJNFCAbWn9YQfKP12si7bQap5W+N0f9SDidOx3yu3qlY5D9ChMetPS3VyBWbQsoK Mt+Y4ScAbaSeExcEq3ChfTUWIoiB+nUw3QCPunEhdbZncIFBoQ3H7SugruNFlNL3srRo yRcA== X-Gm-Message-State: AOAM530BqUl3s06cBP72ocXendOP201Hf7xcSYcafOX+z5YU78CX+SYu 6meRmO2fgU6dGOWhZCN1aqY= X-Google-Smtp-Source: ABdhPJxN5yuYAcgBvdug6jZoIdwisnqxMtW5FZv34PLH+8/idfRIrGQBmtUnrxgSoSQ6eaLltpjXrQ== X-Received: by 2002:a05:600c:19d1:: with SMTP id u17mr31365086wmq.111.1619629497536; Wed, 28 Apr 2021 10:04:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 06/30] target/mips: Restrict mips_cpu_dump_state() to cpu.c Date: Wed, 28 Apr 2021 19:03:46 +0200 Message-Id: <20210428170410.479308-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 1 - target/mips/cpu.c | 77 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 77 ----------------------------------------- 3 files changed, 77 insertions(+), 78 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 37f54a8b3fc..57072a941e7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -79,7 +79,6 @@ extern const int mips_defs_number; =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ed9552ebeb7..232f701b836 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ul= ong val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) +{ + int i; + int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while (0) + + + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { + qemu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + int i; + + qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx + " LO=3D0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], + env->hflags, env->btarget, env->bcond); + for (i =3D 0; i < 32; i++) { + if ((i & 3) =3D=3D 0) { + qemu_fprintf(f, "GPR%02d:", i); + } + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); + if ((i & 3) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } + } + + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" + TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { + fpu_dump_state(env, f, flags); + } +} + static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/translate.c b/target/mips/translate.c index 8d686e90954..f0ae3716022 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25586,83 +25586,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb, int max_insns) translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 -static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) -{ - int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - - qemu_fprintf(f, - "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); - for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { - qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); - } - -#undef printfpr -} - -void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - int i; - - qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx - " LO=3D0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], - env->hflags, env->btarget, env->bcond); - for (i =3D 0; i < 32; i++) { - if ((i & 3) =3D=3D 0) { - qemu_fprintf(f, "GPR%02d:", i); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx, - regnames[i], env->active_tc.gpr[i]); - if ((i & 3) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } - } - - qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" - TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); - if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, flags); - } -} - void mips_tcg_init(void) { int i; --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629504; cv=none; d=zohomail.com; s=zohoarc; b=ZWe5MokTJkrZnOPbXkExObVvGoK99C6al/uUsrHoZVGVwpVGAnoEbB5dTP/JpqOargbgfaD4Tk9uS3VCoLO1UeMPqUnZbDtC5aPtWoQFZpPPoyBy/KSjQ+wXh5b4nFdgzl+qgdwCm4fMrdHfUlxhsnfk1GhzTwlB2S8shMztKT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629504; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=81mtH9pgmG7PdH3lg91nxUZhPt4Fd55YXcDqmcN5kGI=; b=Uprfpaziq75vpYOnOdjPUSCotd7J53MlD2E5S/ykel+ipASwobyM1JFjxOqGOYEMnZALwP9EVFTIxR7yaxcqqQHwT+VNUI6agEuoKwjKH2YsH2hSl9mC86yaz9dqNtmAYKOoSegz+XDWQo64fXUdBLMQFYBcViaRJmJ0c8NRi2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619629504350847.7928604227473; Wed, 28 Apr 2021 10:05:04 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id h4so54790694wrt.12 for ; Wed, 28 Apr 2021 10:05:03 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q16sm343815wmj.24.2021.04.28.10.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=81mtH9pgmG7PdH3lg91nxUZhPt4Fd55YXcDqmcN5kGI=; b=QjfVs81kGXoTnlok0YAqYAHt5jSKXiS6P/RWxr5HCIwMqXSm5sSbHMVsMatc9lDzh/ TixdjG5eQw+TM/l9ki/EzpkNqC6sVfNOx/V5cBbVg1UYaZuNJhPIPCjdyr1gQHb+Iazp x/nRQi7/Huc8YuH+UudFb79ZlbEVJf8JaD/g6tf6PieHiInrLK7HhCqFL52X/jyCUbCJ kJL6Z78hUcrpNXBBfm+eNHZIbijG0KaWJRry+4uFv4Y2GVpKLMZ9y6ohkccGeKRwI8I2 gJr4w/OcOiRFpSQnVTW0sCp6BmgMrgST9sX/G4HsLxAnKJ4vYOgO01mjG8bMwvIN5Yfb SYUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=81mtH9pgmG7PdH3lg91nxUZhPt4Fd55YXcDqmcN5kGI=; b=GwnRLbYAacWKMwkK4ZdJVBk87bNaKxbn4J7mpsF+kFNLycEY8ek8+n08ykQWcFTaXU INj0XM4iAKsTqC6cTUABm0h4va2Ljybvqg+C431jdopyV/hZzARn4CjnOBoHs86SO+Lo fvmX+OefUibg3dQX0FxfW6XpjFXj/MKhf2SfWaxFgPD+k9bwEgyDCkJGexXByBYl7kWR SDMipv8kWUgZ9DX3aVrDmPSftnLiyF+vQ9ShgVUyS2ZdTqLWrHAHhswSDf0FFQDbagXW e9lqbEXN/GxxiZv+2mGGhmhnoL2LeoyzaWdC6GqiEs6ev5iXJZBgLuk92bvTRcRHKaBZ tO8g== X-Gm-Message-State: AOAM533cyszCD+ZBCovdj5pzVexO5eawU4lNnC5UO2/wtoONENeEf+zX G9Sh1OFKt0rAaOzCqtUNeuU= X-Google-Smtp-Source: ABdhPJyWZfhniJfRdhXe4VW6ZGJYS2ThKT5rrI5sPRQXg/SMhJAbAB5e9PwGq+XF4aBkIqsST4LxeA== X-Received: by 2002:a05:6000:18af:: with SMTP id b15mr38185828wri.71.1619629502155; Wed, 28 Apr 2021 10:05:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 07/30] target/mips: Turn printfpr() macro into a proper function Date: Wed, 28 Apr 2021 19:03:47 +0200 Message-Id: <20210428170410.479308-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Turn printfpr() macro into a proper function: fpu_dump_fpr(). Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v4: int -> bool is_fpu64 (rth) --- target/mips/cpu.c | 50 ++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 232f701b836..8f76f4576f4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,33 +145,31 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_u= long val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) +{ + if (is_fpu64) { + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g= \n", + fpr->w[FP_ENDIAN_IDX], fpr->d, + (double)fpr->fd, + (double)fpr->fs[FP_ENDIAN_IDX], + (double)fpr->fs[!FP_ENDIAN_IDX]); + } else { + fpr_t tmp; + + tmp.w[FP_ENDIAN_IDX] =3D fpr->w[FP_ENDIAN_IDX]; + tmp.w[!FP_ENDIAN_IDX] =3D (fpr + 1)->w[FP_ENDIAN_IDX]; + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\= n", + tmp.w[FP_ENDIAN_IDX], tmp.d, + (double)tmp.fd, + (double)tmp.fs[FP_ENDIAN_IDX], + (double)tmp.fs[!FP_ENDIAN_IDX]); + } +} + static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - + bool is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); =20 qemu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", @@ -179,10 +177,8 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f,= int flags) get_float_exception_flags(&env->active_fpu.fp_status)); for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); + fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); } - -#undef printfpr } =20 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629518; cv=none; d=zohomail.com; s=zohoarc; b=bAzx7ZjUziqUDhz921N43fF5WVrMP6CXxuZ+fUg7A2eJvL83RIe8Ou8tvO4ZQ9EnGJMl8HvfQ/YLJoh+3rIsdgDwkDpHJ7hsSGR06F/ldNsy2CgqSOd6Kx9u8xh+/QTinwoVU+yMnvBGO7dHUI2z5rp4P9SY0dplNJx3+aAlyZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629518; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EOSzSixAzta/FPxWAggSKFD1+tlg1/eL2RD8SSdD1EU=; b=h1lWMo+WgZJs4PH3DEqBY/2nFQWQaq0ctYqP3lgc4VlVRBjA3w83Phe/CymolfbhL3ptcj2VV1OyvGyb4Q86MX9+V2BJoPLh/asDlezZPM9CSu7IkjOUZTVVqCyK/RVi0RvM6n76gVjJ6D7aNU6ByHcPE0BSlHLvXZtNZ6uUWL4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619629518280590.3514430015213; Wed, 28 Apr 2021 10:05:18 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id e5so35179174wrg.7 for ; Wed, 28 Apr 2021 10:05:12 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id p7sm472394wrt.24.2021.04.28.10.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EOSzSixAzta/FPxWAggSKFD1+tlg1/eL2RD8SSdD1EU=; b=a0pLiGNtt6e2X8pDEOarq78UvC6GkxlEqyHcQRTqdwyZI8Iy14HJgwc4hOcAzbxfAn RKauC7fXCB6aLDmiu0hdYe3ss6cQlkZFu0krTaqpkDafphfBi92ds47oqVdfhs0gO7jU 0TbfiXvbEEQpG0gC+ZslYxG+8iWSROeiB4/lb4bOsHj0EZA48ZcZqHZz1aqi4mMEkzsv 8rUPDmQpkJSXzxjCZ5aQlzPXyTDnWMtWn1kc5IROYWfScbSRsaiplx0EIwfn0u3d93u1 tNPsoBMCxZO9Wf+YlSeN7Kj9ETvekCJ0ie4AkFwlENxFBcRy/xvpyHjvvMmizq+LuAst VfRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EOSzSixAzta/FPxWAggSKFD1+tlg1/eL2RD8SSdD1EU=; b=azK6IEVepV/RuV/miXs6RYIhnRn3QA9xBNiDoVqrPAyHuX6EsC9PiVA2xdH67FO/lA RPelwFwWFI+mcO8tP3NK2PY52avkj4z5uR6lldNoZCC8Esy+Xyw/huN7RIK6KDshkt73 IeUjQChPGETIZoYRoWv9Phq9XAEWymcFsfhbT0mGFG18t10tyG5aemzuWpzlFjnjSTQw 4lERXTqHeYz31mcWDdQYN6HmPiY2WG58daXTNZJ880068Ifdb+JVAsrK6F6LNLv32wyK 2k6I+ihbDOoK1FQz7q4RhO9CEyxleDeuvHTyrIMhibqfyveuX4vNDD4DiBafDhVhs7Du DFiQ== X-Gm-Message-State: AOAM533a81YALV7xPpclbei275NGKwkNqt6eq58X6rXyJRwKL3xu5qeq UECeK/bB8uqnu0wanzCxSD0= X-Google-Smtp-Source: ABdhPJzQ+R8PszHv9zeuPLpGPAfVl7rJ7bdlFdtyccvmCXqLPsOM7fPKgzvRy2GuU0Lf5X619bMKfA== X-Received: by 2002:a05:6000:144d:: with SMTP id v13mr37432655wrx.73.1619629511740; Wed, 28 Apr 2021 10:05:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 08/30] target/mips: Declare mips_env_set_pc() inlined in "internal.h" Date: Wed, 28 Apr 2021 19:03:48 +0200 Message-Id: <20210428170410.479308-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Rename set_pc() as mips_env_set_pc(), declare it inlined and use it in cpu.c and op_helper.c. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v4: mips_cpu_set_error_pc -> mips_env_set_pc (rth) --- target/mips/internal.h | 10 ++++++++++ target/mips/cpu.c | 8 +------- target/mips/op_helper.c | 16 +++------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 57072a941e7..04f4b3d6614 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -219,6 +219,16 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) +{ + env->active_tc.PC =3D value & ~(target_ulong)1; + if (value & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } +} + static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8f76f4576f4..a751c958329 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -327,14 +327,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState= *env, static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D value & ~(target_ulong)1; - if (value & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } + mips_env_set_pc(&cpu->env, value); } =20 #ifdef CONFIG_TCG diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b80e8f75401..222a0d7c7b3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -993,24 +993,14 @@ static void debug_post_eret(CPUMIPSState *env) } } =20 -static void set_pc(CPUMIPSState *env, target_ulong error_pc) -{ - env->active_tc.PC =3D error_pc & ~(target_ulong)1; - if (error_pc & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } -} - static inline void exception_return(CPUMIPSState *env) { debug_pre_eret(env); if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env, env->CP0_ErrorEPC); + mips_env_set_pc(env, env->CP0_ErrorEPC); env->CP0_Status &=3D ~(1 << CP0St_ERL); } else { - set_pc(env, env->CP0_EPC); + mips_env_set_pc(env, env->CP0_EPC); env->CP0_Status &=3D ~(1 << CP0St_EXL); } compute_hflags(env); @@ -1036,7 +1026,7 @@ void helper_deret(CPUMIPSState *env) env->hflags &=3D ~MIPS_HFLAG_DM; compute_hflags(env); =20 - set_pc(env, env->CP0_DEPC); + mips_env_set_pc(env, env->CP0_DEPC); =20 debug_post_eret(env); } --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619630082; cv=none; d=zohomail.com; s=zohoarc; b=XU6eTMge+h6Hahap9VRDpjVbvUflnP/XfeqOvl0zQOJ34duGo0HyPIN3rMxu5Hogh4dBw2CC7sVrIzhpKtQ5QDPUnuUFi5pUeydZQpoCrAEd1vAq7+XNZJtnIcx4u8S82Gg4h12zLReUm9FH+Hx9pWcgkIQq3B/Wck7C4lNgHvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619630082; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fVSsRIdWjTO573Wp4QCX8aQdVwf3iswd3WsuMon1AAs=; b=G/Liz+xQI/sieHsDUfHyhzqA3OPY89tT6sEWhTdsTd2j2XfZ06o9IAZzc2YBbkoR6tVFQlTXsJybvGpnMhsWjZeJpthMYoilw1XQ4UaVl1T6p+HL5lTy92LtvDpSIxge9pKI3OLp4j5V3RIPpUdSbuhGwbHcMeHslAO+5KVLwFU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.zohomail.com with SMTPS id 1619630082841303.3657881658878; Wed, 28 Apr 2021 10:14:42 -0700 (PDT) Received: by mail-wm1-f41.google.com with SMTP id b19-20020a05600c06d3b029014258a636e8so5089206wmn.2 for ; Wed, 28 Apr 2021 10:14:42 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id o17sm243715wmq.47.2021.04.28.10.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVSsRIdWjTO573Wp4QCX8aQdVwf3iswd3WsuMon1AAs=; b=DVsvn6rVWYLt16vA/ur6Vu/DOjWdXnD+nTpNs/BqPeuxk/AZXd6ib/S1r/kldtPc0T 0rtMBacmw4rxcBQWZ7K9+DQoHuXlsm9ZV5kxKoivhcJyz3KWwC2pLSinoisOrE6uvywk 2NDac1bXpcyQqPTXTo8z8PQKLD/2U67/dV1B6NzJwyW3wX3msPYcfTiA8I2kMG01hgkm h8T0poTJMfdkT/yNYo0F+DVPMqlI4R2bK8on1rz6qc4L0kly7faFeGCfP9q+IwAfn/sI SDYwxd3tTM6XUFfHLWa+bKo7DlohozxZs5MiJ/WPDkPirGjp+nIOR744O1/UqIuNSjGV y8lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fVSsRIdWjTO573Wp4QCX8aQdVwf3iswd3WsuMon1AAs=; b=H5ELtY40r0Y65qf2JK06OB+eM9eP9YTvkEc6ScKvI5hJAnNlAmTFTq1+emcp2EkdQP W8xbK4lf2hH9vUfBvk3CM0smIQaJvSM3SCldN6qjVhokhmhGk5Wd7jTrkBcP0YO6aikM 3yKjtvzFXMHLVTIg989YF4+aAsFKhoDqUhpEkezAwuqYM7IevU8NaCSKaiUsooFtqUNa g2jUgsADcxmfAHmGkyJTieLLFQkWNhTW6RAqCb2F9GxHbOcnDj5/9fLcNdm5rFjX6bQ3 3sr7u8Bs656GCsbn1H3CbfsFwnXEDp6wGsHWOZi9pkdXaPieOyWpb0Yp12pmfvJNDbys Ipww== X-Gm-Message-State: AOAM532SJSnJMT1IBMz3/hTRhu12zm09vUknO8pOLBVVgm0vTJIZiZ2E +YVHmeuAPZFpjucYnIICjQuQCvtP529lXQ== X-Google-Smtp-Source: ABdhPJyTqpy0HC5hDBvRtqUL49sURErddUHzRGMc8hC0f5QOakjby5qzf3rEw+vYGJhMm+1Iwkwtgg== X-Received: by 2002:a7b:c74d:: with SMTP id w13mr5908334wmk.25.1619629516585; Wed, 28 Apr 2021 10:05:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 09/30] target/mips: Merge do_translate_address into cpu_mips_translate_address Date: Wed, 28 Apr 2021 19:03:49 +0200 Message-Id: <20210428170410.479308-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Currently cpu_mips_translate_address() calls raise_mmu_exception(), and do_translate_address() calls cpu_loop_exit_restore(). This API split is dangerous, we could call cpu_mips_translate_address without returning to the main loop. As there is only one caller, it is trivial (and safer) to merge do_translate_address() back to cpu_mips_translate_address(). Reported-by: Richard Henderson Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/op_helper.c | 20 ++------------------ target/mips/tlb_helper.c | 11 ++++++----- 3 files changed, 9 insertions(+), 24 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 04f4b3d6614..e93e057bece 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -148,7 +148,7 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type); + MMUAccessType access_type, uintptr_t ret= addr); #endif =20 #define cpu_signal_handler cpu_mips_signal_handler diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 222a0d7c7b3..61e68cc8bed 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -287,23 +287,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shi= ft, uint32_t shiftx, =20 #ifndef CONFIG_USER_ONLY =20 -static inline hwaddr do_translate_address(CPUMIPSState *env, - target_ulong address, - MMUAccessType access_type, - uintptr_t retaddr) -{ - hwaddr paddr; - CPUState *cs =3D env_cpu(env); - - paddr =3D cpu_mips_translate_address(env, address, access_type); - - if (paddr =3D=3D -1LL) { - cpu_loop_exit_restore(cs, retaddr); - } else { - return paddr; - } -} - #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ { = \ @@ -313,7 +296,8 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg, int mem_idx) \ } = \ do_raise_exception(env, EXCP_AdEL, GETPC()); = \ } = \ - env->CP0_LLAddr =3D do_translate_address(env, arg, MMU_DATA_LOAD, GETP= C()); \ + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ + GETPC()); = \ env->lladdr =3D arg; = \ env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ return env->llval; = \ diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 8d3ea497803..1ffdc1f8304 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -904,21 +904,22 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, =20 #ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, uintptr_t ret= addr) { hwaddr physical; int prot; int ret =3D 0; + CPUState *cs =3D env_cpu(env); =20 /* data access */ ret =3D get_physical_address(env, &physical, &prot, address, access_ty= pe, cpu_mmu_index(env, false)); - if (ret !=3D TLBRET_MATCH) { - raise_mmu_exception(env, address, access_type, ret); - return -1LL; - } else { + if (ret =3D=3D TLBRET_MATCH) { return physical; } + + raise_mmu_exception(env, address, access_type, ret); + cpu_loop_exit_restore(cs, retaddr); } =20 static void set_hflags_for_handler(CPUMIPSState *env) --=20 2.26.3 From nobody Fri Apr 26 21:14:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619629524; cv=none; d=zohomail.com; s=zohoarc; b=g5yYIj+hBjyQ6i7jTcyOve5bt+7C2OKZwQE1PuqB0T3UhGgtB5E29kIkxDgJOonQxt4WSxX+J0JhaPzTQ0x6KBM0PGz2yuSNV1U6Jeh6WrK3edL/ZIWVGUZ3GGlvboylIzc9R2Nhk/9yyScpL1kWELsfYewzjT3pzt4R4OXFv+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629524; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/l+wNVz0p8CKuO/J0+adTcaPg0pyoEzc7P/c9rJpHXk=; b=LTF3DxXYYC38yBw00rXlhQQnDOABjcw62yZvbA1+h47GA3TJDAWgGxK8GEsrGzJWOAGt4Ntc6heDmC3t6xLs/4lVUPOjniWY+vxOEPI6XkpCwzANPotW1GX3HxOhI+rz070LQqNrR0EkhkEfkJ/pfjMBxNLwkv+mwV2oiYFJ0Qo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1619629524509901.6763986086186; Wed, 28 Apr 2021 10:05:24 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id e5so35179719wrg.7 for ; Wed, 28 Apr 2021 10:05:22 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id f22sm282930wmj.42.2021.04.28.10.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/l+wNVz0p8CKuO/J0+adTcaPg0pyoEzc7P/c9rJpHXk=; b=qUw6js57fEQVPv/bZHlHy99YuRL7evFKjcW3NxE7+ZASxBIM7utZF+/P8KNsROXP4A p/e/L+5zSYPrE6Fk23QgHQRyx0AcxPgCofGXhiySXPgSz5z/F4YfVN2ZPSSP3KJxcifu d1gamI7WD7e7Nne3GN55wUe32JCt9Z1Z3Yk/I+adWKY8qh4Jkt4HpWGO2JjCVxGehjHy tuxC9El75dgqUXYPKd2oKxK8ZZEGpb/23Qo62qX0alVsqrvli9dF6GHpGj4XYz4Vuaz7 kTamNTst7sEzF0KLe3tSvKZ3jTsSSPZA0cEk6QK3fbjkf6m6Mxnp6IVsjBMI9juWe4dr 3kQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/l+wNVz0p8CKuO/J0+adTcaPg0pyoEzc7P/c9rJpHXk=; b=q+I1JihwJzlZc3c0bASftG48u2uGsG5KMHLUvASVPDzg/Zit/xfm82laeBH2Bik3D1 tOcCvAWSLicyX72q63GsqtZtqnl39IJBxi+x5zJImIGaauWClJp89QQM141EbboH8wQl +RdsB9cjt5n2yvuJj/ROUDnMzFabj3QQMcbTSeHa+7PrqaFtM7R5uj0+f9b/s+kW8+ee i9C/hEkK//DLwkEfHdhtot5UfIZvCGXDOLle8ZGMUDbnS6z27+hQBjPu3pxobzJwOLjh bQjKXDmdnEvxe5qQa/HCS1s+umJof69LcaAx2PsA8rfSlUyco523o8jgiCmbBw0PdeRJ wvEA== X-Gm-Message-State: AOAM531bfxrU7mr1sf5zk6BRHuHZmPHhAaVM1WZSQANpr4N+RPLRplvt iwgQwNaupGQvdtlUoRNpBsg= X-Google-Smtp-Source: ABdhPJwkYVj7lJqJJCH0e+81mCYyeZ9G9V6cqAeLGeg2PcOLnD2uZU9jJ/ilJ4N9KkFEFH6C0iPNUg== X-Received: by 2002:adf:df90:: with SMTP id z16mr15254779wrl.132.1619629521643; Wed, 28 Apr 2021 10:05:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 10/30] target/mips: Extract load/store helpers to ldst_helper.c Date: Wed, 28 Apr 2021 19:03:50 +0200 Message-Id: <20210428170410.479308-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/ldst_helper.c | 288 ++++++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 259 ---------------------------------- target/mips/meson.build | 1 + 3 files changed, 289 insertions(+), 259 deletions(-) create mode 100644 target/mips/ldst_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c new file mode 100644 index 00000000000..d42812b8a6a --- /dev/null +++ b/target/mips/ldst_helper.c @@ -0,0 +1,288 @@ +/* + * MIPS emulation load/store helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/memop.h" +#include "internal.h" + +#ifndef CONFIG_USER_ONLY + +#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ +{ = \ + if (arg & almask) { = \ + if (!(env->hflags & MIPS_HFLAG_DM)) { = \ + env->CP0_BadVAddr =3D arg; = \ + } = \ + do_raise_exception(env, EXCP_AdEL, GETPC()); = \ + } = \ + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ + GETPC()); = \ + env->lladdr =3D arg; = \ + env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ + return env->llval; = \ +} +HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) +#endif +#undef HELPER_LD_ATOMIC + +#endif /* !CONFIG_USER_ONLY */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); + + if (GET_LMASK(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } +} + +#if defined(TARGET_MIPS64) +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); + + if (GET_LMASK64(arg2) <=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK64(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) =3D=3D 7) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + mem_idx, GETPC()); + } +} +#endif /* TARGET_MIPS64 */ + +static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; + +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); + addr +=3D 4; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 4; + } + } + + if (do_r31) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#if defined(TARGET_MIPS64) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#endif /* TARGET_MIPS64 */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 61e68cc8bed..7a7369bc8a6 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -285,265 +285,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t sh= ift, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 -#ifndef CONFIG_USER_ONLY - -#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ -{ = \ - if (arg & almask) { = \ - if (!(env->hflags & MIPS_HFLAG_DM)) { = \ - env->CP0_BadVAddr =3D arg; = \ - } = \ - do_raise_exception(env, EXCP_AdEL, GETPC()); = \ - } = \ - env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ - GETPC()); = \ - env->lladdr =3D arg; = \ - env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ - return env->llval; = \ -} -HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) -#ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) -#endif -#undef HELPER_LD_ATOMIC -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#define GET_OFFSET(addr, offset) (addr + (offset)) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#define GET_OFFSET(addr, offset) (addr - (offset)) -#endif - -void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - - if (GET_LMASK(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } -} - -#if defined(TARGET_MIPS64) -/* - * "half" load and stores. We must do the memory access inline, - * or fault handling won't work. - */ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK64(v) ((v) & 7) -#else -#define GET_LMASK64(v) (((v) & 7) ^ 7) -#endif - -void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - - if (GET_LMASK64(arg2) <=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK64(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) =3D=3D 7) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), - mem_idx, GETPC()); - } -} -#endif /* TARGET_MIPS64 */ - -static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; - -void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); - addr +=3D 4; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 4; - } - } - - if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} - -#if defined(TARGET_MIPS64) -void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} -#endif - - void helper_fork(target_ulong arg1, target_ulong arg2) { /* diff --git a/target/mips/meson.build b/target/mips/meson.build index daf5f1d55bc..15c2f835c68 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -18,6 +18,7 @@ mips_tcg_ss.add(files( 'dsp_helper.c', 'fpu_helper.c', + 'ldst_helper.c', 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629528; cv=none; d=zohomail.com; s=zohoarc; b=SFKvt9gbMfX6Ebdgq/yZtUGut3mv76QB+y2rpC5BADh1qjukpMDL9ubQJ9+98vsrITpe2YB5wItVcYRdGj6fGP4CHWBuJ5Nvc1EscBqdUMMccbnbH49A2aW+6CiFKVpcYL/EYgaPAJ0iQe9191IwqDYCAQLSOy6Q1uaLKRsa5OE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629528; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sZBW30FOGnAuhkbH2UFK9YLL45nz87Al8a/KOWE0Q44=; b=OELzKjECtvRi6tIrt/cCFGL/WAHcgy9pvEOZex5YzmTClYndOaA7RSUAtxCloNjN+peyxv7cei6kefAh4l5QUGtFPJp807mPAIiQB10DwNn2IMoRA8svz2OakQdnj8ZWLK9VQfxOFC8qpSH24V7IePSKoGVGiHFy1fdAKPQ/uTQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1619629528485519.3327124270198; Wed, 28 Apr 2021 10:05:28 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id d11so5986603wrw.8 for ; Wed, 28 Apr 2021 10:05:27 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id t206sm382523wmb.11.2021.04.28.10.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sZBW30FOGnAuhkbH2UFK9YLL45nz87Al8a/KOWE0Q44=; b=dvtzMWZ4MZslUc0oVHLASB1hI6oxKmEL/3NHLMUaELU50dD2xIjub/dASUQNH1lTJ7 lWS19v8TWpKYSb6dDNSyjKcGMGWGtJA91/HDnQ4EITl8jbvMvP2j+ZNgU0/AwVCXYI9u u3CJw4JP94g/POe9t5pjf0iS1yuAWEuZA8pRTpBlQ4hyU/oA95oiwKcA6sQpM4+/Nu50 mWR+AZXhwQR9H+mB7LowQtFc0it8HQJw28roggkQECO1cHuN8pLsOBRSZFcESa6zGNl+ qizYFrdnv2qrh6AZD18jrr8NBARCqhR9S8thAZwgy4KHtCxo6mz2O8eWhiKlt8t2IjG/ 3tpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sZBW30FOGnAuhkbH2UFK9YLL45nz87Al8a/KOWE0Q44=; b=P2ksetJVXE5DzwPPjEZejJ37DqtGfT5obzPTvfh2ic4G1zPpVXhf0xeud5yUqLiQq0 Kj2z7LWN5+teUxlf5vAIf8MfsOe2fC27UGFJzqqYR6dDuDeypVBLH5yxkn2JrS7qi2wj DeT5RvujvnwlnYto4F9aWtxuwF/haw+KmbmhQAyKO8sFp2oGU8cBg+FenCSQVhaGzx0T t6tVmUY4ebDorO52QDGaSCnuwEUORv5mxGeWgVJN7BiUWYVYKqMVJEb9KlhVYgtb1m7Z S4reSkXOnshwP05R5rOXky7MgIJvInHdk3xvf1TjsaJQrdD4hSKH4RCsUE2GJYATrSwP M4bA== X-Gm-Message-State: AOAM5335c7lKD3QILjzEpM+VDFJIZnQTOsn1BZP6ZjWp32eNCwc5F3Bb tuC1WrACiPF5NiYYaaqR9MA= X-Google-Smtp-Source: ABdhPJxyxD6fDOXcltF3ejLDUKYOIiCjYjakrmwZ7crNXSDOO1z7EHYsmLxgqHVePVdPVDRosV8dpQ== X-Received: by 2002:adf:e40c:: with SMTP id g12mr825079wrm.11.1619629526292; Wed, 28 Apr 2021 10:05:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 11/30] meson: Introduce meson_user_arch source set for arch-specific user-mode Date: Wed, 28 Apr 2021 19:03:51 +0200 Message-Id: <20210428170410.479308-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Similarly to the 'target_softmmu_arch' source set which allows to restrict target-specific sources to system emulation, add the equivalent 'target_user_arch' set for user emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meson.build b/meson.build index d8bb1ec5aa9..1ffdc9e6c4e 100644 --- a/meson.build +++ b/meson.build @@ -1751,6 +1751,7 @@ hw_arch =3D {} target_arch =3D {} target_softmmu_arch =3D {} +target_user_arch =3D {} =20 ############### # Trace files # @@ -2168,6 +2169,11 @@ abi =3D config_target['TARGET_ABI_DIR'] target_type=3D'user' qemu_target_name =3D 'qemu-' + target_name + if arch in target_user_arch + t =3D target_user_arch[arch].apply(config_target, strict: false) + arch_srcs +=3D t.sources() + arch_deps +=3D t.dependencies() + endif if 'CONFIG_LINUX_USER' in config_target base_dir =3D 'linux-user' target_inc +=3D include_directories('linux-user/host/' / config_host= ['ARCH']) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629533; cv=none; d=zohomail.com; s=zohoarc; b=eWXimBYWdmX+sQRJ7tHp6qVTfMeFI1D209/noJoBPfsXYm594gZ4yd0ZACD+dXU8KXIJ0W28JI/OiLsIKJFQxr5Hs+pCQO99NxIHkZQK+IymRd3YCBi/SL4WKse9FkyDO54pJQC58GOy3HhBkh+z1DBB3+daCAxTxZalhicNiUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629533; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kx/9p01ewXbbtjHOZt3V0DD4dy9s/DfXp7a3bZduRsU=; b=NWfwY8fyZcj02+HpVv/F/PMjYXXMz7ZsM6vibKmsFnFIPRBp+ZJVQldxCKQdRBVAUqjQlPaDQjoVlsmnLqUu0TyyeK9bpbiGLd9vJs9v22uo3r1pCjTNn0HXYQDzkGjAVs8fVFKyBMNNzq0n3pCPw0+uDqwNTqAEVsID88+yqC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1619629533185806.5629926921068; Wed, 28 Apr 2021 10:05:33 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id q9so9682503wrs.6 for ; Wed, 28 Apr 2021 10:05:32 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id r11sm446083wrx.22.2021.04.28.10.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kx/9p01ewXbbtjHOZt3V0DD4dy9s/DfXp7a3bZduRsU=; b=Y7eo0tl7flDM1EiecSNBqpVJBJnCtl3l/emqgjSaQshyn0+Qb8hepFk9ssLLH6CCf4 pIireY3+rB2AEWu1uppAdhNyPVU474/eSDUeCRyfFPTGGrvbrm6wjv4HkbZojaNZ76mU dh/bnRrJhlO6xyFs1NArmd01yXycqP5qUb5/gA+del0w9PmpbTgJUjGVHjM59fHp2VDa sVFwmEzwHWirvTfoaDR+eIzxY1aPxwjuD2x8UM57OLTB8gvNabrJFuxKyaJvs2lrJvuD xaRtKLWkybnJCKc0wnuZsCwOBYwgnNqSidSGsRtHgGoZxjFgh3h/VZM1ZdQH6KS2PxYm THLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kx/9p01ewXbbtjHOZt3V0DD4dy9s/DfXp7a3bZduRsU=; b=Mnxk4a2fzE7SlI1Phk69IUXQkwxD5FbzNkHlq5TbBTt1tyiAciJMtGYLFkyR0Hp/ac SYPKKFiIjm3qqKXHRo2dZCcPvX5rJU1g9xtQYDAUIHHjISxzmMeFP/AGC8mPkx79xFWd Cq3b6oKW6BExqNjMlo797Lo2VpyUqsHKEXCQHcC2yJpt+w/WIBNGMDANTtlBemkeJddR 4/QZuc9abwHYamAMQh29mAoZIuVN+GMk0GJOJNoD+SwGzdtbtov2tX7YE5oyPM55jwMB RFtebrrNcn1bdUGwYtaGrFPeM3Kr0ieS1unjquy0DR/au6piuOuiqKKz9iBldpHZQuVN Xqbw== X-Gm-Message-State: AOAM5303b85IfiGJOILSv6qT+lJqdycxlHItYztnkUiusAcstwOldLav mT0vr8gn+KCSeZ+jiskaJLc= X-Google-Smtp-Source: ABdhPJz+ydjIG7Js8b+/XNgwLNCx4W6h7IohSbmsu1xf11Nazvke4+W5qkPeubXC/xu/6OSngwlDew== X-Received: by 2002:a5d:52d0:: with SMTP id r16mr18563621wrv.358.1619629530987; Wed, 28 Apr 2021 10:05:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 12/30] target/mips: Introduce tcg-internal.h for TCG specific declarations Date: Wed, 28 Apr 2021 19:03:52 +0200 Message-Id: <20210428170410.479308-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 7 +++---- target/mips/tcg/tcg-internal.h | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 target/mips/tcg/tcg-internal.h diff --git a/target/mips/internal.h b/target/mips/internal.h index e93e057bece..754135c1421 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,6 +9,9 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" +#ifdef CONFIG_TCG +#include "tcg/tcg-internal.h" +#endif =20 /* * MMU types, the first four entries have the same layout as the @@ -77,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h new file mode 100644 index 00000000000..24438667f47 --- /dev/null +++ b/target/mips/tcg/tcg-internal.h @@ -0,0 +1,20 @@ +/* + * MIPS internal definitions and helpers (TCG accelerator) + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_TCG_INTERNAL_H +#define MIPS_TCG_INTERNAL_H + +#include "hw/core/cpu.h" + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +#endif --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629538; cv=none; d=zohomail.com; s=zohoarc; b=gINYHfscCwGsEaqqoxx4/UYC5jGJ78PHDot79Zawe6E13QwGTXwLNoc9r3EMgaU14wpxYOFAwS2nrNII2BFz90kzGWAc5Owz9OO5yWdQLLX2pRSddP1PdYppxy9DdE7CKr05nWg1e65A/zXpB0YY5Xqz5haAVLaIfR7L9+CJM1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629538; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aOOn5441pcRfPUiL4gXBm9CusRAuENaccyMye79jHuY=; b=Fp8z0hcPfQVu89dvETsdoPfHjgtZb7inbGQOyKO9wMH7L0HctNB86iH7kDTkmplnSRvAnj+KS4yVCsoB9UDa3gnCFf2KQ3KxGkSqtw0vRzmaSdMiTPh96jM8ht/VTfXg821WTVwav3OOmnctVFzjt+8MzbU9tll0clN/FFgB3GE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1619629538087384.5820239815739; Wed, 28 Apr 2021 10:05:38 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id t18so6249090wry.1 for ; Wed, 28 Apr 2021 10:05:36 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id t7sm460285wrw.60.2021.04.28.10.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aOOn5441pcRfPUiL4gXBm9CusRAuENaccyMye79jHuY=; b=Z0tSAEFI6kYmFOx4S1Y6JI2+pN7eBczEWvQzcwjgHcheFNRoYCRoWpzpHQ3YKtHdkS 9tSvKZW9Bir4x7h+U3HNONRv3aW7zrEV4c4szV9CrXV0LqA7WElbGcZQNeJCpfkgWlnN q/E6H16inR3qQ+gIw9h/uO//PNbi7Rj+Ga4i5uiSmoJlqPnd9EEMF0VF0ibvcoHqRI1a E/EBmruLztjokDvlMLZ5hUPMYqVB8URmd9uHaP4cAjUmEcHT+EBrBPhMx+yfxlO2qEgF T0KXkOJA9YFUR+fKKSpvktd/QWGnDpmKS7bQ2C2V+RBxh1uGon7u6WsNJDzx9AA9MsjA V8AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aOOn5441pcRfPUiL4gXBm9CusRAuENaccyMye79jHuY=; b=bxBwNxT/gcgS0wcGSgwJZdiVeIcY1shwleQ5nao4ITeqzbzhO5RsEqre22kdmzQgUE 8kAwgQnW+y6aV6PRpezDZRzEtIJouNyQ5zrJDomDFRJQi1WHK3XdyLfwqoA7hoHJmwti yZd9EUlEnTASUjRADiwo6oxUydDTScfCLery16wY/KVzG8Y/jdi/hAtZ88YwpPgXFD7p LKwYp7vn+AJ18fHJlFvWDzwuB4Gk7vOHe1BxZu5Yelt1tD3TMXp0+0yAM07rdVePXTw3 xltntOiuR8SWsTINuDJmdDpUlpTmStwuCGVaW1dwtf9BFgUDGct0AoBU44ysZ+5a53A8 Jr5A== X-Gm-Message-State: AOAM5331zdlQCN/2ypuWqpAtWmN7AmdHMJX00iQurbRVL190ZdLbdEYb QHCjdhlylJd2gk7P+ZgDM1g= X-Google-Smtp-Source: ABdhPJwDeRwSjy9iWd7kSd3BsIAiOyJ2wUqVhXBa9ekdipC8IuARpOfeheumpd0YLMJD1lJEVJmDoA== X-Received: by 2002:a5d:570e:: with SMTP id a14mr24184426wrv.254.1619629535693; Wed, 28 Apr 2021 10:05:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 13/30] target/mips: Add simple user-mode mips_cpu_do_interrupt() Date: Wed, 28 Apr 2021 19:03:53 +0200 Message-Id: <20210428170410.479308-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index =3D EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/user/tlb_helper.c | 28 ++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 5 ----- target/mips/meson.build | 5 +++++ target/mips/tcg/meson.build | 3 +++ target/mips/tcg/user/meson.build | 3 +++ 5 files changed, 39 insertions(+), 5 deletions(-) create mode 100644 target/mips/tcg/user/tlb_helper.c create mode 100644 target/mips/tcg/meson.build create mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c new file mode 100644 index 00000000000..453b9e9b930 --- /dev/null +++ b/target/mips/tcg/user/tlb_helper.c @@ -0,0 +1,28 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/exec-all.h" +#include "internal.h" + +void mips_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index =3D EXCP_NONE; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 1ffdc1f8304..78720c4d20a 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -965,11 +965,8 @@ static inline void set_badinstr_registers(CPUMIPSState= *env) } } =20 -#endif /* !CONFIG_USER_ONLY */ - void mips_cpu_do_interrupt(CPUState *cs) { -#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; bool update_badinstr =3D 0; @@ -1272,11 +1269,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } -#endif cs->exception_index =3D EXCP_NONE; } =20 -#if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); diff --git a/target/mips/meson.build b/target/mips/meson.build index 15c2f835c68..ca3cc62cf7a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,6 +6,7 @@ decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] =20 +mips_user_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -34,6 +35,9 @@ ), if_false: files( 'mxu_translate.c', )) +if 'CONFIG_TCG' in config_all + subdir('tcg') +endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 @@ -52,3 +56,4 @@ =20 target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} +target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build new file mode 100644 index 00000000000..b74fa04303e --- /dev/null +++ b/target/mips/tcg/meson.build @@ -0,0 +1,3 @@ +if have_user + subdir('user') +endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build new file mode 100644 index 00000000000..79badcd3217 --- /dev/null +++ b/target/mips/tcg/user/meson.build @@ -0,0 +1,3 @@ +mips_user_ss.add(files( + 'tlb_helper.c', +)) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629548; cv=none; d=zohomail.com; s=zohoarc; b=PWjKsd9yCA96X6zq/APEv2XUCvBZVDXW/SjRv3De7T4leRhb8Js6VDJkzpv38wuigiAljxxJyD4S2nSzhk59mUYlpvJ3Zzon2/Oz35t978enk8zCtVaHygtaXKEleToC/hiAxZaaJvgqy/2GyQqt0DO2Vk4jTXWPjvs1RDCNv50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629548; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7OS6JG9BL3+LnpLCM/Z0MR7VlobeUEBPsxpBEJslEbA=; b=KkEBiaDsCob9zpGbOjtvrMrFOou7Kr1LTipuI0hw2nIIr6p9nhjDO9mUMfDHnmCD7TtA0WPf/VCOttOIwxu5Fl1SeFvtBatrxiFSIBkqQqOS4b+wrNTHU/KUZ8YBWuMoc/5w7+w6bMZeXtwO0X1zJd/Fe17YFXhhd+Ba/hGgZjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1619629548799873.391862793033; Wed, 28 Apr 2021 10:05:48 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id a4so63854442wrr.2 for ; Wed, 28 Apr 2021 10:05:48 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id t20sm6774853wmi.35.2021.04.28.10.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7OS6JG9BL3+LnpLCM/Z0MR7VlobeUEBPsxpBEJslEbA=; b=i0M8/cDwR59x500XlqqbXm/fDCJJXLwyw7qcQR4qYH+qS9TWIuLe6ddSSp4TOeBqBR f93VWlsykeXhH+aYqND9xOq88SaVHYSuOjJfJhR0Um3lyHSzkl5rxCf3ZvgU1jUORKZd 3kcPa55ljxBz0gE5wenShWWpiwTveBrJj+cv5mIPMJ4lC9Jt3onWP8s8D4amN4mwo26K fAdYrgwvJLE1eF1uStXdSKPiDZBCM/xMJn2sG05aaj4Jkr+JjeZd7IBSMqtzP08vwNBy lorCHL/M9n+NKkk+CqMF3FBQc1jGXz58iIB8H1Ngp/g+GepE+LZiBsLKQaa4mj20eQxp 1f2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7OS6JG9BL3+LnpLCM/Z0MR7VlobeUEBPsxpBEJslEbA=; b=YOPg7arNaj+1I+q2rOULpNP90VpR5IcdKt2EXY9FV1VayQW5SovD5GMhfj0lyg0R4j b5LgZZBrPgdx2xEmDQ50eFi1e3qCvlxHTGu8h/DOH6o211rw8c3FAIgy2MeJxPJJzlEp Vr5XSFg1ivE1WIauqvZHLHuVQO5L4M7m8u0Q1Hf/2Ish3eDY+48QM5YpFnzsLvUt8Q4K tBC6TkERnKEkfeJ6tqb92KCxBreqH+I608uUVVynQqaGeTqHUDdEu5MCiuRD9yi8Qb6W i+EfOqT7tPbV+cWic/Jya9S+CyyW9cQcJmEV1+M99qUVW6c+fS30Z2JcDzUUoDqMQNyi b+7A== X-Gm-Message-State: AOAM532iBO6FYvbyA09iwpOsKeHg3EsailXTAY/8v0ZBoZy6MeN2iXdx om6Vu9+4RgqDUW0NFwqke+k= X-Google-Smtp-Source: ABdhPJwCKKP04wpsCRscD1BqWoRrZbSQnXQdMVgtt5BRv7r00fKJ6uqE68JbYoszCcPkPZLNtLz6Vg== X-Received: by 2002:adf:9245:: with SMTP id 63mr35960296wrj.324.1619629545517; Wed, 28 Apr 2021 10:05:45 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 14/30] target/mips: Add simple user-mode mips_cpu_tlb_fill() Date: Wed, 28 Apr 2021 19:03:54 +0200 Message-Id: <20210428170410.479308-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/user/tlb_helper.c | 36 +++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 10 --------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index 453b9e9b930..b835144b820 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -22,6 +22,42 @@ #include "exec/exec-all.h" #include "internal.h" =20 +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs =3D env_cpu(env); + + env->error_code =3D 0; + if (access_type =3D=3D MMU_INST_FETCH) { + env->error_code |=3D EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCP_AdES; + } else { + cs->exception_index =3D EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + void mips_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D EXCP_NONE; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 78720c4d20a..afc019c80dd 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, env->error_code =3D error_code; } =20 -#if !defined(CONFIG_USER_ONLY) - hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -833,7 +829,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret =3D TLBRET_BADADDR; =20 /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (probe) { return false; } -#endif =20 raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr) { --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629552; cv=none; d=zohomail.com; s=zohoarc; b=UYLnn6VNQOMlptIrGBR/uMdT9N4MtMIxP2eiTfJLir7m/ljqtWAx14UuoQxHR0zyBdENc5bguRlLW2blXcGoyRJoMbKcnsUkHIa7OFHfUeIUoiaBFY4s4d4Xj5wZ+NN+Tl7FiZpdVD80nLCNNYkmyowYChU6XbEnzhsyCpwccSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629552; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IVwZ7ZYGcqvI/Dkkcktk2wuADx6ZHHmimEVhHCeRWCA=; b=GbMniLlvMLiidihvdQPucuL7+jLkjmf8T6YYxjr4E+H697FM9QnTFbxom19F3FFpdQ6HOFeVFKuO46kTSZbNI9L/RPZLccGM81yMNpkN9EocKSvaMPPgfoZ5FafmlfLxwZejAmsMGmpIu8IoQg7VLjpILUdVcJn0hC/OE7+vSlg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1619629552538960.4121871351384; Wed, 28 Apr 2021 10:05:52 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id a4so63854704wrr.2 for ; Wed, 28 Apr 2021 10:05:51 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id c16sm438060wrt.83.2021.04.28.10.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IVwZ7ZYGcqvI/Dkkcktk2wuADx6ZHHmimEVhHCeRWCA=; b=TfMkKcPXydgzX4J0810iJjM2celwg0rwx+bd6QVJJ+KJA8Yl7X5aNKQiphMpBOKIOI QiA/osKmJIosS8ctTX2Hr9+Fl7CiKTttEF7NlGwO9Vh2j0rqicTOyRwRDjgD19vzV860 BFUPgByHw1ayEKwO0wyMK9FXIj32TVjK0U4qUXESMKvJnmYZTwpSoQCEdrvVj1VtO4Md PNOPQvd85V+H+77r7xMsVu4idnZ2aYksY65D+O+6UtmtJMOaNnkzOWcP2wpzcyi/RMCf FgHS3E0iyPkMN95Hw1VIQxl3V9H91DKuQbDHfG3wYPIddZNndKuCgJ3xvLBBsyix4xyY ajaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IVwZ7ZYGcqvI/Dkkcktk2wuADx6ZHHmimEVhHCeRWCA=; b=KBrz1fCi/MrJvxQptivMgIPUCZqsltBbjQoM2hb8sJqOhxlPo7IvCADRgT4EbA8sjS asyzFFeAOqRg8QTA/mhd7gGI5lpUnnsQS7xBWUxgGWLOtiSZBiGEFFZ2pcDNsKo/bX3+ rl09VtlP4QD5mTwZRJ1iHp0/jxCxHr5C/xe2O1Y99MEWmTGzEEUP+AwjN1VaStLGoXQ0 WT5QMJ2PYU/Pmb7yMdt0OSwBaC1h+VzpSJx9v2w19HoVv5AyBoRZxQfL7pW8PnMsutgT aIBwPDPKwJOykHVGkiRV6DPnytxHSCJZQhJu43NjymDsYS24e00wID4PWeF8A2ALMetK 3ObQ== X-Gm-Message-State: AOAM531sowy+XWF1DdykPzFqBAlHicYwgpZLr+DHMK0xIFb7J2bK4APV R7q0UbAB2EBIZf50PmO2z/E= X-Google-Smtp-Source: ABdhPJx6jfpmbwEA+AgtydXhKkzKx90XlLw1YDZMxkrM9p9cXwaiPqYVdrmQS91OtQmxEBM52T6ZFA== X-Received: by 2002:adf:c70b:: with SMTP id k11mr38160932wrg.165.1619629550299; Wed, 28 Apr 2021 10:05:50 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 15/30] target/mips: Move cpu_signal_handler definition around Date: Wed, 28 Apr 2021 19:03:55 +0200 Message-Id: <20210428170410.479308-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have 2 blocks guarded with #ifdef for sysemu, which are simply separated by the cpu_signal_handler definition. To simplify the following commits which involve various changes in internal.h, first join the sysemu-guarded blocks. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 754135c1421..3c8ccfbe929 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); -#endif + +extern const VMStateDescription vmstate_mips_cpu; + +#endif /* !CONFIG_USER_ONLY */ =20 #define cpu_signal_handler cpu_mips_signal_handler =20 -#ifndef CONFIG_USER_ONLY -extern const VMStateDescription vmstate_mips_cpu; -#endif - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619629556; cv=none; d=zohomail.com; s=zohoarc; b=g+vK/IFbe1vYUghHdAIYIvJr82D2XLZ0M9jgBDBV4FHZZiMj/dg49ttwr02K/ekhgGkcr9wNXOBYAXwrUuUAjTgujMioCevkXkwtEEkRL9Uy7n2LOAnLDHMczWM8W0hqi/U6P02yNG8au9aVH0u6wenK79jZ3h/s5osHMI0rfAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629556; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2Pw61SyIs2pPxJ556dFiJw8eBQVZJG1ECBOw/xVsIRc=; b=IH98nchdSbvZumUK7lk1l9+pORkKZD5nYslH5/gUDiybY0oQ6Mo9jXsJR27vSO88W/kIylJJ7AA/IDpJ5mZlmvOcC9Rdcc5LDJ3/zmm7NHB75Hju+9cT98JnFx3y1t1g2RuVjceBUMdXgfE33o8TnkcIg7s1hIR6CSFic6VPT/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1619629556932907.4612814065637; Wed, 28 Apr 2021 10:05:56 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id m9so51091390wrx.3 for ; Wed, 28 Apr 2021 10:05:56 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id k16sm315548wmi.44.2021.04.28.10.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Pw61SyIs2pPxJ556dFiJw8eBQVZJG1ECBOw/xVsIRc=; b=lGoBYgDcoMNRNFT6oNpSUS8+oknGkn6/MSiVENlkehBs8T27n1R1LCkiWawqaS8kVL cX+un8M22WWgVt8xziSMmyZCW/hWt4cK8Go2ANP93Iw0OH4W1vw/bPDT57AYax4xuUCU S5I4PJK3FYLpUsgMMEEv6McCdYG7jKj1bLMaibB/EUtjo6lZ6ILSRI/VVBE4PzP3nXTR 6s5L3PWHh4basTYfE2GYqfix8kR0HPPluZGw3qghbfGrReCsdH9w2AG0p6UaWiAweD+c sGMAjFjKYDYl0ZgbZHUBKOEm1aE1r6BtZZccPOUEf6YZ6CuyixBkeXtj/+UVQIB9iITu n0+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2Pw61SyIs2pPxJ556dFiJw8eBQVZJG1ECBOw/xVsIRc=; b=gi346gFVKWg3IPJq49XpemF4RGoxNMEbnvL5/rYf6IE4fmdtJCU1ltYtcNmatP1sqD N66WDDr5HUrOMNwPZeOn/jjO9wB8BDmBqe0NC2JNnmnw5ZFfQgunM49GTQSTWiDPfyvu VB3+VxlTnzKtjpU2u9A6zq2NT1AO+u2M6T5zo9vwKcLa7scbSuLwxSXXurBo5b7Eb9Qu SmiA0wTp5QGOG3U5qo1KsPJmRW4+NWGXeoxx37okVa5IvZI7VQdcZJANQtrpCMd2NXuw 9Sqmnlh5BXS+jU5SfWSvOsG+P8Z08gFlIzfKJIxxPnHUG9m7QIKQy2uII1hEwHTCNhG8 k7cQ== X-Gm-Message-State: AOAM531CVfHHgnbKhvM8Mj1O0trajAaksrgsnq+jtp/MkuzSdqK7yKZ5 SpSwxyDY+1nTBgtKkRL/d1I= X-Google-Smtp-Source: ABdhPJwuZx115aouP8WME0Yn/0ZEOza+zILNTWAkOVzTZfsswgqG5pfAP3b/tVrWeX6OZsUMGn/q6Q== X-Received: by 2002:adf:f1cf:: with SMTP id z15mr11280927wro.97.1619629554927; Wed, 28 Apr 2021 10:05:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 16/30] target/mips: Move sysemu specific files under sysemu/ subfolder Date: Wed, 28 Apr 2021 19:03:56 +0200 Message-Id: <20210428170410.479308-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/{ =3D> sysemu}/addr.c | 0 target/mips/{ =3D> sysemu}/cp0_timer.c | 0 target/mips/{ =3D> sysemu}/machine.c | 0 MAINTAINERS | 3 ++- target/mips/meson.build | 12 ++++++------ target/mips/sysemu/meson.build | 5 +++++ 6 files changed, 13 insertions(+), 7 deletions(-) rename target/mips/{ =3D> sysemu}/addr.c (100%) rename target/mips/{ =3D> sysemu}/cp0_timer.c (100%) rename target/mips/{ =3D> sysemu}/machine.c (100%) create mode 100644 target/mips/sysemu/meson.build diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c similarity index 100% rename from target/mips/addr.c rename to target/mips/sysemu/addr.c diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c similarity index 100% rename from target/mips/cp0_timer.c rename to target/mips/sysemu/cp0_timer.c diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c similarity index 100% rename from target/mips/machine.c rename to target/mips/sysemu/machine.c diff --git a/MAINTAINERS b/MAINTAINERS index 36055f14c59..0620326544e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,7 +404,8 @@ F: target/arm/kvm.c MIPS KVM CPUs M: Huacai Chen S: Odd Fixes -F: target/mips/kvm.c +F: target/mips/kvm* +F: target/mips/sysemu/ =20 PPC KVM CPUs M: David Gibson diff --git a/target/mips/meson.build b/target/mips/meson.build index ca3cc62cf7a..9a507937ece 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,6 +7,7 @@ ] =20 mips_user_ss =3D ss.source_set() +mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -14,6 +15,11 @@ 'gdbstub.c', 'msa.c', )) + +if have_system + subdir('sysemu') +endif + mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) mips_tcg_ss.add(files( @@ -41,12 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss =3D ss.source_set() -mips_softmmu_ss.add(files( - 'addr.c', - 'cp0_timer.c', - 'machine.c', -)) mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', 'mips-semi.c', diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build new file mode 100644 index 00000000000..f2a1ff46081 --- /dev/null +++ b/target/mips/sysemu/meson.build @@ -0,0 +1,5 @@ +mips_softmmu_ss.add(files( + 'addr.c', + 'cp0_timer.c', + 'machine.c', +)) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629562; cv=none; d=zohomail.com; s=zohoarc; b=FMjGIP2ezBa7HuOXIQb9HK5YZh49cUmDnnBrxcRCISQPKfzo/NOjmYI3twNWUJ8FWH7X1C3dL06K8f3nOkU3Pn9mEz3cwdZs7ao1ksE2Pcs2NzfDPhvFRei8/lJFDFm7sQjmio8U4YpzYqP2SmP+rzyuaC07SIFdWR9uJb7zV1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629562; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=86m1gkF8voOveh0aUUwn9uOk+WCwC8lChneRmIjfEfY=; b=hyZzqZZAVlVMFjaiC8Lw8pbRkn0q7fYZ1Yuh474WK7U1QMNBIPD0d1kh7izzdKaNh1oGA/pvrgNK2ls1HTA31Pjarz2RlAJl+HBEiBcu95Axb4EllhQzV4R5p66Ih4CjU5iWZs5ecijLRqAC5VucNRB6FTuU+TuK9NwdglRWJiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 1619629562119268.1327739726819; Wed, 28 Apr 2021 10:06:02 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id e5so35181652wrg.7 for ; Wed, 28 Apr 2021 10:06:01 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id s83sm318750wms.16.2021.04.28.10.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=86m1gkF8voOveh0aUUwn9uOk+WCwC8lChneRmIjfEfY=; b=c9JZobaxhIPA5jPH3IHlwz2shIF7jUz9oW+uM3pu0rnsDNmnVOoAqFusagFfqqUCzV Hh4csH0oqZnBxPG0CW7zCV01O1yO/XUHL2Da1L+TMsjF2Bdp2fsOBwczYsbo8X9DwdCF QD7wWQkHRFetlxI1FrtAVv1M1h3BNXaeWKDNXLoTtfpwk+ljk43Cf9NO5w+s+GEzFyIU 248Xeq7cPq/WPfb1OxGGB8m64sCm0Uoklj0UZZ4IUutI/dMedb4N4CRsLhfmaRu164Z8 xKq/VF/hgoKcXtNJ2EC/Qeh52YDRJsRq8vuEbCbS/lwS2nt/qGTJvBv6B8sd0dGqgVvG E4Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=86m1gkF8voOveh0aUUwn9uOk+WCwC8lChneRmIjfEfY=; b=O+cbDVaAfpEHaUNUoymzKOFICXEEu0NTWMmyaCBB1zQ1dTqKPnwUkf7gj4F+SrlerS DiwDi6kqklsDPxtaiZZ6jcIt8LEBvGjY7/TzFOu1UGsDO4hHKseRstfV1Roc3wbzED8w QMHRKH8ZFm5DLkPKHxc7RC3sUzcYKHC01AytoArmy+G7Ete90pTaOBze5somA4HLDXA6 2I4wujcgbC5Vcf9diibUf34eQl5SYzgcNHsQlvZVIFCbOHQxMJc2pQXvr3HC6PXdR93K 8ORt8m1XkasRo3Bv44MUZUspk3aE0r7TRmn6KrTKYejMWtO5UGXqS95PJVkvikiDJXT/ IL0g== X-Gm-Message-State: AOAM531NqQgdh58rakjnAfZs4xuPkUW+9MclkMoQZZ5kzzniy4vmBGeD TgONx0qbotvet6Ui3l340N4= X-Google-Smtp-Source: ABdhPJzWyac4yqZMkFUCImGC9teyHbnSPH/9ZD97KZ61oEjCoZ/SSWCQQ8k1T/po62MPbJ0p/WTgOw== X-Received: by 2002:adf:f5c6:: with SMTP id k6mr19464735wrp.338.1619629559686; Wed, 28 Apr 2021 10:05:59 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 17/30] target/mips: Move physical addressing code to sysemu/physaddr.c Date: Wed, 28 Apr 2021 19:03:57 +0200 Message-Id: <20210428170410.479308-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Declare get_physical_address() with local scope and move it along with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 25 +++- target/mips/sysemu/physaddr.c | 257 +++++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 254 -------------------------------- target/mips/sysemu/meson.build | 1 + 4 files changed, 282 insertions(+), 255 deletions(-) create mode 100644 target/mips/sysemu/physaddr.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 3c8ccfbe929..be32102a2ac 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) +#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) +#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) +#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) +#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) + +#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) +#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) + #if !defined(CONFIG_USER_ONLY) =20 +enum { + TLBRET_XI =3D -6, + TLBRET_RI =3D -5, + TLBRET_DIRTY =3D -4, + TLBRET_INVALID =3D -3, + TLBRET_NOMATCH =3D -2, + TLBRET_BADADDR =3D -1, + TLBRET_MATCH =3D 0 +}; + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c new file mode 100644 index 00000000000..1918633aa1c --- /dev/null +++ b/target/mips/sysemu/physaddr.c @@ -0,0 +1,257 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "../internal.h" + +static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) +{ + /* + * Interpret access control mode and mmu_idx. + * AdE? TLB? + * AM K S U E K S U E + * UK 0 0 1 1 0 0 - - 0 + * MK 1 0 1 1 0 1 - - !eu + * MSK 2 0 0 1 0 1 1 - !eu + * MUSK 3 0 0 0 0 1 1 1 !eu + * MUSUK 4 0 0 0 0 0 1 1 0 + * USK 5 0 0 1 0 0 0 - 0 + * - 6 - - - - - - - - + * UUSK 7 0 0 0 0 0 0 0 0 + */ + int32_t adetlb_mask; + + switch (mmu_idx) { + case 3: /* ERL */ + /* If EU is set, always unmapped */ + if (eu) { + return 0; + } + /* fall through */ + case MIPS_HFLAG_KM: + /* Never AdE, TLB mapped if AM=3D{1,2,3} */ + adetlb_mask =3D 0x70000000; + goto check_tlb; + + case MIPS_HFLAG_SM: + /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ + adetlb_mask =3D 0xc0380000; + goto check_ade; + + case MIPS_HFLAG_UM: + /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ + adetlb_mask =3D 0xe4180000; + /* fall through */ + check_ade: + /* does this AM cause AdE in current execution mode */ + if ((adetlb_mask << am) < 0) { + return TLBRET_BADADDR; + } + adetlb_mask <<=3D 8; + /* fall through */ + check_tlb: + /* is this AM mapped in current execution mode */ + return ((adetlb_mask << am) < 0); + default: + assert(0); + return TLBRET_BADADDR; + }; +} + +static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx, + unsigned int am, bool eu, + target_ulong segmask, + hwaddr physical_base) +{ + int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); + + if (mapped < 0) { + /* is_seg_am_mapped can report TLBRET_BADADDR */ + return mapped; + } else if (mapped) { + /* The segment is TLB mapped */ + return env->tlb->map_address(env, physical, prot, real_address, + access_type); + } else { + /* The segment is unmapped */ + *physical =3D physical_base | (real_address & segmask); + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } +} + +static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_addres= s, + MMUAccessType access_type, int mmu_= idx, + uint16_t segctl, target_ulong segma= sk) +{ + unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; + bool eu =3D (segctl >> CP0SC_EU) & 1; + hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; + + return get_seg_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, am, eu, segmask, + pa & ~(hwaddr)segmask); +} + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx) +{ + /* User mode can only access useg/xuseg */ +#if defined(TARGET_MIPS64) + int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; + int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; + int kernel_mode =3D !user_mode && !supervisor_mode; + int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; + int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; + int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; +#endif + int ret =3D TLBRET_MATCH; + /* effective address (modified for KVM T&E kernel segments) */ + target_ulong address =3D real_address; + + if (mips_um_ksegs_enabled()) { + /* KVM T&E adds guest kernel segments in useg */ + if (real_address >=3D KVM_KSEG0_BASE) { + if (real_address < KVM_KSEG2_BASE) { + /* kseg0 */ + address +=3D KSEG0_BASE - KVM_KSEG0_BASE; + } else if (real_address <=3D USEG_LIMIT) { + /* kseg2/3 */ + address +=3D KSEG2_BASE - KVM_KSEG2_BASE; + } + } + } + + if (address <=3D USEG_LIMIT) { + /* useg */ + uint16_t segctl; + + if (address >=3D 0x40000000UL) { + segctl =3D env->CP0_SegCtl2; + } else { + segctl =3D env->CP0_SegCtl2 >> 16; + } + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, segctl, 0x3FFFFFFF); +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { + /* KX/SX/UX bit to check for each xkphys EVA access mode */ + static const uint8_t am_ksux[8] =3D { + [CP0SC_AM_UK] =3D (1u << CP0St_KX), + [CP0SC_AM_MK] =3D (1u << CP0St_KX), + [CP0SC_AM_MSK] =3D (1u << CP0St_SX), + [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), + [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), + [CP0SC_AM_USK] =3D (1u << CP0St_SX), + [6] =3D (1u << CP0St_KX), + [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), + }; + unsigned int am =3D CP0SC_AM_UK; + unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; + + if (xr & (1 << ((address >> 59) & 0x7))) { + am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; + } + /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ + if (env->CP0_Status & am_ksux[am]) { + ret =3D get_seg_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, am, false, env->PA= Mask, + 0); + } else { + ret =3D TLBRET_BADADDR; + } + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } +#endif + } else if (address < KSEG1_BASE) { + /* kseg0 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); + } else if (address < KSEG2_BASE) { + /* kseg1 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1, 0x1FFFFFFF); + } else if (address < KSEG3_BASE) { + /* sseg (kseg2) */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); + } else { + /* + * kseg3 + * XXX: debug segment is not emulated + */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0, 0x1FFFFFFF); + } + return ret; +} + +hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, + cpu_mmu_index(env, false)) !=3D 0) { + return -1; + } + return phys_addr; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index afc019c80dd..bfb08eaf506 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -25,16 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -enum { - TLBRET_XI =3D -6, - TLBRET_RI =3D -5, - TLBRET_DIRTY =3D -4, - TLBRET_INVALID =3D -3, - TLBRET_NOMATCH =3D -2, - TLBRET_BADADDR =3D -1, - TLBRET_MATCH =3D 0 -}; - #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ @@ -166,236 +156,6 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *de= f) } } =20 -static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) -{ - /* - * Interpret access control mode and mmu_idx. - * AdE? TLB? - * AM K S U E K S U E - * UK 0 0 1 1 0 0 - - 0 - * MK 1 0 1 1 0 1 - - !eu - * MSK 2 0 0 1 0 1 1 - !eu - * MUSK 3 0 0 0 0 1 1 1 !eu - * MUSUK 4 0 0 0 0 0 1 1 0 - * USK 5 0 0 1 0 0 0 - 0 - * - 6 - - - - - - - - - * UUSK 7 0 0 0 0 0 0 0 0 - */ - int32_t adetlb_mask; - - switch (mmu_idx) { - case 3: /* ERL */ - /* If EU is set, always unmapped */ - if (eu) { - return 0; - } - /* fall through */ - case MIPS_HFLAG_KM: - /* Never AdE, TLB mapped if AM=3D{1,2,3} */ - adetlb_mask =3D 0x70000000; - goto check_tlb; - - case MIPS_HFLAG_SM: - /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ - adetlb_mask =3D 0xc0380000; - goto check_ade; - - case MIPS_HFLAG_UM: - /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ - adetlb_mask =3D 0xe4180000; - /* fall through */ - check_ade: - /* does this AM cause AdE in current execution mode */ - if ((adetlb_mask << am) < 0) { - return TLBRET_BADADDR; - } - adetlb_mask <<=3D 8; - /* fall through */ - check_tlb: - /* is this AM mapped in current execution mode */ - return ((adetlb_mask << am) < 0); - default: - assert(0); - return TLBRET_BADADDR; - }; -} - -static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx, - unsigned int am, bool eu, - target_ulong segmask, - hwaddr physical_base) -{ - int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); - - if (mapped < 0) { - /* is_seg_am_mapped can report TLBRET_BADADDR */ - return mapped; - } else if (mapped) { - /* The segment is TLB mapped */ - return env->tlb->map_address(env, physical, prot, real_address, - access_type); - } else { - /* The segment is unmapped */ - *physical =3D physical_base | (real_address & segmask); - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; - } -} - -static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_addres= s, - MMUAccessType access_type, int mmu_= idx, - uint16_t segctl, target_ulong segma= sk) -{ - unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; - bool eu =3D (segctl >> CP0SC_EU) & 1; - hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; - - return get_seg_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, am, eu, segmask, - pa & ~(hwaddr)segmask); -} - -static int get_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx) -{ - /* User mode can only access useg/xuseg */ -#if defined(TARGET_MIPS64) - int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; - int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; - int kernel_mode =3D !user_mode && !supervisor_mode; - int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; - int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; - int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; -#endif - int ret =3D TLBRET_MATCH; - /* effective address (modified for KVM T&E kernel segments) */ - target_ulong address =3D real_address; - -#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) -#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) -#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) -#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) -#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) - -#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) -#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) - - if (mips_um_ksegs_enabled()) { - /* KVM T&E adds guest kernel segments in useg */ - if (real_address >=3D KVM_KSEG0_BASE) { - if (real_address < KVM_KSEG2_BASE) { - /* kseg0 */ - address +=3D KSEG0_BASE - KVM_KSEG0_BASE; - } else if (real_address <=3D USEG_LIMIT) { - /* kseg2/3 */ - address +=3D KSEG2_BASE - KVM_KSEG2_BASE; - } - } - } - - if (address <=3D USEG_LIMIT) { - /* useg */ - uint16_t segctl; - - if (address >=3D 0x40000000UL) { - segctl =3D env->CP0_SegCtl2; - } else { - segctl =3D env->CP0_SegCtl2 >> 16; - } - ret =3D get_segctl_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, segctl, 0x3FFFFFFF); -#if defined(TARGET_MIPS64) - } else if (address < 0x4000000000000000ULL) { - /* xuseg */ - if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0x8000000000000000ULL) { - /* xsseg */ - if ((supervisor_mode || kernel_mode) && - SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xC000000000000000ULL) { - /* xkphys */ - if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { - /* KX/SX/UX bit to check for each xkphys EVA access mode */ - static const uint8_t am_ksux[8] =3D { - [CP0SC_AM_UK] =3D (1u << CP0St_KX), - [CP0SC_AM_MK] =3D (1u << CP0St_KX), - [CP0SC_AM_MSK] =3D (1u << CP0St_SX), - [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), - [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), - [CP0SC_AM_USK] =3D (1u << CP0St_SX), - [6] =3D (1u << CP0St_KX), - [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), - }; - unsigned int am =3D CP0SC_AM_UK; - unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; - - if (xr & (1 << ((address >> 59) & 0x7))) { - am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; - } - /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ - if (env->CP0_Status & am_ksux[am]) { - ret =3D get_seg_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, am, false, env->PA= Mask, - 0); - } else { - ret =3D TLBRET_BADADDR; - } - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xFFFFFFFF80000000ULL) { - /* xkseg */ - if (kernel_mode && KX && - address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } -#endif - } else if (address < KSEG1_BASE) { - /* kseg0 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); - } else if (address < KSEG2_BASE) { - /* kseg1 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1, 0x1FFFFFFF); - } else if (address < KSEG3_BASE) { - /* sseg (kseg2) */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); - } else { - /* - * kseg3 - * XXX: debug segment is not emulated - */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0, 0x1FFFFFFF); - } - return ret; -} - void cpu_mips_tlb_flush(CPUMIPSState *env) { /* Flush qemu's TLB and discard all shadowed entries. */ @@ -482,20 +242,6 @@ static void raise_mmu_exception(CPUMIPSState *env, tar= get_ulong address, env->error_code =3D error_code; } =20 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - hwaddr phys_addr; - int prot; - - if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { - return -1; - } - return phys_addr; -} - #if !defined(TARGET_MIPS64) =20 /* diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index f2a1ff46081..925ceeaa449 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -2,4 +2,5 @@ 'addr.c', 'cp0_timer.c', 'machine.c', + 'physaddr.c', )) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629591; cv=none; d=zohomail.com; s=zohoarc; b=QazahPHLp1jb6zRNphIFR54rPOZM7NB2sbU+CHOAq/hxnJm+T/yzX/dr+Q8BAkLYMkfP+sJhcHLXsMtJrNM7VdemZA7R0JhalFGmo4jDWeYMR7nqUdDlAbJyW1wMwNbl3HdATbpx5+ZwtUlWRd42toYyJTeznht7WtL37opkPKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629591; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kmC/c7HfZL6KsbHDqY+pDUb4saJpKTFpx4rhG/OKbHA=; b=RpwNOocEg4RLJQdS9Kx/D63OKSqZ6VZ9MaJfVZ5TxdkMK/p4PuBXuPnP8VZJjVAks2gpxvlnDuhiz4paPwVkqMqS7mkuc14Yd5cp8F5LcxqBeRCzxFzzIyV9TpocWuxMHwWEjJPEwAkC+7XCHi5xdn/vb91v/qathFM1TQ2IHrA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619629591739841.6988266279736; Wed, 28 Apr 2021 10:06:31 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id t18so6250924wry.1 for ; Wed, 28 Apr 2021 10:06:29 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id j13sm409561wrw.93.2021.04.28.10.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kmC/c7HfZL6KsbHDqY+pDUb4saJpKTFpx4rhG/OKbHA=; b=VQL53lUmOnj3UECIR1qJ2QhPFhB0YffT49pk6s8T+dQ4CLZCai1TIqPuurlX4ATaZZ 2BNO+0pOEZdzDEAQzsynYNsnRyHTfip0IhVrJYIGc6OKYKEwD2val8a+dzfc/xslMvqa j6WOrJL10CPciDo8BrksiMflWAbMluFRBQE4lmyxr6P73vzPbeRsn3/LPLkP8T/uCh3D OTyhQwlR9GLhTOQEoUW5tnIEBn8oKvreFp/s0Q2nq1dFJ7YYy4jGZ3KSt8sd/NOTbLYS owNwU7qTCi/yNzwSa6HI21BcEyiIJ6rJuX/BJIWl++BYeZDWW12HLsJnCbCkxZgBzh2+ ikAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kmC/c7HfZL6KsbHDqY+pDUb4saJpKTFpx4rhG/OKbHA=; b=L/dVl81+GcvAaruwAYoEO4iHqWHp667ovzoCHJLeRiPaLbP3mpsrXXnJPzl5MrMWrJ JhDoRATj1TgN2xSnKSCIG/HdDRGW5T/l+ROz4LjOsWv1Skf8TzhwLR8lNkKz3luwLb2Q CI5qaW9DtmR5W7qKHN21JtGm2kJLVpSX6RvwGvzo1d0LzRBPzUWWWRclVJa8PLDwS+0H 5trpbITpBULhkaZwqKWRQjTNx2X6mSb43/bG8ziGS3wdTLWi/0rqlrQgrc8d9xTog32p 64WwZDSnRGwjFCJRIT1ABAR5o9sxhXV5TKgKEhKlr+Qrc5aJTpVq0GUEQhvEafMhYnHV l4og== X-Gm-Message-State: AOAM5339Td3rxUNBFek4q7Hw8vEuVPO96q0VvmSIKYJwE6r87kzVbFS8 FP5wB0iwpUcQfpxigv8PxaM= X-Google-Smtp-Source: ABdhPJyssGiowuYhER2dF5TReqE/kDhFgnZB23s/r4cvAa7IR3fSYXIJyRqaBcjN6gud1TWhM0RH/Q== X-Received: by 2002:adf:e404:: with SMTP id g4mr2298612wrm.240.1619629569374; Wed, 28 Apr 2021 10:06:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 18/30] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG Date: Wed, 28 Apr 2021 19:03:58 +0200 Message-Id: <20210428170410.479308-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 4 ---- target/mips/tcg/tcg-internal.h | 9 +++++++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index be32102a2ac..6bac8ef704a 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, @@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 -/* op_helper.c */ -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); - static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) { env->active_tc.PC =3D value & ~(target_ulong)1; diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 24438667f47..b65580af211 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,10 +11,19 @@ #define MIPS_TCG_INTERNAL_H =20 #include "hw/core/cpu.h" +#include "cpu.h" =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +#if !defined(CONFIG_USER_ONLY) + +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); + +uint32_t cpu_mips_get_random(CPUMIPSState *env); + +#endif /* !CONFIG_USER_ONLY */ + #endif --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629576; cv=none; d=zohomail.com; s=zohoarc; b=U6FUyZ9UkikiqbLMXD4dwkuCXdAdz/xFWRksJvX4zNIfJbwNMApByYDcCyCiyo2FL3euJ5epvESNEwySiQhmwC9WsaFXgiTEbKskY7EpwYnoAXVPw40ny7qwzuptPBSgZlmsvDvQ94cKU1QH1sAuxcVwwGLnlxNbh7I+ZLG4UrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629576; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tn2MzTrz7xwfpKYZAt9e7EHE2771er0S6seDM+df6hc=; b=NUiG7t8FMMY0dmMKBCeHfDQ3RKbSFO7PlnAQBvrQSuCg02kVF8OauK8eLzymcUc8VahgTMjThooGj4JIRe489YPZt0lpXLUzvoE8K8QZw51oa5LZV/8q23s2z9yLnRdB6cTcXGC8Z8Xbf5mpH+ga3qjqOb5bnduQuevNe45ficE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1619629576855600.230645879454; Wed, 28 Apr 2021 10:06:16 -0700 (PDT) Received: by mail-wr1-f54.google.com with SMTP id l2so11515662wrm.9 for ; Wed, 28 Apr 2021 10:06:15 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l14sm346220wmq.4.2021.04.28.10.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tn2MzTrz7xwfpKYZAt9e7EHE2771er0S6seDM+df6hc=; b=chMIc7ugskdXUfGWNYfEr9IL9quipWYmFjLPuF34VY5iwOtD32XPM61PQLx1xFy/e+ 4KVnsbih9+twOgc93LtV7nri41JrBejiKzUyHqBkbaN1MYUPqMiGmikorag4HK06MXsN fR3l/HgRbCWnOgLu40oKEsgDOzrBgyJcP+3qS9v/Ps7W5MWKvB+C6Er6o4yTI6gm1XOp yi+eByEevGjyVM4hEvIrFaT8Dnj4+uxybgmHCdTcS/4dsbOxwaW6wIsMySbDJFmA9mmv I8N7Hd/HfN7Rzp5fzBqE0B92LBEOpjyrMBFf6UlEvYFykCAqyNMevblD5ho0XITghIds wzPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tn2MzTrz7xwfpKYZAt9e7EHE2771er0S6seDM+df6hc=; b=PWLvZ+CQdhWfDhMksiY/2SjS5q3SZglNK1MR1fss1ajCLPjEN3p9CbNShC0M/fsaVh EsF0tdVh0fgxUZuVwh0PTDBS5ELFa09MieHSjugsIInDRagPuCFO55B+dGT+Bjkgg3pJ GrV1XP5v0/vD050YOzSH/TcwnOOAD8WhXTRzBDrqlfAxnW2Rt+HwdAKgtO4EMxoBdcOL aMWPfCI7hA5xO9cIm0jpC5InwJwOSrE0FVicIcPjryJfpa4SSe4eW2GrLRNfUTPrJf7l FDGcQcEwV6U+THSXD/uvbRLQYpgvTB5TGR+xWuo+uqIvL57HvzL5IlU8J5DcTILywr3P y0xQ== X-Gm-Message-State: AOAM531Jp8Tvot2vyEbqzVvgvxgFkszJ/s6QJdqxk4zu5PlVsBBquhpG 3RmVwmbRnGH1Q2t+MY4hxKs= X-Google-Smtp-Source: ABdhPJxi2jhAvNCHXwv7A8TYsMQZTiMpj93nmCJBiYwgF5NvxVQIkRzyRntEZiI8kO/Y7kR5gI4Agw== X-Received: by 2002:adf:f80f:: with SMTP id s15mr3953974wrp.341.1619629574227; Wed, 28 Apr 2021 10:06:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 19/30] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Date: Wed, 28 Apr 2021 19:03:59 +0200 Message-Id: <20210428170410.479308-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 166 +-------------------- target/mips/tcg/sysemu_helper.h.inc | 168 ++++++++++++++++++++++ target/mips/{ =3D> tcg/sysemu}/cp0_helper.c | 0 target/mips/{ =3D> tcg/sysemu}/mips-semi.c | 0 target/mips/meson.build | 5 - target/mips/tcg/meson.build | 3 + target/mips/tcg/sysemu/meson.build | 4 + 7 files changed, 179 insertions(+), 167 deletions(-) create mode 100644 target/mips/tcg/sysemu_helper.h.inc rename target/mips/{ =3D> tcg/sysemu}/cp0_helper.c (100%) rename target/mips/{ =3D> tcg/sysemu}/mips-semi.c (100%) create mode 100644 target/mips/tcg/sysemu/meson.build diff --git a/target/mips/helper.h b/target/mips/helper.h index 709494445dd..bc308e5db13 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_1(raise_exception_debug, noreturn, env) =20 -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(do_semihosting, void, env) -#endif - #ifdef TARGET_MIPS64 DEF_HELPER_4(sdl, void, env, tl, tl, int) DEF_HELPER_4(sdr, void, env, tl, tl, int) @@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) =20 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 -#ifndef CONFIG_USER_ONLY -/* CP0 helpers */ -DEF_HELPER_1(mfc0_mvpcontrol, tl, env) -DEF_HELPER_1(mfc0_mvpconf0, tl, env) -DEF_HELPER_1(mfc0_mvpconf1, tl, env) -DEF_HELPER_1(mftc0_vpecontrol, tl, env) -DEF_HELPER_1(mftc0_vpeconf0, tl, env) -DEF_HELPER_1(mfc0_random, tl, env) -DEF_HELPER_1(mfc0_tcstatus, tl, env) -DEF_HELPER_1(mftc0_tcstatus, tl, env) -DEF_HELPER_1(mfc0_tcbind, tl, env) -DEF_HELPER_1(mftc0_tcbind, tl, env) -DEF_HELPER_1(mfc0_tcrestart, tl, env) -DEF_HELPER_1(mftc0_tcrestart, tl, env) -DEF_HELPER_1(mfc0_tchalt, tl, env) -DEF_HELPER_1(mftc0_tchalt, tl, env) -DEF_HELPER_1(mfc0_tccontext, tl, env) -DEF_HELPER_1(mftc0_tccontext, tl, env) -DEF_HELPER_1(mfc0_tcschedule, tl, env) -DEF_HELPER_1(mftc0_tcschedule, tl, env) -DEF_HELPER_1(mfc0_tcschefback, tl, env) -DEF_HELPER_1(mftc0_tcschefback, tl, env) -DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) -DEF_HELPER_1(mftc0_entryhi, tl, env) -DEF_HELPER_1(mftc0_status, tl, env) -DEF_HELPER_1(mftc0_cause, tl, env) -DEF_HELPER_1(mftc0_epc, tl, env) -DEF_HELPER_1(mftc0_ebase, tl, env) -DEF_HELPER_2(mftc0_configx, tl, env, tl) -DEF_HELPER_1(mfc0_lladdr, tl, env) -DEF_HELPER_1(mfc0_maar, tl, env) -DEF_HELPER_1(mfhc0_maar, tl, env) -DEF_HELPER_2(mfc0_watchlo, tl, env, i32) -DEF_HELPER_2(mfc0_watchhi, tl, env, i32) -DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) -DEF_HELPER_1(mfc0_debug, tl, env) -DEF_HELPER_1(mftc0_debug, tl, env) -#ifdef TARGET_MIPS64 -DEF_HELPER_1(dmfc0_tcrestart, tl, env) -DEF_HELPER_1(dmfc0_tchalt, tl, env) -DEF_HELPER_1(dmfc0_tccontext, tl, env) -DEF_HELPER_1(dmfc0_tcschedule, tl, env) -DEF_HELPER_1(dmfc0_tcschefback, tl, env) -DEF_HELPER_1(dmfc0_lladdr, tl, env) -DEF_HELPER_1(dmfc0_maar, tl, env) -DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) -DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) -#endif /* TARGET_MIPS64 */ - -DEF_HELPER_2(mtc0_index, void, env, tl) -DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) -DEF_HELPER_2(mtc0_yqmask, void, env, tl) -DEF_HELPER_2(mtc0_vpeopt, void, env, tl) -DEF_HELPER_2(mtc0_entrylo0, void, env, tl) -DEF_HELPER_2(mtc0_tcstatus, void, env, tl) -DEF_HELPER_2(mttc0_tcstatus, void, env, tl) -DEF_HELPER_2(mtc0_tcbind, void, env, tl) -DEF_HELPER_2(mttc0_tcbind, void, env, tl) -DEF_HELPER_2(mtc0_tcrestart, void, env, tl) -DEF_HELPER_2(mttc0_tcrestart, void, env, tl) -DEF_HELPER_2(mtc0_tchalt, void, env, tl) -DEF_HELPER_2(mttc0_tchalt, void, env, tl) -DEF_HELPER_2(mtc0_tccontext, void, env, tl) -DEF_HELPER_2(mttc0_tccontext, void, env, tl) -DEF_HELPER_2(mtc0_tcschedule, void, env, tl) -DEF_HELPER_2(mttc0_tcschedule, void, env, tl) -DEF_HELPER_2(mtc0_tcschefback, void, env, tl) -DEF_HELPER_2(mttc0_tcschefback, void, env, tl) -DEF_HELPER_2(mtc0_entrylo1, void, env, tl) -DEF_HELPER_2(mtc0_context, void, env, tl) -DEF_HELPER_2(mtc0_memorymapid, void, env, tl) -DEF_HELPER_2(mtc0_pagemask, void, env, tl) -DEF_HELPER_2(mtc0_pagegrain, void, env, tl) -DEF_HELPER_2(mtc0_segctl0, void, env, tl) -DEF_HELPER_2(mtc0_segctl1, void, env, tl) -DEF_HELPER_2(mtc0_segctl2, void, env, tl) -DEF_HELPER_2(mtc0_pwfield, void, env, tl) -DEF_HELPER_2(mtc0_pwsize, void, env, tl) -DEF_HELPER_2(mtc0_wired, void, env, tl) -DEF_HELPER_2(mtc0_srsconf0, void, env, tl) -DEF_HELPER_2(mtc0_srsconf1, void, env, tl) -DEF_HELPER_2(mtc0_srsconf2, void, env, tl) -DEF_HELPER_2(mtc0_srsconf3, void, env, tl) -DEF_HELPER_2(mtc0_srsconf4, void, env, tl) -DEF_HELPER_2(mtc0_hwrena, void, env, tl) -DEF_HELPER_2(mtc0_pwctl, void, env, tl) -DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) -DEF_HELPER_2(mtc0_entryhi, void, env, tl) -DEF_HELPER_2(mttc0_entryhi, void, env, tl) -DEF_HELPER_2(mtc0_compare, void, env, tl) -DEF_HELPER_2(mtc0_status, void, env, tl) -DEF_HELPER_2(mttc0_status, void, env, tl) -DEF_HELPER_2(mtc0_intctl, void, env, tl) -DEF_HELPER_2(mtc0_srsctl, void, env, tl) -DEF_HELPER_2(mtc0_cause, void, env, tl) -DEF_HELPER_2(mttc0_cause, void, env, tl) -DEF_HELPER_2(mtc0_ebase, void, env, tl) -DEF_HELPER_2(mttc0_ebase, void, env, tl) -DEF_HELPER_2(mtc0_config0, void, env, tl) -DEF_HELPER_2(mtc0_config2, void, env, tl) -DEF_HELPER_2(mtc0_config3, void, env, tl) -DEF_HELPER_2(mtc0_config4, void, env, tl) -DEF_HELPER_2(mtc0_config5, void, env, tl) -DEF_HELPER_2(mtc0_lladdr, void, env, tl) -DEF_HELPER_2(mtc0_maar, void, env, tl) -DEF_HELPER_2(mthc0_maar, void, env, tl) -DEF_HELPER_2(mtc0_maari, void, env, tl) -DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) -DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) -DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) -DEF_HELPER_2(mtc0_xcontext, void, env, tl) -DEF_HELPER_2(mtc0_framemask, void, env, tl) -DEF_HELPER_2(mtc0_debug, void, env, tl) -DEF_HELPER_2(mttc0_debug, void, env, tl) -DEF_HELPER_2(mtc0_performance0, void, env, tl) -DEF_HELPER_2(mtc0_errctl, void, env, tl) -DEF_HELPER_2(mtc0_taglo, void, env, tl) -DEF_HELPER_2(mtc0_datalo, void, env, tl) -DEF_HELPER_2(mtc0_taghi, void, env, tl) -DEF_HELPER_2(mtc0_datahi, void, env, tl) - -#if defined(TARGET_MIPS64) -DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) -DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) -#endif - -/* MIPS MT functions */ -DEF_HELPER_2(mftgpr, tl, env, i32) -DEF_HELPER_2(mftlo, tl, env, i32) -DEF_HELPER_2(mfthi, tl, env, i32) -DEF_HELPER_2(mftacx, tl, env, i32) -DEF_HELPER_1(mftdsp, tl, env) -DEF_HELPER_3(mttgpr, void, env, tl, i32) -DEF_HELPER_3(mttlo, void, env, tl, i32) -DEF_HELPER_3(mtthi, void, env, tl, i32) -DEF_HELPER_3(mttacx, void, env, tl, i32) -DEF_HELPER_2(mttdsp, void, env, tl) -DEF_HELPER_0(dmt, tl) -DEF_HELPER_0(emt, tl) -DEF_HELPER_1(dvpe, tl, env) -DEF_HELPER_1(evpe, tl, env) - -/* R6 Multi-threading */ -DEF_HELPER_1(dvp, tl, env) -DEF_HELPER_1(evp, tl, env) -#endif /* !CONFIG_USER_ONLY */ - /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) @@ -783,4 +621,8 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 DEF_HELPER_3(cache, void, env, tl, i32) =20 +#ifndef CONFIG_USER_ONLY +#include "tcg/sysemu_helper.h.inc" +#endif /* !CONFIG_USER_ONLY */ + #include "msa_helper.h.inc" diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc new file mode 100644 index 00000000000..d136c4160a7 --- /dev/null +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -0,0 +1,168 @@ +/* + * QEMU MIPS sysemu helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_1(do_semihosting, void, env) + +/* CP0 helpers */ +DEF_HELPER_1(mfc0_mvpcontrol, tl, env) +DEF_HELPER_1(mfc0_mvpconf0, tl, env) +DEF_HELPER_1(mfc0_mvpconf1, tl, env) +DEF_HELPER_1(mftc0_vpecontrol, tl, env) +DEF_HELPER_1(mftc0_vpeconf0, tl, env) +DEF_HELPER_1(mfc0_random, tl, env) +DEF_HELPER_1(mfc0_tcstatus, tl, env) +DEF_HELPER_1(mftc0_tcstatus, tl, env) +DEF_HELPER_1(mfc0_tcbind, tl, env) +DEF_HELPER_1(mftc0_tcbind, tl, env) +DEF_HELPER_1(mfc0_tcrestart, tl, env) +DEF_HELPER_1(mftc0_tcrestart, tl, env) +DEF_HELPER_1(mfc0_tchalt, tl, env) +DEF_HELPER_1(mftc0_tchalt, tl, env) +DEF_HELPER_1(mfc0_tccontext, tl, env) +DEF_HELPER_1(mftc0_tccontext, tl, env) +DEF_HELPER_1(mfc0_tcschedule, tl, env) +DEF_HELPER_1(mftc0_tcschedule, tl, env) +DEF_HELPER_1(mfc0_tcschefback, tl, env) +DEF_HELPER_1(mftc0_tcschefback, tl, env) +DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) +DEF_HELPER_1(mftc0_entryhi, tl, env) +DEF_HELPER_1(mftc0_status, tl, env) +DEF_HELPER_1(mftc0_cause, tl, env) +DEF_HELPER_1(mftc0_epc, tl, env) +DEF_HELPER_1(mftc0_ebase, tl, env) +DEF_HELPER_2(mftc0_configx, tl, env, tl) +DEF_HELPER_1(mfc0_lladdr, tl, env) +DEF_HELPER_1(mfc0_maar, tl, env) +DEF_HELPER_1(mfhc0_maar, tl, env) +DEF_HELPER_2(mfc0_watchlo, tl, env, i32) +DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) +DEF_HELPER_1(mfc0_debug, tl, env) +DEF_HELPER_1(mftc0_debug, tl, env) +#ifdef TARGET_MIPS64 +DEF_HELPER_1(dmfc0_tcrestart, tl, env) +DEF_HELPER_1(dmfc0_tchalt, tl, env) +DEF_HELPER_1(dmfc0_tccontext, tl, env) +DEF_HELPER_1(dmfc0_tcschedule, tl, env) +DEF_HELPER_1(dmfc0_tcschefback, tl, env) +DEF_HELPER_1(dmfc0_lladdr, tl, env) +DEF_HELPER_1(dmfc0_maar, tl, env) +DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_2(mtc0_index, void, env, tl) +DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) +DEF_HELPER_2(mtc0_yqmask, void, env, tl) +DEF_HELPER_2(mtc0_vpeopt, void, env, tl) +DEF_HELPER_2(mtc0_entrylo0, void, env, tl) +DEF_HELPER_2(mtc0_tcstatus, void, env, tl) +DEF_HELPER_2(mttc0_tcstatus, void, env, tl) +DEF_HELPER_2(mtc0_tcbind, void, env, tl) +DEF_HELPER_2(mttc0_tcbind, void, env, tl) +DEF_HELPER_2(mtc0_tcrestart, void, env, tl) +DEF_HELPER_2(mttc0_tcrestart, void, env, tl) +DEF_HELPER_2(mtc0_tchalt, void, env, tl) +DEF_HELPER_2(mttc0_tchalt, void, env, tl) +DEF_HELPER_2(mtc0_tccontext, void, env, tl) +DEF_HELPER_2(mttc0_tccontext, void, env, tl) +DEF_HELPER_2(mtc0_tcschedule, void, env, tl) +DEF_HELPER_2(mttc0_tcschedule, void, env, tl) +DEF_HELPER_2(mtc0_tcschefback, void, env, tl) +DEF_HELPER_2(mttc0_tcschefback, void, env, tl) +DEF_HELPER_2(mtc0_entrylo1, void, env, tl) +DEF_HELPER_2(mtc0_context, void, env, tl) +DEF_HELPER_2(mtc0_memorymapid, void, env, tl) +DEF_HELPER_2(mtc0_pagemask, void, env, tl) +DEF_HELPER_2(mtc0_pagegrain, void, env, tl) +DEF_HELPER_2(mtc0_segctl0, void, env, tl) +DEF_HELPER_2(mtc0_segctl1, void, env, tl) +DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) +DEF_HELPER_2(mtc0_wired, void, env, tl) +DEF_HELPER_2(mtc0_srsconf0, void, env, tl) +DEF_HELPER_2(mtc0_srsconf1, void, env, tl) +DEF_HELPER_2(mtc0_srsconf2, void, env, tl) +DEF_HELPER_2(mtc0_srsconf3, void, env, tl) +DEF_HELPER_2(mtc0_srsconf4, void, env, tl) +DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_pwctl, void, env, tl) +DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) +DEF_HELPER_2(mtc0_entryhi, void, env, tl) +DEF_HELPER_2(mttc0_entryhi, void, env, tl) +DEF_HELPER_2(mtc0_compare, void, env, tl) +DEF_HELPER_2(mtc0_status, void, env, tl) +DEF_HELPER_2(mttc0_status, void, env, tl) +DEF_HELPER_2(mtc0_intctl, void, env, tl) +DEF_HELPER_2(mtc0_srsctl, void, env, tl) +DEF_HELPER_2(mtc0_cause, void, env, tl) +DEF_HELPER_2(mttc0_cause, void, env, tl) +DEF_HELPER_2(mtc0_ebase, void, env, tl) +DEF_HELPER_2(mttc0_ebase, void, env, tl) +DEF_HELPER_2(mtc0_config0, void, env, tl) +DEF_HELPER_2(mtc0_config2, void, env, tl) +DEF_HELPER_2(mtc0_config3, void, env, tl) +DEF_HELPER_2(mtc0_config4, void, env, tl) +DEF_HELPER_2(mtc0_config5, void, env, tl) +DEF_HELPER_2(mtc0_lladdr, void, env, tl) +DEF_HELPER_2(mtc0_maar, void, env, tl) +DEF_HELPER_2(mthc0_maar, void, env, tl) +DEF_HELPER_2(mtc0_maari, void, env, tl) +DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) +DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) +DEF_HELPER_2(mtc0_xcontext, void, env, tl) +DEF_HELPER_2(mtc0_framemask, void, env, tl) +DEF_HELPER_2(mtc0_debug, void, env, tl) +DEF_HELPER_2(mttc0_debug, void, env, tl) +DEF_HELPER_2(mtc0_performance0, void, env, tl) +DEF_HELPER_2(mtc0_errctl, void, env, tl) +DEF_HELPER_2(mtc0_taglo, void, env, tl) +DEF_HELPER_2(mtc0_datalo, void, env, tl) +DEF_HELPER_2(mtc0_taghi, void, env, tl) +DEF_HELPER_2(mtc0_datahi, void, env, tl) + +#if defined(TARGET_MIPS64) +DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) +DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) +#endif + +/* MIPS MT functions */ +DEF_HELPER_2(mftgpr, tl, env, i32) +DEF_HELPER_2(mftlo, tl, env, i32) +DEF_HELPER_2(mfthi, tl, env, i32) +DEF_HELPER_2(mftacx, tl, env, i32) +DEF_HELPER_1(mftdsp, tl, env) +DEF_HELPER_3(mttgpr, void, env, tl, i32) +DEF_HELPER_3(mttlo, void, env, tl, i32) +DEF_HELPER_3(mtthi, void, env, tl, i32) +DEF_HELPER_3(mttacx, void, env, tl, i32) +DEF_HELPER_2(mttdsp, void, env, tl) +DEF_HELPER_0(dmt, tl) +DEF_HELPER_0(emt, tl) +DEF_HELPER_1(dvpe, tl, env) +DEF_HELPER_1(evpe, tl, env) + +/* R6 Multi-threading */ +DEF_HELPER_1(dvp, tl, env) +DEF_HELPER_1(evp, tl, env) diff --git a/target/mips/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c similarity index 100% rename from target/mips/cp0_helper.c rename to target/mips/tcg/sysemu/cp0_helper.c diff --git a/target/mips/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c similarity index 100% rename from target/mips/mips-semi.c rename to target/mips/tcg/sysemu/mips-semi.c diff --git a/target/mips/meson.build b/target/mips/meson.build index 9a507937ece..a55af1cd6cf 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -47,11 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cp0_helper.c', - 'mips-semi.c', -)) - mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) =20 target_arch +=3D {'mips': mips_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index b74fa04303e..2cffc5a5ac6 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,6 @@ if have_user subdir('user') endif +if have_system + subdir('sysemu') +endif diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build new file mode 100644 index 00000000000..5c3024e7760 --- /dev/null +++ b/target/mips/tcg/sysemu/meson.build @@ -0,0 +1,4 @@ +mips_softmmu_ss.add(files( + 'cp0_helper.c', + 'mips-semi.c', +)) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629586; cv=none; d=zohomail.com; s=zohoarc; b=Z4GhdQZ9LRSW/dgtu72+Ovd8rYOcb5YnCqOGhjVLCRYqpJnBCRue+tmkCoYVA0MbGbC0tZuKsh/rV0sxWvS6VEEiYaeMyHdZlQQKHqQfax508m393Z/6Sc5J4vcVckF5wmKmwdkzl0WJm33C5xuwPX3QKhzjskOTvcvQusVtaF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629586; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2lgWpDVtHLK5W5X4ptXi3w0BPexnbmIruOxVJ55tAs4=; b=VFYuyq3+gVuq4fFlFmgYkBGHNujTT4Eci26+vVjusawR3l0Ysp0KwKcZh7SeP/plrltaoyMD0YKwaJPfDB8C4dZhwJRD5bEaU1Fz5SyX1u3UOylJbHiQImEl0ab7+aXEdnHMGX6ALao5vD0E69Jf9g/uY1x+ovwf+GwJILhQ6Co= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 1619629586801447.51082905831254; Wed, 28 Apr 2021 10:06:26 -0700 (PDT) Received: by mail-wm1-f46.google.com with SMTP id b19-20020a05600c06d3b029014258a636e8so5076697wmn.2 for ; Wed, 28 Apr 2021 10:06:25 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id o10sm439289wrx.35.2021.04.28.10.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2lgWpDVtHLK5W5X4ptXi3w0BPexnbmIruOxVJ55tAs4=; b=KEUMGpNLOWKZsMwBZLtNU9zxJuYgxNH7+2pJ28GqEQ87zZxBDdQDiCBM42miyaBhw0 EHLuiiP7NRAvp6hVA+cU9+9gSjCvlS8KXHe5uBvSxvZp7WSWwAusWvJweXAJrHyR4PX8 5C9+0jHBeFM5ImDmkLO65qYEULQOFe/OwMKQD/NyrtyCv1nt7ukSPHJiS90KIhP7b2Ir EUyMHTmgIg8G33JY5gbxsaggZFYhTMD0Dz4k48EAreEiZiMhEKXvOAFHLo+UbC1bgZV/ H+IPqLEZ/4Hoege6f7uewJLr1nbBHJ/lQIsyXnEXDy4Hx2tmvepepywE2ICtgWnaAT11 qmbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2lgWpDVtHLK5W5X4ptXi3w0BPexnbmIruOxVJ55tAs4=; b=JcjIs5A6J3p/vxLk2WJalVxGU+m2tePKywRqGSSWzPT4fXNm/eQO18NgMfx2+faq0z zgvy1OfFWpwc6ew4zXDu+9q5OVgjApvatgoh4N/nEs4YH53QxIkmeycLNcNqNGnqnvl+ LO/V36Tu2sG06sXKst6JSZxAn8JMAuXEiJ0Y6dvq1hrAwFvrWkJZee3Rxt9KjiAYdR5H RljWLObFgZJqrXDWTO9ciDf6muYp3Ku2ASYFce2wQgJkFj/5FrP2C1dWkGhFGSFX5RCs gd6X0B6uNk6b50X2U2GjFzIwvOHUnrQY3f/sWl9bCOVv93CJHvfVDsP7fOc2l/iB6LF9 TW6Q== X-Gm-Message-State: AOAM530khxHGNRJ1Efq/d2ZrpN2sRfOvJrAfgAtLQkdKvuF37PY3wKDv BM8kcsGRP2O8F0g5F4IpIno= X-Google-Smtp-Source: ABdhPJwFPhWRY5eVEjoeQzHnn9Dr0Thm6wpoTeqHcwUfKYFQfxpDMpdWhOD+auf/j/Ae/aytDuvT4w== X-Received: by 2002:a1c:7711:: with SMTP id t17mr9935056wmi.6.1619629579141; Wed, 28 Apr 2021 10:06:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 20/30] target/mips: Restrict mmu_init() to TCG Date: Wed, 28 Apr 2021 19:04:00 +0200 Message-Id: <20210428170410.479308-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 3 --- target/mips/tcg/tcg-internal.h | 2 ++ target/mips/cpu.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 6bac8ef704a..2c9666905df 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t= value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 -/* helper.c */ -void mmu_init(CPUMIPSState *env, const mips_def_t *def); - static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) { env->active_tc.PC =3D value & ~(target_ulong)1; diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index b65580af211..70655bab45c 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 #if !defined(CONFIG_USER_ONLY) =20 +void mmu_init(CPUMIPSState *env, const mips_def_t *def); + void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a751c958329..c3159e3d7f3 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) =20 env->exception_base =3D (int32_t)0xBFC00000; =20 -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629586; cv=none; d=zohomail.com; s=zohoarc; b=kiNtb5gH2DU/PkIzZ5gKJreYI0UzmsMgKjyWfDTFpDFxtNMtHTMlaYnWQHADcNuPQaMbCWjcSt6rsuzX0agzkLiH+VcWhJiUT+5u6f0OhirPZZUbmhM4mbklgiBBhYiCJmjxfctQzbM0ccc2/HkCDGQp+VHCeh889fV3EEcD0TI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629586; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2C0UvV4ix/FbrE14gWIC5d1EOb1/N6nvJDFEzIzr/78=; b=AnLsHxNx40EfsSosPraI4ryqG93rOGNaqk1QuVtfCU1AbH6Bm/Z5gARNnAfzScacrv3TCnsf/hB+qQ6ds7PMEqmotNsx7hzq/2H/GUrRgFSnWeQHZWtO/6NuoYx1ARqKMpFb8H69MSm5k595oqq3IOauLx9rRxzF1xafoBL6KvA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 161962958608581.98718082085009; Wed, 28 Apr 2021 10:06:26 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id h4so54795092wrt.12 for ; Wed, 28 Apr 2021 10:06:24 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id n5sm418211wrx.92.2021.04.28.10.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2C0UvV4ix/FbrE14gWIC5d1EOb1/N6nvJDFEzIzr/78=; b=mhcTK4J/KHU5AOUl3MxxXLogc3TAvE2WynrzSxHsjCS11u4Hiq1Q/pcWNlKEYnyD5D 8lEaV+y5ycb9collq5xPThOktkTaXhXRXJr2rT7gLOa4EXw7HOQ3vbZUzuieF95ikKd1 HShGRdiJQAi+jdl+p2Gp3uYt/szXF4SyrKHDjd+VdVyd7jaSykvrimEcPkBDQRVd/v5N MmXDOY9aPxqc+owTOhe8iHIF0exqzRAhpk3TzpBSrDgiaMbDvWwNhv6avdbxKS1tqSiS EDwIkjZKDIBeWQP56QHrEpYDYujvCGknOzl771JWE354UIscWLoIZF2jh6N7WqAXjus3 +SCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2C0UvV4ix/FbrE14gWIC5d1EOb1/N6nvJDFEzIzr/78=; b=MqABr3Np0KkguWjO6LTXDyA6jVfZ9LKW6arTeEGVbjiM7FDP3HXG7mQbJilE/5mJiq ZzPsQTxHD6hfcZ6FXGgfLsoo4Dr/LR7dJVFBs4q0QjMHgC9io2qmOxCHTHA5YpvjTixd Z+f+bPpBPYvG2zBj5ztogDCHOJvBtdvnxSpNI6r+KL3saNbrSbXm5jeYAsjxtkmNLqd0 fAaLmTWSytguLekdJoZ7G86fw9+LN2BPvJVAqIzJCODAYalVxs2f6LLqWnUoF89F4vIl 1HV5Uo5+dJD+c6kjnUBGSw2Sfn9Gh2cSVF6RLsfcJhi7tpel4VdKj2lCkUOr4naSsjm+ Bhrg== X-Gm-Message-State: AOAM532SqKYwQKfOlbjGStVBa1Ye7GqRAY9BfVmwCUC+YDbzKKzUUfsA Asr1XrIJUKI8WY1yBh4CxME= X-Google-Smtp-Source: ABdhPJy0OMhAQinlO0AipKVD2kpFapq1pDs/xrft7CLG4ybMLIyIINWK5H9SwESDqE+VtB3wqzrLFw== X-Received: by 2002:a5d:4412:: with SMTP id z18mr23143711wrq.103.1619629583814; Wed, 28 Apr 2021 10:06:23 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 21/30] target/mips: Move tlb_helper.c to tcg/sysemu/ Date: Wed, 28 Apr 2021 19:04:01 +0200 Message-Id: <20210428170410.479308-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 5 ----- target/mips/tcg/tcg-internal.h | 5 +++++ target/mips/{ =3D> tcg/sysemu}/tlb_helper.c | 3 --- target/mips/meson.build | 1 - target/mips/tcg/sysemu/meson.build | 1 + 5 files changed, 6 insertions(+), 9 deletions(-) rename target/mips/{ =3D> tcg/sysemu}/tlb_helper.c (99%) diff --git a/target/mips/internal.h b/target/mips/internal.h index 2c9666905df..558cdca4e84 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -164,16 +164,12 @@ void r4k_helper_tlbp(CPUMIPSState *env); void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); -void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type, uintptr_t ret= addr); - extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -423,7 +419,6 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void cpu_mips_tlb_flush(CPUMIPSState *env); void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 70655bab45c..a39ff45d58f 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -24,8 +24,13 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type, uintptr_t ret= addr); +void cpu_mips_tlb_flush(CPUMIPSState *env); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c similarity index 99% rename from target/mips/tlb_helper.c rename to target/mips/tcg/sysemu/tlb_helper.c index bfb08eaf506..bf242f5e65a 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -25,8 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -#if !defined(CONFIG_USER_ONLY) - /* no MMU emulation */ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type) @@ -1072,4 +1070,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, i= nt use_extra) } } } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/meson.build b/target/mips/meson.build index a55af1cd6cf..ff5eb210dfd 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -31,7 +31,6 @@ 'msa_translate.c', 'op_helper.c', 'rel6_translate.c', - 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 5c3024e7760..73ab9571ba6 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,4 +1,5 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'tlb_helper.c', )) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629591; cv=none; d=zohomail.com; s=zohoarc; b=aJSG8rJb5cdhwQ9l7U1jANf3/UNJnTBN5soRPLoIqjGnS7ObnAqG/8FgKGUVo/2ATwFkqUda0ywFtD2iOEOKLVvMj8VIiUnCfL7sGa5rmhwwH7LxJvWw3S0uZv8EZvU1YN3uKG4/JQ3+bSGphptYrT2n61at46HzvjrffmX2PWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629591; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yrsw7IxXDyNNt3tdDpsGCTMjH/SzXB09St0lk0R+vuk=; b=U8bRX9fmcTFdWTPsCjcEUD12rPpd+NWeb1qJ7VWFvtpOF41THn9PA5ZuO6aTiW2tSLRfMJ+K9UHKPAV1Nnyil2wybIFOau8uQkeElP++Yd/8b71W50KvULT/Ra7pkcr2QFzxEsbqjpgrhlZP59QPOPVn2vZWHHwlGw5GENqPjx4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 161962959104920.491973369499306; Wed, 28 Apr 2021 10:06:31 -0700 (PDT) Received: by mail-wr1-f54.google.com with SMTP id n2so10671407wrm.0 for ; Wed, 28 Apr 2021 10:06:29 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id i14sm7040279wmq.1.2021.04.28.10.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yrsw7IxXDyNNt3tdDpsGCTMjH/SzXB09St0lk0R+vuk=; b=kU00Mh5mdjuUJuLn0yWw+0s1saUgIkmsx1dm1V7eVTJ0s576P+BsvLrR6W7BINhzfx 1NivSpXtl2V6OzBLRzITm8e8V1M0Junwkw3sRcZQ7cLzCh9mFu4WubWx3QAt383z1H5i FKgjSjGk9Scm/d4pQmxFwiBEXR4S2vfYiXhmZDNOjJrT9LzjwcCDVx1va/K6lpZPY0Ll FSjiQv7Hh+D5uZcCJpSicMIp3bkk4Z+6k6jOMbSWpUptaGO/ZEsQataKF0kUJQbfAp5Z xdN6eN24ZxbKGMhrr9C4N7hcSttYHwYbjkedqVFN+Dtsio2vXXV9BC0UwoG5HG0GV9+n Opkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Yrsw7IxXDyNNt3tdDpsGCTMjH/SzXB09St0lk0R+vuk=; b=nGAFdqSyuY88RQXW6sG66V2nWHbojJsIRbYHNPZ6mvOOBzt9geeuDKcu30Sfkyjzp0 NwcHpF+bhHUZUEhkqD/YNPCc65JEsbJtuKeNcXLDjlkBIHLgLTBDTuMKGHszlJqwpoMp FnzyIx3N05tCR55jLoZO9K/gHY7IcoAXy8BB4HUhQS8k6RHWmmQTjnNjQakH69M7EZ4P aaBHsmgxY62DNUJR0UxhFAZulAbdYnnPHos9kwNxwIecRkz5hAbtqycj2Kml6HavHOjm Bcs95KuYqlTGJ8NKtLIOJ7LMmNtVoOwe+JTl44UJkW/f4tHSAJHFY/wTzFogl6QD3DZO SxMQ== X-Gm-Message-State: AOAM533PgD6nzldL4Riz8Dtgyn5JqdkZKrvsyj2pWuuzTvJgFMTaoBjO 0Zwaa1Jz9iQBAwMbkVvSIMQ= X-Google-Smtp-Source: ABdhPJwpUys3xWnUDvktoK//wy8lErbHYUp2Qfgz6eMD9Z1ioqjRSSXpsXKIl/vuSDh+3X9Z8VhlPA== X-Received: by 2002:a5d:5444:: with SMTP id w4mr36550273wrv.202.1619629588555; Wed, 28 Apr 2021 10:06:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 22/30] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Date: Wed, 28 Apr 2021 19:04:02 +0200 Message-Id: <20210428170410.479308-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The 3 map_address() handlers are local to tlb_helper.c, no need to have their prototype declared publically. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 6 ------ target/mips/tcg/sysemu/tlb_helper.c | 13 +++++++------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 558cdca4e84..c1751700731 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,12 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); void r4k_helper_tlbwi(CPUMIPSState *env); void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index bf242f5e65a..a45146a2b21 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -26,8 +26,8 @@ #include "hw/mips/cpudevs.h" =20 /* no MMU emulation */ -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, + target_ulong address, MMUAccessType access_t= ype) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physica= l, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { if (!(env->CP0_Status & (1 << CP0St_ERL))) { @@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint32_t MMID =3D env->CP0_MemoryMapID; --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629595; cv=none; d=zohomail.com; s=zohoarc; b=amWrbBSk0xDR/uiCP7qLZ0qdQ6VEqc7kWZVxoCHp7I8+eE8xy5rwg3u0jSsNNod8RqLTo4IVsuhcbegRZr7x9YmA0ULNrwDyLS8feuOP3yGw4RS75GFFLjHV1liwos+gtVqQnRrRlUh37C+JVphFROLo+SXjQLJuVWTg9/4nYpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629595; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EDhX+WED1Dz1wQl7trAiDfJ6HPpg1cFqmFghcHNe/d0=; b=lHMBoWiAJexQQjd1+saknziOLsGevz0iPwaPBA7ZdIlI77UpQ6byhCUSYSkqvvDiT//34hBetkunoF7skTaeDfwMmG39sZ5SOJfSjvS/02nOdCtswMO+GhC3AXOWaJnJ7crah7x0sgCYt0FejXiIhS0bdotGhcCw+soOlTkCx2M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1619629595624386.4328865556546; Wed, 28 Apr 2021 10:06:35 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id b19-20020a05600c06d3b029014258a636e8so5076976wmn.2 for ; Wed, 28 Apr 2021 10:06:34 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id t14sm464096wrz.55.2021.04.28.10.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EDhX+WED1Dz1wQl7trAiDfJ6HPpg1cFqmFghcHNe/d0=; b=qTQHNOv/20YbT6LuMnFUP8lTQ3TJOX1Fcf6VsKuSDnb4wpwtDKb7/ANzPq+wlV4ZXt Rm0LL6vCdR/R6BuMSStm3O4VuvOR6CfGFb6dbKMmjaprV5/d/+v2UEkoIQN7rjOCANx7 fR/RPh+2yvRSTa7c0QrgNoebqnUEzfVS7ml8BlMU05UXN87+YeAyfY9UdI8n5CAzZU9u +TstGNjN4Za5ko13FM0Bwa41aSpFI66tqtoSwEv92zUDvaGKZn9aKbn8tl8YOqNhXMUr w+fWRje2eau67N7vQSV34FvmrjCuBid+HL3z6tjJpA3mV6tMagv8WT4waFLzbAorVZl3 x00w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EDhX+WED1Dz1wQl7trAiDfJ6HPpg1cFqmFghcHNe/d0=; b=rEWHETN/tUR430wGd+WBlmHMk8VlobA86v+H3xeJxR4Pc6OWfcTP4ItrilhY9tx6dC +2MZ4qzzi9hnKHYicJN/tHovP49mf2nVfRkdPgKmhVEL4tIA7UXnnii+ARzwIXLWX3TS dV7nNB0eEqZAigeqApHooSzYCZ8XRFZBdPN05J+84RIhZRUO47xI+YVGwXhdlaR0UnTw 67XISvAwzxFv3BjGfOFvB6m/+Xe21GA1eB3zSq8oLNGDP/EPGraLx0GaHF/c05UdgYUO FRMczo+ePVccmVvAOC+XV6Hv9BZKQ9FjUN+cuczCq0y3ie1j7v7okFLE86BOtLOUrUq0 pTfw== X-Gm-Message-State: AOAM530DhbD7dA0ipwZ0+jItHJQNXtqi2LvFGcutESZNl0XcRGjlT2fl HYSbmLuRUiYdoSxs0Bwj3FI= X-Google-Smtp-Source: ABdhPJypzdvlQfmHSIDz8P8/ESnVw3xlV/hZIn2TfeRNDPI7A7m/8ehXdg5WrpZ+AJRW7b6Zju7wjQ== X-Received: by 2002:a1c:2:: with SMTP id 2mr32645705wma.113.1619629593289; Wed, 28 Apr 2021 10:06:33 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 23/30] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Date: Wed, 28 Apr 2021 19:04:03 +0200 Message-Id: <20210428170410.479308-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 5 - target/mips/tcg/tcg-internal.h | 3 + target/mips/tcg/sysemu_helper.h.inc | 7 ++ target/mips/cpu.c | 17 --- target/mips/op_helper.c | 100 ----------------- target/mips/tcg/sysemu/special_helper.c | 140 ++++++++++++++++++++++++ target/mips/tcg/sysemu/meson.build | 1 + 7 files changed, 151 insertions(+), 122 deletions(-) create mode 100644 target/mips/tcg/sysemu/special_helper.c diff --git a/target/mips/helper.h b/target/mips/helper.h index bc308e5db13..4ee7916d8b2 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env) DEF_HELPER_1(tlbr, void, env) DEF_HELPER_1(tlbinv, void, env) DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_1(di, tl, env) -DEF_HELPER_1(ei, tl, env) -DEF_HELPER_1(eret, void, env) -DEF_HELPER_1(eretnc, void, env) -DEF_HELPER_1(deret, void, env) DEF_HELPER_3(ginvt, void, env, tl, i32) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index a39ff45d58f..73667b35778 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -10,6 +10,7 @@ #ifndef MIPS_TCG_INTERNAL_H #define MIPS_TCG_INTERNAL_H =20 +#include "tcg/tcg.h" #include "hw/core/cpu.h" #include "cpu.h" =20 @@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1= , int32_t *pagemask); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb); + hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index d136c4160a7..38e55cbf118 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env) /* R6 Multi-threading */ DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) + +/* Special */ +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(eretnc, void, env) +DEF_HELPER_1(deret, void, env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c3159e3d7f3..a33e3b6c202 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -342,23 +342,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } - -# ifndef CONFIG_USER_ONLY -static bool mips_io_recompile_replay_branch(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { - env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - env->hflags &=3D ~MIPS_HFLAG_BMASK; - return true; - } - return false; -} -# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 static bool mips_cpu_has_work(CPUState *cs) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 7a7369bc8a6..a077535194b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -655,106 +655,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg= , uint32_t type) } } =20 -/* Specials */ -target_ulong helper_di(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 & ~(1 << CP0St_IE); - return t0; -} - -target_ulong helper_ei(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 | (1 << CP0St_IE); - return t0; -} - -static void debug_pre_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - qemu_log("\n"); - } -} - -static void debug_post_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -static inline void exception_return(CPUMIPSState *env) -{ - debug_pre_eret(env); - if (env->CP0_Status & (1 << CP0St_ERL)) { - mips_env_set_pc(env, env->CP0_ErrorEPC); - env->CP0_Status &=3D ~(1 << CP0St_ERL); - } else { - mips_env_set_pc(env, env->CP0_EPC); - env->CP0_Status &=3D ~(1 << CP0St_EXL); - } - compute_hflags(env); - debug_post_eret(env); -} - -void helper_eret(CPUMIPSState *env) -{ - exception_return(env); - env->CP0_LLAddr =3D 1; - env->lladdr =3D 1; -} - -void helper_eretnc(CPUMIPSState *env) -{ - exception_return(env); -} - -void helper_deret(CPUMIPSState *env) -{ - debug_pre_eret(env); - - env->hflags &=3D ~MIPS_HFLAG_DM; - compute_hflags(env); - - mips_env_set_pc(env, env->CP0_DEPC); - - debug_post_eret(env); -} #endif /* !CONFIG_USER_ONLY */ =20 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c new file mode 100644 index 00000000000..971883fa385 --- /dev/null +++ b/target/mips/tcg/sysemu/special_helper.c @@ -0,0 +1,140 @@ +/* + * QEMU MIPS emulation: Special opcode helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "internal.h" + +/* Specials */ +target_ulong helper_di(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + qemu_log("\n"); + } +} + +static void debug_post_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 + && env->active_tc.PC !=3D tb->pc) { + env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &=3D ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} + +static inline void exception_return(CPUMIPSState *env) +{ + debug_pre_eret(env); + if (env->CP0_Status & (1 << CP0St_ERL)) { + mips_env_set_pc(env, env->CP0_ErrorEPC); + env->CP0_Status &=3D ~(1 << CP0St_ERL); + } else { + mips_env_set_pc(env, env->CP0_EPC); + env->CP0_Status &=3D ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(env); +} + +void helper_eret(CPUMIPSState *env) +{ + exception_return(env); + env->CP0_LLAddr =3D 1; + env->lladdr =3D 1; +} + +void helper_eretnc(CPUMIPSState *env) +{ + exception_return(env); +} + +void helper_deret(CPUMIPSState *env) +{ + debug_pre_eret(env); + + env->hflags &=3D ~MIPS_HFLAG_DM; + compute_hflags(env); + + mips_env_set_pc(env, env->CP0_DEPC); + + debug_post_eret(env); +} diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 73ab9571ba6..4da2c577b20 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'special_helper.c', 'tlb_helper.c', )) --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629605; cv=none; d=zohomail.com; s=zohoarc; b=VSgonSYD+D/SBg5dDyDzXC+PakoBCA8mnFmcDyzEzT4rdsUUNB+vANSfUX5DRGiZfpCXDjsKmCgrtazC0/5FNgStattYRLq4lfZ3GkwKheE84k/or2dcUmkspW+TGrsE+DOgQyUzwCdKvpE/uxDMuwwRR0r8X1+0ZttllbHiCqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629605; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DMCAo+wC8HY/UfjCzg1y7H88VRtuoDpPVZxw1qG03XE=; b=Ceq10b4qmXqm5/GgGnBTOeMe8vCY6IG2twhfk+JSP8mEtLFF4ZAWF3pMiWoslgRyi87tb3z2wkIRmixk9/n+bIgl90bZ8jPR4YrRSjLKAN2RuO+aZSW5uRVnoh+SnexYw0Vh5Ilks5YnBxpk5WPgsTGmlnfguQqyBmAbwxwz/ww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1619629605356565.6521379328383; Wed, 28 Apr 2021 10:06:45 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id x7so63798621wrw.10 for ; Wed, 28 Apr 2021 10:06:44 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id p14sm468189wrx.88.2021.04.28.10.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DMCAo+wC8HY/UfjCzg1y7H88VRtuoDpPVZxw1qG03XE=; b=CQe0DmiYEbrM84r4S/vW5BpHQiRVKsTHbpzrIMhBSx0fa08ZA9HQQx613iEFc794sy 5lG5J0Z49W7EKpmPSv3XSN1ebOCXesd0CMMQbd64XR4v+E/TFLtqIbRvFF077YFru4wp yZOntwoC5hMQHSS9rpm7RahyRuhE4JWdOrQlmv772/Cnqd0b4mdGhSmzWTgGDXIktnKb y0XcliPVwq/uOYbMm/emvkbecuC3h09gW2FfYNswvOgN3C/BIMfQGZoDQqVUK1FO7HzE LfKllK0SuAgvLoth4uE0d5rXLc/lXN/mEnu41Gmu1a01Ove6TNgrwCZ3ffQsuH4nGqnC NM8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DMCAo+wC8HY/UfjCzg1y7H88VRtuoDpPVZxw1qG03XE=; b=XQbKyAunvdhYPS/W7b1t4tRA6G2itMFumy7c2awsrYKQTbt9vQOEH5m/LLb3Aob6It qv1xc0vxP87bC8a1gyL/vD6QNNrlKnnsNsuNHtynJtUBrTNzi3CFkPAxaG5lLwTk5Jb6 N/bzDccahxQIdU+MhEJhoCVLD+sWOVqBKTd61HRWYZ00W/ob0HjRwly+qS0MBqO2uvHD 8IrIPMbv+sKFZHs7KpjSScw7zxuNKUkbe7XEc+R1SiACKKEH5fynDKSXmMcyXnpyhk3D lfq76OWd4HrBtsPa5hxUHig/r3SNURc4cYb86+dzlHkO1ltFxlhV0rwpEhpjd/3rSq2/ JKiw== X-Gm-Message-State: AOAM533YRveQPUgv2s4aOAuJJ+lURpxzseCd0pLEmg9+BIlN9svhN0IR XvIvIwpNbGj7R8U0n09wi18= X-Google-Smtp-Source: ABdhPJxqnTk4fM0HoNWEYMuAwb//kipq6mv3UU/OLdnK04N/skob3i/hsltnNtn/zQR4xsf6CvKquA== X-Received: by 2002:adf:e60d:: with SMTP id p13mr27846688wrm.326.1619629603059; Wed, 28 Apr 2021 10:06:43 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 24/30] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c Date: Wed, 28 Apr 2021 19:04:04 +0200 Message-Id: <20210428170410.479308-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move helper_cache() to tcg/sysemu/special_helper.c. The CACHE opcode is privileged and is not accessible in user emulation. However we get a link failure when restricting the symbol to sysemu. For now, add a stub helper to satisfy linking, which abort if ever called. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v4: qemu_build_not_reached -> g_assert_not_reached (rth) --- target/mips/helper.h | 2 -- target/mips/tcg/sysemu_helper.h.inc | 1 + target/mips/op_helper.c | 35 ------------------------- target/mips/tcg/sysemu/special_helper.c | 33 +++++++++++++++++++++++ target/mips/translate.c | 13 +++++++++ 5 files changed, 47 insertions(+), 37 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 4ee7916d8b2..d49620f9282 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -614,8 +614,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -DEF_HELPER_3(cache, void, env, tl, i32) - #ifndef CONFIG_USER_ONLY #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 38e55cbf118..1ccbf687237 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -173,3 +173,4 @@ DEF_HELPER_1(ei, tl, env) DEF_HELPER_1(eret, void, env) DEF_HELPER_1(eretnc, void, env) DEF_HELPER_1(deret, void, env) +DEF_HELPER_3(cache, void, env, tl, i32) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a077535194b..a7fe1de8c42 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -788,38 +788,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, } } #endif /* !CONFIG_USER_ONLY */ - -void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) -{ -#ifndef CONFIG_USER_ONLY - static const char *const type_name[] =3D { - "Primary Instruction", - "Primary Data or Unified Primary", - "Tertiary", - "Secondary" - }; - uint32_t cache_type =3D extract32(op, 0, 2); - uint32_t cache_operation =3D extract32(op, 2, 3); - target_ulong index =3D addr & 0x1fffffff; - - switch (cache_operation) { - case 0b010: /* Index Store Tag */ - memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b001: /* Index Load Tag */ - memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b000: /* Index Invalidate */ - case 0b100: /* Hit Invalidate */ - case 0b110: /* Hit Writeback */ - /* no-op */ - break; - default: - qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", - cache_operation, type_name[cache_type]); - break; - } -#endif -} diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 971883fa385..2a2afb49e81 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -138,3 +138,36 @@ void helper_deret(CPUMIPSState *env) =20 debug_post_eret(env); } + +void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) +{ + static const char *const type_name[] =3D { + "Primary Instruction", + "Primary Data or Unified Primary", + "Tertiary", + "Secondary" + }; + uint32_t cache_type =3D extract32(op, 0, 2); + uint32_t cache_operation =3D extract32(op, 2, 3); + target_ulong index =3D addr & 0x1fffffff; + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ + memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b001: /* Index Load Tag */ + memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; + default: + qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", + cache_operation, type_name[cache_type]); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index f0ae3716022..c03a8ae1fed 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -39,6 +39,19 @@ #include "fpu_helper.h" #include "translate.h" =20 +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { g_assert_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) +#endif + enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629610; cv=none; d=zohomail.com; s=zohoarc; b=SpQ1OMsBstS/N3Fdcjy2TaRnbdMCHLGY996J2bjHQ0Pw0n1mPSyA5OX9FRrDsn7E/07AqjviUYXYOPz+OZavphYRp15NHQPvhp3TrVwfEQi3f71NwlgDR91IWc0zkaCPEcyMQKQ6QnU1ItW+cdL2lDZjbkGClu19jKI/C4IWSl8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629610; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RE8Rh/P8oiUuNdAEBdEJjzjODSOJEocW4+dEbr6XfbY=; b=YZSfFvUdjYtXjZ5/jj6VToZ6kiWUvILPjYwTTQTAp2zLy5GaT+zfLCXD3EvbWNVWPJWdmWf4jkVeuxvHolaruc1+uGaR43JezF9YOyMGRoIQCaY0zNcMneL3BZUqdrFNZpkQF0PD2Quz3daVNkhlZu82inHXYJlsSHPBOhDIZE4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1619629610280769.7458027261883; Wed, 28 Apr 2021 10:06:50 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id y124-20020a1c32820000b029010c93864955so9705688wmy.5 for ; Wed, 28 Apr 2021 10:06:49 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l12sm461226wrm.76.2021.04.28.10.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RE8Rh/P8oiUuNdAEBdEJjzjODSOJEocW4+dEbr6XfbY=; b=Knx8ljG4xguvm/WkEMnSXf9DVADA0zmPlN4HHH7YA7JgNnWJAQjbOozmhSb1zldWJ2 ckSkv53CDqs8PXm/ry3YXHzDNw3/lsLTL7fUcLCaOfDNTQKxJgls56ybAuVof9AMMnqA UP73g0RbozgDuUrUWGvIUV4q6qdJbwBnO5ICRuke56KQa7FocuGhG23tkOD9l9BR5TTA Q+biTOS23vRYsNeJ3KpKjvanS1b6F9RxnpGk8E5uMg+QG2vAoogA7dZwxr/ztU9WlJzF zo2M0+9BcEQ0CDjRFtHagnDeNglE4xnPZxba+EX0x/1MVcVAdYGNDJOAQ4kXLEIwn+Uc 22vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RE8Rh/P8oiUuNdAEBdEJjzjODSOJEocW4+dEbr6XfbY=; b=q+LLr5g5n+DozrjpmMCDWvWCCrk9KMq3EMIX62LG+pkfv1ckdRIw6fpd9cInUg03Z/ PLjCbk5FGuNiV7Isw2Eo6apUlMc6Yk5z9hSaAtRt5DhQ4bKImzuUPsHG8yXbikOIBXAE tkT67V8A0AH60nHeiS6IXsGXnoTfC6sgrbefYNjgIMCHLiquhAXHOd+j99hPCb24KIaP k9kuZSPiyOxowIAR/v8QoPFeKoEaAuW3dJ5wc0LpquUrG9nU5CzRKilQPTduJGYtEmao a49ys9r/b88hqJyXVq0FY/L6oAAWpMffC8tj/ZWzMxR3ComX/IeXrxbwt94qr0yoFZ7a 4U0w== X-Gm-Message-State: AOAM531LHOFgeQVtKZ9vNwnYDPM6RWDAqgIlQKwtHCWNDlvhV8JdJgmI AdNMF+jR4SRjvSTTZ6HbYtM= X-Google-Smtp-Source: ABdhPJxh/Pd2aMEXy+ysfgqZa4Ymx4Phxx3F6f83OdRQJJ+gNCw+PDjgdiutueXDJ+E9qKuK1v9PzA== X-Received: by 2002:a1c:f608:: with SMTP id w8mr5708278wmc.44.1619629607861; Wed, 28 Apr 2021 10:06:47 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 25/30] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Date: Wed, 28 Apr 2021 19:04:05 +0200 Message-Id: <20210428170410.479308-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move TLB management helpers to tcg/sysemu/tlb_helper.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 10 - target/mips/internal.h | 7 - target/mips/tcg/sysemu_helper.h.inc | 9 + target/mips/op_helper.c | 333 ---------------------------- target/mips/tcg/sysemu/tlb_helper.c | 331 +++++++++++++++++++++++++++ 5 files changed, 340 insertions(+), 350 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d49620f9282..ba301ae160d 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -202,16 +202,6 @@ FOP_PROTO(sune) FOP_PROTO(sne) #undef FOP_PROTO =20 -/* Special functions */ -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(tlbwi, void, env) -DEF_HELPER_1(tlbwr, void, env) -DEF_HELPER_1(tlbp, void, env) -DEF_HELPER_1(tlbr, void, env) -DEF_HELPER_1(tlbinv, void, env) -DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_3(ginvt, void, env, tl, i32) -#endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) DEF_HELPER_1(rdhwr_synci_step, tl, env) DEF_HELPER_1(rdhwr_cc, tl, env) diff --git a/target/mips/internal.h b/target/mips/internal.h index c1751700731..a1c7f658c2b 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,13 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void r4k_helper_tlbwi(CPUMIPSState *env); -void r4k_helper_tlbwr(CPUMIPSState *env); -void r4k_helper_tlbp(CPUMIPSState *env); -void r4k_helper_tlbr(CPUMIPSState *env); -void r4k_helper_tlbinv(CPUMIPSState *env); -void r4k_helper_tlbinvf(CPUMIPSState *env); - void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 1ccbf687237..4353a966f97 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -167,6 +167,15 @@ DEF_HELPER_1(evpe, tl, env) DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) =20 +/* TLB */ +DEF_HELPER_1(tlbwi, void, env) +DEF_HELPER_1(tlbwr, void, env) +DEF_HELPER_1(tlbp, void, env) +DEF_HELPER_1(tlbr, void, env) +DEF_HELPER_1(tlbinv, void, env) +DEF_HELPER_1(tlbinvf, void, env) +DEF_HELPER_3(ginvt, void, env, tl, i32) + /* Special */ DEF_HELPER_1(di, tl, env) DEF_HELPER_1(ei, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a7fe1de8c42..cb2a7e96fc3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -324,339 +324,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_u= long arg) return env->CP0_YQMask; } =20 -#ifndef CONFIG_USER_ONLY -/* TLB management */ -static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) -{ - /* Discard entries from env->tlb[first] onwards. */ - while (env->tlb->tlb_in_use > first) { - r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); - } -} - -static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) -{ -#if defined(TARGET_MIPS64) - return extract64(entrylo, 6, 54); -#else - return extract64(entrylo, 6, 24) | /* PFN */ - (extract64(entrylo, 32, 32) << 24); /* PFNX */ -#endif -} - -static void r4k_fill_tlb(CPUMIPSState *env, int idx) -{ - r4k_tlb_t *tlb; - uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); - - /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { - tlb->EHINV =3D 1; - return; - } - tlb->EHINV =3D 0; - tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - tlb->VPN &=3D env->SEGMask; -#endif - tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - tlb->MMID =3D env->CP0_MemoryMapID; - tlb->PageMask =3D env->CP0_PageMask; - tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; - tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; - tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; - tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; - tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; - tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; - tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; - tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; -} - -void r4k_helper_tlbinv(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - if (!tlb->G && tlb_mmid =3D=3D MMID) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbinvf(CPUMIPSState *env) -{ - int idx; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbwi(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - VPN &=3D env->SEGMask; -#endif - EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; - G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; - RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; - V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; - RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* - * Discard cached TLB entries, unless tlbwi is just upgrading access - * permissions on the current entry. - */ - if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || - (!tlb->EHINV && EHINV) || - (tlb->V0 && !V0) || (tlb->D0 && !D0) || - (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || - (tlb->V1 && !V1) || (tlb->D1 && !D1) || - (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - } - - r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(env, idx); -} - -void r4k_helper_tlbwr(CPUMIPSState *env) -{ - int r =3D cpu_mips_get_random(env); - - r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(env, r); -} - -void r4k_helper_tlbp(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - r4k_tlb_t *tlb; - target_ulong mask; - target_ulong tag; - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - int i; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (i =3D 0; i < env->tlb->nb_tlb; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { - /* TLB match */ - env->CP0_Index =3D i; - break; - } - } - if (i =3D=3D env->tlb->nb_tlb) { - /* No match. Discard any shadow entries, if any of them match. */ - for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { - r4k_mips_tlb_flush_extra(env, i); - break; - } - } - - env->CP0_Index |=3D 0x80000000; - } -} - -static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) -{ -#if defined(TARGET_MIPS64) - return tlb_pfn << 6; -#else - return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ - (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ -#endif -} - -void r4k_helper_tlbr(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* If this will change the current ASID/MMID, flush qemu's TLB. */ - if (MMID !=3D tlb_mmid) { - cpu_mips_tlb_flush(env); - } - - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - - if (tlb->EHINV) { - env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; - env->CP0_PageMask =3D 0; - env->CP0_EntryLo0 =3D 0; - env->CP0_EntryLo1 =3D 0; - } else { - env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; - env->CP0_MemoryMapID =3D tlb->MMID; - env->CP0_PageMask =3D tlb->PageMask; - env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | - ((uint64_t)tlb->RI0 << CP0EnLo_RI) | - ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); - env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | - ((uint64_t)tlb->RI1 << CP0EnLo_RI) | - ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); - } -} - -void helper_tlbwi(CPUMIPSState *env) -{ - env->tlb->helper_tlbwi(env); -} - -void helper_tlbwr(CPUMIPSState *env) -{ - env->tlb->helper_tlbwr(env); -} - -void helper_tlbp(CPUMIPSState *env) -{ - env->tlb->helper_tlbp(env); -} - -void helper_tlbr(CPUMIPSState *env) -{ - env->tlb->helper_tlbr(env); -} - -void helper_tlbinv(CPUMIPSState *env) -{ - env->tlb->helper_tlbinv(env); -} - -void helper_tlbinvf(CPUMIPSState *env) -{ - env->tlb->helper_tlbinvf(env); -} - -static void global_invalidate_tlb(CPUMIPSState *env, - uint32_t invMsgVPN2, - uint8_t invMsgR, - uint32_t invMsgMMid, - bool invAll, - bool invVAMMid, - bool invMMid, - bool invVA) -{ - - int idx; - r4k_tlb_t *tlb; - bool VAMatch; - bool MMidMatch; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VAMatch =3D - (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) -#ifdef TARGET_MIPS64 - && - (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) -#endif - ); - MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; - if ((invAll && (idx > env->CP0_Wired)) || - (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || - (VAMatch && invVA) || - (MMidMatch && !(tlb->G) && invMMid)) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) -{ - bool invAll =3D type =3D=3D 0; - bool invVA =3D type =3D=3D 1; - bool invMMid =3D type =3D=3D 2; - bool invVAMMid =3D type =3D=3D 3; - uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); - uint8_t invMsgR =3D 0; - uint32_t invMsgMMid =3D env->CP0_MemoryMapID; - CPUState *other_cs =3D first_cpu; - -#ifdef TARGET_MIPS64 - invMsgR =3D extract64(arg, 62, 2); -#endif - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, - invAll, invVAMMid, invMMid, invVA); - } -} - -#endif /* !CONFIG_USER_ONLY */ - static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index a45146a2b21..259f780d19f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -24,6 +24,337 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" +#include "exec/helper-proto.h" + +/* TLB management */ +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) +{ +#if defined(TARGET_MIPS64) + return extract64(entrylo, 6, 54); +#else + return extract64(entrylo, 6, 24) | /* PFN */ + (extract64(entrylo, 32, 32) << 24); /* PFNX */ +#endif +} + +static void r4k_fill_tlb(CPUMIPSState *env, int idx) +{ + r4k_tlb_t *tlb; + uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { + tlb->EHINV =3D 1; + return; + } + tlb->EHINV =3D 0; + tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &=3D env->SEGMask; +#endif + tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + tlb->MMID =3D env->CP0_MemoryMapID; + tlb->PageMask =3D env->CP0_PageMask; + tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; + tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; + tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; + tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; + tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; + tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; +} + +static void r4k_helper_tlbinv(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + if (!tlb->G && tlb_mmid =3D=3D MMID) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbinvf(CPUMIPSState *env) +{ + int idx; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbwi(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &=3D env->SEGMask; +#endif + EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; + G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; + RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; + V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; + RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ + if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || + (!tlb->EHINV && EHINV) || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1) || + (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(env, idx); +} + +static void r4k_helper_tlbwr(CPUMIPSState *env) +{ + int r =3D cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(env, r); +} + +static void r4k_helper_tlbp(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + int i; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (i =3D 0; i < env->tlb->nb_tlb; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { + /* TLB match */ + env->CP0_Index =3D i; + break; + } + } + if (i =3D=3D env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { + r4k_mips_tlb_flush_extra(env, i); + break; + } + } + + env->CP0_Index |=3D 0x80000000; + } +} + +static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) +{ +#if defined(TARGET_MIPS64) + return tlb_pfn << 6; +#else + return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ + (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ +#endif +} + +static void r4k_helper_tlbr(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* If this will change the current ASID/MMID, flush qemu's TLB. */ + if (MMID !=3D tlb_mmid) { + cpu_mips_tlb_flush(env); + } + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + if (tlb->EHINV) { + env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; + env->CP0_PageMask =3D 0; + env->CP0_EntryLo0 =3D 0; + env->CP0_EntryLo1 =3D 0; + } else { + env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; + env->CP0_MemoryMapID =3D tlb->MMID; + env->CP0_PageMask =3D tlb->PageMask; + env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + ((uint64_t)tlb->RI0 << CP0EnLo_RI) | + ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); + env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + ((uint64_t)tlb->RI1 << CP0EnLo_RI) | + ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); + } +} + +void helper_tlbwi(CPUMIPSState *env) +{ + env->tlb->helper_tlbwi(env); +} + +void helper_tlbwr(CPUMIPSState *env) +{ + env->tlb->helper_tlbwr(env); +} + +void helper_tlbp(CPUMIPSState *env) +{ + env->tlb->helper_tlbp(env); +} + +void helper_tlbr(CPUMIPSState *env) +{ + env->tlb->helper_tlbr(env); +} + +void helper_tlbinv(CPUMIPSState *env) +{ + env->tlb->helper_tlbinv(env); +} + +void helper_tlbinvf(CPUMIPSState *env) +{ + env->tlb->helper_tlbinvf(env); +} + +static void global_invalidate_tlb(CPUMIPSState *env, + uint32_t invMsgVPN2, + uint8_t invMsgR, + uint32_t invMsgMMid, + bool invAll, + bool invVAMMid, + bool invMMid, + bool invVA) +{ + + int idx; + r4k_tlb_t *tlb; + bool VAMatch; + bool MMidMatch; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VAMatch =3D + (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) +#ifdef TARGET_MIPS64 + && + (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) +#endif + ); + MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; + if ((invAll && (idx > env->CP0_Wired)) || + (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || + (VAMatch && invVA) || + (MMidMatch && !(tlb->G) && invMMid)) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) +{ + bool invAll =3D type =3D=3D 0; + bool invVA =3D type =3D=3D 1; + bool invMMid =3D type =3D=3D 2; + bool invVAMMid =3D type =3D=3D 3; + uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); + uint8_t invMsgR =3D 0; + uint32_t invMsgMMid =3D env->CP0_MemoryMapID; + CPUState *other_cs =3D first_cpu; + +#ifdef TARGET_MIPS64 + invMsgR =3D extract64(arg, 62, 2); +#endif + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, + invAll, invVAMMid, invMMid, invVA); + } +} =20 /* no MMU emulation */ static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619629615; cv=none; d=zohomail.com; s=zohoarc; b=Zx6OvWiMh7beBQtqFTXyo6M5giNjlvhTiaIEEQ/NgYYm8q+vDUIksiBq3JMEArd+XAvSZzszwTApHuujlQkKyBHNrZBtjlrcSYOO5Bb3SfwHpHHBUdJ9nR8ytAaNGJKboog77Rm8U3gzo9cEYmpbBH3zLTu0WkWLh431CWOdSZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629615; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SXUq+bSQsPw/8chasWcQ1MIj+V40BxgUhki5IPJZ9tM=; b=h65wwm/p0ve3xCudduWz1X0RocWpw1Yvgt0WVpfjqHs8q/pTVHFNrVf1aeiLU+nylqoA258HB9QkCf7T7FQe0ZH9KGx1MljLVZNt8/jHddhpje5/UF6c7JCQAA9KwDLlXJzeY55Eelo0DJjp/+uGCIw4BmkO6EIQBZgSQ2sxNYY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1619629614813572.7411396781063; Wed, 28 Apr 2021 10:06:54 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id x5so13560725wrv.13 for ; Wed, 28 Apr 2021 10:06:53 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id u5sm435087wrt.71.2021.04.28.10.06.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SXUq+bSQsPw/8chasWcQ1MIj+V40BxgUhki5IPJZ9tM=; b=l4oZv5at3tX2KiYCKbZnu9ykrb92vw7V8mrPJaqOhEsXRlTG/rytRckoCp+6/QqQf6 8t3z06Npqul16woSBdOmJLTAjTteQVQ1sCRvDNS7PC723gfE4JQ03ETiaQpy/7+Y4DVM hVRgnQv4BODDDST4xMnt4U3LYwuIb4tZa7qb6yIAoXGn6ipgvS9ELggsV3oRPCTAytA6 dyEXfASYICs5iE/F5dyM79/Te6H0naKmd8Unb3x0upgmS99OUtAfPCch9hQmvuDpcuLw 4Mk/Mw3kViu7beI91GYbIxgWIx/6DES6kOITOBGsC9rGaY/1OPH7sVVuekqXaSIRHFYk u0bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SXUq+bSQsPw/8chasWcQ1MIj+V40BxgUhki5IPJZ9tM=; b=RpmoLCIol9vr1dhwE1thiK2p6O1xEBrG63QlxDqf6OahO20UHKWvgBy+2eOqOHuC9G EEBIgapQ7a2afrVlpVC8cIh1/OSWNzSmAqXHPCzmMC5zrr3Pv5tZ/LVL4hMp97QoORgA NlgSM6ZYx8dJW7EN69yjRCL+bSwZY2Z7m8YaweK1yGki0Gv/J9reO5rT6ZyaBB2a0BML WN0FxHsT+w3OmYzLEVXuFIAHSpeU5LnLwh0ma21UXjxVyvPeI4CF29/B/N7zca7efwQh 0IrgAOHpmjfkK8CjVBeepMiRik3XNUbcspReBBZs7FdWtaEVSeA9MPkPV696TaFK3L+f 7Y7A== X-Gm-Message-State: AOAM530jmtSyiie7/7CNkqpd5ybvNWYUKeJNcMUmwWVQr/Tb6+LT84HY nI+5EgKlCrkQpw1yFtig7k0= X-Google-Smtp-Source: ABdhPJywP9fCyLNC4A0mXDHuNILGjEFEGPI/L1vKukEzvA2N0UDtbqS1rKiL2IPXZURM+eDx7YtVQQ== X-Received: by 2002:a5d:6d85:: with SMTP id l5mr3515246wrs.22.1619629612750; Wed, 28 Apr 2021 10:06:52 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 26/30] target/mips: Move exception management code to exception.c Date: Wed, 28 Apr 2021 19:04:06 +0200 Message-Id: <20210428170410.479308-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 13 --- target/mips/tcg/tcg-internal.h | 14 +++ target/mips/cpu.c | 113 ---------------------- target/mips/exception.c | 167 +++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 37 -------- target/mips/meson.build | 1 + 6 files changed, 182 insertions(+), 163 deletions(-) create mode 100644 target/mips/exception.c diff --git a/target/mips/internal.h b/target/mips/internal.h index a1c7f658c2b..07573c3e38f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -80,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, @@ -410,16 +409,4 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *c= pu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); =20 -const char *mips_exception_name(int32_t exception); - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, - int error_code, uintptr_t pc); - -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) -{ - do_raise_exception_err(env, exception, 0, pc); -} - #endif diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 73667b35778..75aa3ef98ed 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -14,11 +14,25 @@ #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +const char *mips_exception_name(int32_t exception); + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, + int error_code, uintptr_t pc); + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + #if !defined(CONFIG_USER_ONLY) =20 void mmu_init(CPUMIPSState *env, const mips_def_t *def); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a33e3b6c202..daa9a4791ee 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -218,112 +218,12 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *= f, int flags) } } =20 -static const char * const excp_names[EXCP_LAST + 1] =3D { - [EXCP_RESET] =3D "reset", - [EXCP_SRESET] =3D "soft reset", - [EXCP_DSS] =3D "debug single step", - [EXCP_DINT] =3D "debug interrupt", - [EXCP_NMI] =3D "non-maskable interrupt", - [EXCP_MCHECK] =3D "machine check", - [EXCP_EXT_INTERRUPT] =3D "interrupt", - [EXCP_DFWATCH] =3D "deferred watchpoint", - [EXCP_DIB] =3D "debug instruction breakpoint", - [EXCP_IWATCH] =3D "instruction fetch watchpoint", - [EXCP_AdEL] =3D "address error load", - [EXCP_AdES] =3D "address error store", - [EXCP_TLBF] =3D "TLB refill", - [EXCP_IBE] =3D "instruction bus error", - [EXCP_DBp] =3D "debug breakpoint", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_BREAK] =3D "break", - [EXCP_CpU] =3D "coprocessor unusable", - [EXCP_RI] =3D "reserved instruction", - [EXCP_OVERFLOW] =3D "arithmetic overflow", - [EXCP_TRAP] =3D "trap", - [EXCP_FPE] =3D "floating point", - [EXCP_DDBS] =3D "debug data break store", - [EXCP_DWATCH] =3D "data watchpoint", - [EXCP_LTLBL] =3D "TLB modify", - [EXCP_TLBL] =3D "TLB load", - [EXCP_TLBS] =3D "TLB store", - [EXCP_DBE] =3D "data bus error", - [EXCP_DDBL] =3D "debug data break load", - [EXCP_THREAD] =3D "thread", - [EXCP_MDMX] =3D "MDMX", - [EXCP_C2E] =3D "precise coprocessor 2", - [EXCP_CACHE] =3D "cache error", - [EXCP_TLBXI] =3D "TLB execute-inhibit", - [EXCP_TLBRI] =3D "TLB read-inhibit", - [EXCP_MSADIS] =3D "MSA disabled", - [EXCP_MSAFPE] =3D "MSA floating point", -}; - -const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); vp->env.exception_base =3D address; } =20 -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); - bad_pc =3D env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index =3D exception; - env->error_code =3D error_code; - - cpu_loop_exit_restore(cs, pc); -} - static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -331,19 +231,6 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_env_set_pc(&cpu->env, value); } =20 -#ifdef CONFIG_TCG -static void mips_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - env->active_tc.PC =3D tb->pc; - env->hflags &=3D ~MIPS_HFLAG_BMASK; - env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; -} -#endif /* CONFIG_TCG */ - static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu =3D MIPS_CPU(cs); diff --git a/target/mips/exception.c b/target/mips/exception.c new file mode 100644 index 00000000000..4fb8b00711d --- /dev/null +++ b/target/mips/exception.c @@ -0,0 +1,167 @@ +/* + * MIPS Exceptions processing helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + bad_pc =3D env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) +{ + do_raise_exception_err(env, exception, error_code, 0); +} + +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, GETPC()); +} + +void helper_raise_exception_debug(CPUMIPSState *env) +{ + do_raise_exception(env, EXCP_DEBUG, 0); +} + +static void raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, 0); +} + +void helper_wait(CPUMIPSState *env) +{ + CPUState *cs =3D env_cpu(env); + + cs->halted =3D 1; + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ + raise_exception(env, EXCP_HLT); +} + +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + env->active_tc.PC =3D tb->pc; + env->hflags &=3D ~MIPS_HFLAG_BMASK; + env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +static const char * const excp_names[EXCP_LAST + 1] =3D { + [EXCP_RESET] =3D "reset", + [EXCP_SRESET] =3D "soft reset", + [EXCP_DSS] =3D "debug single step", + [EXCP_DINT] =3D "debug interrupt", + [EXCP_NMI] =3D "non-maskable interrupt", + [EXCP_MCHECK] =3D "machine check", + [EXCP_EXT_INTERRUPT] =3D "interrupt", + [EXCP_DFWATCH] =3D "deferred watchpoint", + [EXCP_DIB] =3D "debug instruction breakpoint", + [EXCP_IWATCH] =3D "instruction fetch watchpoint", + [EXCP_AdEL] =3D "address error load", + [EXCP_AdES] =3D "address error store", + [EXCP_TLBF] =3D "TLB refill", + [EXCP_IBE] =3D "instruction bus error", + [EXCP_DBp] =3D "debug breakpoint", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_BREAK] =3D "break", + [EXCP_CpU] =3D "coprocessor unusable", + [EXCP_RI] =3D "reserved instruction", + [EXCP_OVERFLOW] =3D "arithmetic overflow", + [EXCP_TRAP] =3D "trap", + [EXCP_FPE] =3D "floating point", + [EXCP_DDBS] =3D "debug data break store", + [EXCP_DWATCH] =3D "data watchpoint", + [EXCP_LTLBL] =3D "TLB modify", + [EXCP_TLBL] =3D "TLB load", + [EXCP_TLBS] =3D "TLB store", + [EXCP_DBE] =3D "data bus error", + [EXCP_DDBL] =3D "debug data break load", + [EXCP_THREAD] =3D "thread", + [EXCP_MDMX] =3D "MDMX", + [EXCP_C2E] =3D "precise coprocessor 2", + [EXCP_CACHE] =3D "cache error", + [EXCP_TLBXI] =3D "TLB execute-inhibit", + [EXCP_TLBRI] =3D "TLB read-inhibit", + [EXCP_MSADIS] =3D "MSA disabled", + [EXCP_MSAFPE] =3D "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void do_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code, uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index =3D exception; + env->error_code =3D error_code; + + cpu_loop_exit_restore(cs, pc); +} diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index cb2a7e96fc3..ce1549c9854 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -26,30 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" =20 -/*************************************************************************= ****/ -/* Exceptions processing helpers */ - -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) -{ - do_raise_exception_err(env, exception, error_code, 0); -} - -void helper_raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, GETPC()); -} - -void helper_raise_exception_debug(CPUMIPSState *env) -{ - do_raise_exception(env, EXCP_DEBUG, 0); -} - -static void raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, 0); -} - /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { @@ -399,19 +375,6 @@ void helper_pmon(CPUMIPSState *env, int function) } } =20 -void helper_wait(CPUMIPSState *env) -{ - CPUState *cs =3D env_cpu(env); - - cs->halted =3D 1; - cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* - * Last instruction in the block, PC was updated before - * - no need to recover PC and icount. - */ - raise_exception(env, EXCP_HLT); -} - #if !defined(CONFIG_USER_ONLY) =20 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/mips/meson.build b/target/mips/meson.build index ff5eb210dfd..e08077bfc18 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -24,6 +24,7 @@ mips_tcg_ss.add(gen) mips_tcg_ss.add(files( 'dsp_helper.c', + 'exception.c', 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619629621; cv=none; d=zohomail.com; s=zohoarc; b=nJxNmkbrPOSVcamcWcp9/E2zpoyIWWiJ9PlglD8Cpqv8IoOXVjp6vOBdMizC0YsTHRRQlkcrLkvHs8/dYD5+ywG/NuR2BnAm3LdkMJyUwsmkcQuub05Vjyrgsb77EnnCWnVnwPog/Wo07loJ5TeMjg3G+tKZgQz2k1K5V6LCad8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629621; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yk51dUmawdQzcvfpaEpKPBSg/BRf/V0jzLrf3yewDso=; b=noejbaR5AZRbn3isyleUs5hFMfYHQQJ8s2i63CBvUHf3nEZFvsBPp64p0INH8aKNa+FOyJe04EggJRlgaLP2PWGc1QShZN/0INVxUg6Sux0WQ9kHSD4alQrKGE+FcUYqBYORPkV5xXwYdHsE4hAsLOIbBtvagcVfNuYvfFPvTg4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 161962962106648.642057816401916; Wed, 28 Apr 2021 10:07:01 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id d11so5991461wrw.8 for ; Wed, 28 Apr 2021 10:06:59 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q16sm350822wmj.24.2021.04.28.10.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:06:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yk51dUmawdQzcvfpaEpKPBSg/BRf/V0jzLrf3yewDso=; b=EI52mefghT9SjJQ1ieByfLVLbmaMFFeqhdxt7oVV8/3uZHsLskykCkJljuKTPB1yIb 2I4yYmM6HC6xJoZ6ZVXQCtMfB8/wADdbA5aCil31EKECOseluZAEBDWZDQB+zhT0PBAY urrrO5c49Z6hBONy6HjSR1ZxLq1aq8kRF6Bfwo8gptT0vn/vxh8zWj1J7+1BebNJA8Cz sJmqYxp7LVOUO+WRIVQxRBOILfmXY9H0hH/kU2nvWBUZobrsN+Em3gvNF/thrsn5IETp TbcycAWLw0s7VfVPv+W01amGefKQi4FMQRH6bgxv0eR7vCF2Am1O8ZCG8XT0K3G9XjR+ oc0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yk51dUmawdQzcvfpaEpKPBSg/BRf/V0jzLrf3yewDso=; b=tT3tYTEkpUbI1qaiRBq6S1tmBSC5Zhob1byHX+/SYGbRKMusan3D1gmrv4OO9dOFFk 5HlumNJHHcAMFcUw0OfBs2OaWl+ftNpRkO4cLogpGfFcSoZ2o53zCNiqTWL35buaNAaO 6sK8qWhbj6scXqweMEzfOSrt4i7+aUPBxdpJ6LNNpjtcEAHfj6D01/cNVRDmHSVMNecO pBojgDiTXfZ/s4BkSalG71IOLAJ7PgDaSiy6pn+ycf9r8AecOjX5m/0dgau/p22jlioh 62E4Hr+p8mb6dyfRGM4GUy5zIGQRDvPey68HilRLXjH7125drCh9fHqZEYihitYMaQbT aJKQ== X-Gm-Message-State: AOAM532jiQWRsQUSa8yDJxRwmFV5//Ag4t3lLI9yMu4K8lL5FKWstVAp ZfhvGAmF0MBs+UPg/PETj6g= X-Google-Smtp-Source: ABdhPJy/1SZ2nsq9W+w3IKsL2WOIgR1qOM1Sx2XDqbEPeRm/BOs7VSIuyGE1KyoGiLTJMJ0zMNHVcg== X-Received: by 2002:adf:df0a:: with SMTP id y10mr30165979wrl.189.1619629617562; Wed, 28 Apr 2021 10:06:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 27/30] target/mips: Move CP0 helpers to sysemu/cp0.c Date: Wed, 28 Apr 2021 19:04:07 +0200 Message-Id: <20210428170410.479308-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 9 +-- target/mips/cpu.c | 103 --------------------------- target/mips/sysemu/cp0.c | 123 +++++++++++++++++++++++++++++++++ target/mips/sysemu/meson.build | 1 + 4 files changed, 129 insertions(+), 107 deletions(-) create mode 100644 target/mips/sysemu/cp0.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 07573c3e38f..dd332b4dcef 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); + +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); + extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -405,8 +410,4 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index daa9a4791ee..1ad2fe4aa33 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -42,109 +42,6 @@ const char regnames[32][4] =3D { "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; =20 -#if !defined(CONFIG_USER_ONLY) - -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS_R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - -#endif /* !CONFIG_USER_ONLY */ - static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) { if (is_fpu64) { diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c new file mode 100644 index 00000000000..bae37f515bf --- /dev/null +++ b/target/mips/sysemu/cp0.c @@ -0,0 +1,123 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index 925ceeaa449..cefc2275828 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'addr.c', + 'cp0.c', 'cp0_timer.c', 'machine.c', 'physaddr.c', --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629624; cv=none; d=zohomail.com; s=zohoarc; b=VJLVp4ZV5iVanv6XsMral8hrUix7YPA1EO71Yz+G8Ptn+3kUmJCCCVgujwdagcPDg2GBuErfKTj7JKoigUS4MIGAucSDaYJir4wtj20KmZ2fXiUakEI7/LKXVG6WosF1W3lQmZvcItjIu/olppq70EPeVfSOi3ytoQSFUZV1LTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629624; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gr9GSZLN2Z3Rv6FaBMCzoy4GAGj9QQFeN+MV0y3f2mo=; b=m0X+viGaj/3NCVLugSi1tEACxwznyh9WKzwf9RVg3S0m6u+a9uudBlyHGWxbkLY4tEgK14M6qAgRlvJTytpHaBY/FxzOJYXEUY2I2c23NnIXZNI3kvxkza2M2MOXvfrIsss/wso+I0ORHxg5/66k0R6rIj684UazqZTzRCX0yVY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619629624574350.8910069032727; Wed, 28 Apr 2021 10:07:04 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id k14so13912618wrv.5 for ; Wed, 28 Apr 2021 10:07:03 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id f11sm7351858wmc.6.2021.04.28.10.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:07:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gr9GSZLN2Z3Rv6FaBMCzoy4GAGj9QQFeN+MV0y3f2mo=; b=fu5RK9xg6fb6QuIsp/bLoRF+3HXRyryxGk2AVBGu3mHt1Dd/cJvN0LKw8ANZA19iKz fC/2sHwk2rhD3TjgtE6A8M1VTqXpUwmagKMJQARLXknVIl/PM7M3Pwddfa5lQ53LKnCm 6zFibQ41VUGNj6HKefwxP5N9INx/bLt1er2pSgLkPTn7h1Qxh2clXZ/wQDmbYFrD8v/4 9gxdNaM7nfplkZj4ctLzdPKxybz7NsaKvgsefxL9lZ5hlF6Sd5XSEN7jY2QTpuHW60r2 Op9D5bKiz3KvLnhkxMRABdYqTYG5Rp6NBCWDCxXfAN6tXT9tezDH+5AeR4NoG6ZgKyuj 8dZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gr9GSZLN2Z3Rv6FaBMCzoy4GAGj9QQFeN+MV0y3f2mo=; b=CV3BRFppRazvh1nx8tDNfuV0EeKHIc3LdbYTLSiD+HumXfhbhKqi+7oWZNsvkFuXnO Rwdyn0SrYlo8EMvz+V9Ja6RuRL/rN3KTAqJX/xUtByKLe61ix+OOkcxWajB2etc5TEST Q5rNuz6bVfty1JycGMzoYNT/awXfstCvZGQV112j1r2oN/LdqAsB7fKK5pfVzOp0v08q pifsC4zxqmMPyB8bpoooPGeMjYsPyk0f9vKA9r83qcxyfA8edrsymGYjrOQpMxz1bEpS LJ05hed20iayLkDFB1nDmoL8fz5Ix2oE2jNGW7O4Eg12EsyDSxFooHFTZuPMq6ShxlwU AgbA== X-Gm-Message-State: AOAM531WnxUjlRATa5sKTnzdCFYe3EIHtdnMimWeXzaBVS8Iu89BlkNK ekmr6g0XW0cYDiYazCv195g= X-Google-Smtp-Source: ABdhPJyQpT9wzq0QssRq77/wd7IQjU3D/yT2w0NxTPCPl9hmlxpEdXGuZmYWMcFzt19SXwoDxVygnA== X-Received: by 2002:adf:efca:: with SMTP id i10mr37032536wrp.316.1619629622395; Wed, 28 Apr 2021 10:07:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 28/30] target/mips: Move TCG source files under tcg/ sub directory Date: Wed, 28 Apr 2021 19:04:08 +0200 Message-Id: <20210428170410.479308-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/helper.h | 2 +- target/mips/internal.h | 11 ------- target/mips/tcg/tcg-internal.h | 11 +++++++ target/mips/{ =3D> tcg}/msa_helper.h.inc | 0 target/mips/{ =3D> tcg}/mips32r6.decode | 0 target/mips/{ =3D> tcg}/mips64r6.decode | 0 target/mips/{ =3D> tcg}/msa32.decode | 0 target/mips/{ =3D> tcg}/msa64.decode | 0 target/mips/{ =3D> tcg}/tx79.decode | 0 target/mips/{ =3D> tcg}/dsp_helper.c | 0 target/mips/{ =3D> tcg}/exception.c | 0 target/mips/{ =3D> tcg}/fpu_helper.c | 0 target/mips/{ =3D> tcg}/ldst_helper.c | 0 target/mips/{ =3D> tcg}/lmmi_helper.c | 0 target/mips/{ =3D> tcg}/msa_helper.c | 0 target/mips/{ =3D> tcg}/msa_translate.c | 0 target/mips/{ =3D> tcg}/mxu_translate.c | 0 target/mips/{ =3D> tcg}/op_helper.c | 0 target/mips/{ =3D> tcg}/rel6_translate.c | 0 target/mips/{ =3D> tcg}/translate.c | 0 target/mips/{ =3D> tcg}/translate_addr_const.c | 0 target/mips/{ =3D> tcg}/tx79_translate.c | 0 target/mips/{ =3D> tcg}/txx9_translate.c | 0 target/mips/meson.build | 31 -------------------- target/mips/tcg/meson.build | 29 ++++++++++++++++++ 25 files changed, 41 insertions(+), 43 deletions(-) rename target/mips/{ =3D> tcg}/msa_helper.h.inc (100%) rename target/mips/{ =3D> tcg}/mips32r6.decode (100%) rename target/mips/{ =3D> tcg}/mips64r6.decode (100%) rename target/mips/{ =3D> tcg}/msa32.decode (100%) rename target/mips/{ =3D> tcg}/msa64.decode (100%) rename target/mips/{ =3D> tcg}/tx79.decode (100%) rename target/mips/{ =3D> tcg}/dsp_helper.c (100%) rename target/mips/{ =3D> tcg}/exception.c (100%) rename target/mips/{ =3D> tcg}/fpu_helper.c (100%) rename target/mips/{ =3D> tcg}/ldst_helper.c (100%) rename target/mips/{ =3D> tcg}/lmmi_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_translate.c (100%) rename target/mips/{ =3D> tcg}/mxu_translate.c (100%) rename target/mips/{ =3D> tcg}/op_helper.c (100%) rename target/mips/{ =3D> tcg}/rel6_translate.c (100%) rename target/mips/{ =3D> tcg}/translate.c (100%) rename target/mips/{ =3D> tcg}/translate_addr_const.c (100%) rename target/mips/{ =3D> tcg}/tx79_translate.c (100%) rename target/mips/{ =3D> tcg}/txx9_translate.c (100%) diff --git a/target/mips/helper.h b/target/mips/helper.h index ba301ae160d..a9c6c7d1a31 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ =20 -#include "msa_helper.h.inc" +#include "tcg/msa_helper.h.inc" diff --git a/target/mips/internal.h b/target/mips/internal.h index dd332b4dcef..18d5da64a57 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,9 +82,6 @@ extern const int mips_defs_number; =20 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) @@ -151,12 +148,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retadd= r); - void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) return r; } =20 -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); =20 /* cp0_timer.c */ diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 75aa3ef98ed..81b14eb219e 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,15 +11,21 @@ #define MIPS_TCG_INTERNAL_H =20 #include "tcg/tcg.h" +#include "exec/memattrs.h" #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_tcg_init(void); + void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 @@ -46,6 +52,11 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const= TranslationBlock *tb); =20 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc similarity index 100% rename from target/mips/msa_helper.h.inc rename to target/mips/tcg/msa_helper.h.inc diff --git a/target/mips/mips32r6.decode b/target/mips/tcg/mips32r6.decode similarity index 100% rename from target/mips/mips32r6.decode rename to target/mips/tcg/mips32r6.decode diff --git a/target/mips/mips64r6.decode b/target/mips/tcg/mips64r6.decode similarity index 100% rename from target/mips/mips64r6.decode rename to target/mips/tcg/mips64r6.decode diff --git a/target/mips/msa32.decode b/target/mips/tcg/msa32.decode similarity index 100% rename from target/mips/msa32.decode rename to target/mips/tcg/msa32.decode diff --git a/target/mips/msa64.decode b/target/mips/tcg/msa64.decode similarity index 100% rename from target/mips/msa64.decode rename to target/mips/tcg/msa64.decode diff --git a/target/mips/tx79.decode b/target/mips/tcg/tx79.decode similarity index 100% rename from target/mips/tx79.decode rename to target/mips/tcg/tx79.decode diff --git a/target/mips/dsp_helper.c b/target/mips/tcg/dsp_helper.c similarity index 100% rename from target/mips/dsp_helper.c rename to target/mips/tcg/dsp_helper.c diff --git a/target/mips/exception.c b/target/mips/tcg/exception.c similarity index 100% rename from target/mips/exception.c rename to target/mips/tcg/exception.c diff --git a/target/mips/fpu_helper.c b/target/mips/tcg/fpu_helper.c similarity index 100% rename from target/mips/fpu_helper.c rename to target/mips/tcg/fpu_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/tcg/ldst_helper.c similarity index 100% rename from target/mips/ldst_helper.c rename to target/mips/tcg/ldst_helper.c diff --git a/target/mips/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c similarity index 100% rename from target/mips/lmmi_helper.c rename to target/mips/tcg/lmmi_helper.c diff --git a/target/mips/msa_helper.c b/target/mips/tcg/msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/tcg/msa_helper.c diff --git a/target/mips/msa_translate.c b/target/mips/tcg/msa_translate.c similarity index 100% rename from target/mips/msa_translate.c rename to target/mips/tcg/msa_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/tcg/mxu_translate.c similarity index 100% rename from target/mips/mxu_translate.c rename to target/mips/tcg/mxu_translate.c diff --git a/target/mips/op_helper.c b/target/mips/tcg/op_helper.c similarity index 100% rename from target/mips/op_helper.c rename to target/mips/tcg/op_helper.c diff --git a/target/mips/rel6_translate.c b/target/mips/tcg/rel6_translate.c similarity index 100% rename from target/mips/rel6_translate.c rename to target/mips/tcg/rel6_translate.c diff --git a/target/mips/translate.c b/target/mips/tcg/translate.c similarity index 100% rename from target/mips/translate.c rename to target/mips/tcg/translate.c diff --git a/target/mips/translate_addr_const.c b/target/mips/tcg/translate= _addr_const.c similarity index 100% rename from target/mips/translate_addr_const.c rename to target/mips/tcg/translate_addr_const.c diff --git a/target/mips/tx79_translate.c b/target/mips/tcg/tx79_translate.c similarity index 100% rename from target/mips/tx79_translate.c rename to target/mips/tcg/tx79_translate.c diff --git a/target/mips/txx9_translate.c b/target/mips/tcg/txx9_translate.c similarity index 100% rename from target/mips/txx9_translate.c rename to target/mips/tcg/txx9_translate.c diff --git a/target/mips/meson.build b/target/mips/meson.build index e08077bfc18..2407a05d4c0 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,11 +1,3 @@ -gen =3D [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), - decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), -] - mips_user_ss =3D ss.source_set() mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() @@ -20,35 +12,12 @@ subdir('sysemu') endif =20 -mips_tcg_ss =3D ss.source_set() -mips_tcg_ss.add(gen) -mips_tcg_ss.add(files( - 'dsp_helper.c', - 'exception.c', - 'fpu_helper.c', - 'ldst_helper.c', - 'lmmi_helper.c', - 'msa_helper.c', - 'msa_translate.c', - 'op_helper.c', - 'rel6_translate.c', - 'translate.c', - 'translate_addr_const.c', - 'txx9_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( - 'tx79_translate.c', -), if_false: files( - 'mxu_translate.c', -)) if 'CONFIG_TCG' in config_all subdir('tcg') endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) - target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 2cffc5a5ac6..5d8acbaf0d3 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,32 @@ +gen =3D [ + decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), + decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), + decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), + decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), +] + +mips_ss.add(gen) +mips_ss.add(files( + 'dsp_helper.c', + 'exception.c', + 'fpu_helper.c', + 'ldst_helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'msa_translate.c', + 'op_helper.c', + 'rel6_translate.c', + 'translate.c', + 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: 'TARGET_MIPS64', if_true: files( + 'tx79_translate.c', +), if_false: files( + 'mxu_translate.c', +)) + if have_user subdir('user') endif --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629629; cv=none; d=zohomail.com; s=zohoarc; b=eyANvd8VBJM8WX1ot+1dS8vOfxl8RMZr6Cy8S7KEcQ2c+N2uDtsHVIqNiEhuboVt1v3Bfa4SS1gUQjGg1HBiPCiNfbqy6X/c7Wh3eeBo4Vlusx8jefJl5Wwcano5OHUcl2E60tkkwQE0UlG3ZHyaZibPWeE9yxqKPWC745HpHeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629629; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=JothWCnJZWm9XG30h8tr909T3iyjIuWA1PJ1NOGOxnVgCwSSH1sdJhAptqQWeIuQe/FiN/i46amJ3AcmWW9KqtGMg2wjGlSLtX3zmg1t6AON/5OS5WxS0v54U4F6Oag3Vi8p8hvt7gfG4Nx4J/VT8W/hSxVMiS8MMB3gZeLKwks= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.zohomail.com with SMTPS id 1619629629386268.8034890062074; Wed, 28 Apr 2021 10:07:09 -0700 (PDT) Received: by mail-wm1-f41.google.com with SMTP id i129so7275728wma.3 for ; Wed, 28 Apr 2021 10:07:08 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id z7sm482903wrl.11.2021.04.28.10.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:07:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=ArylLzrIM9lnlqIstH7+c8mUL6VJY0VjX8GiWI63FADxS66pFMLVCMHrwBt8FVdqg+ Yk2f35MRzky9eBekfLwZlHRiy0WUJ4rpLObTvW80LlgfVXmoDMWuXzwVHjCUKRFixt4r On589R5hoH2rI5XeZ7uBbQ3B5TmbNluHV+8UxaiVyn1QioABw+v8CXlNzhxz3aW32cf4 Qbfai0ZAYWjdFy4gJzEkKiS8jf9M4CxtZ5773Kc1V8PszBpJ9suyTXrw/Pi4CoGp1ttT oxAmnmoKPl6pWcrPToDiy3md5kpx7aQqkLjYldO4uJ6T5i1Gbl9FF1kBt1Xm1myd+oJM pIUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=oEwKjogwzqew9LHnVJfSpLxM+9Yj6ci2FrJpneJ2XN0=; b=RxINZHEc788x2AyyBidFAe+JI0cnedsBPx2iW6vbBZlZc7Zfa+CLULP+C+nBzwG/v8 BZXuyE/zWimwZEXm8RdqPwypfRTLb0NUkIjXQoYK4e0nNXJlRHEW9yIULyKvaQ7TfXYa WRG5mkE7jK23PY/HY4vycrQZtIsT4WbHF1mejpEGCruMGIFL/1UVHXgc6HobqAhbiteJ 8TIc/HFGd3geTWidMly6uI7b3/LX4UsBm4CCgnm6JL7RSFZLUKbMkdkVs5fIdYWPWbci RisGrzwQXbvwwUd3mLeH5eYDRQdnIomz/9gIRxLBCR6lOQ47XRkl5tvCHFO+0jF4kQOX 3BMw== X-Gm-Message-State: AOAM530lb0ERCGj0eVS+K/Fh6Q0FF5GM25quRSXGeIwwBkdyNopZgfs6 G3JNeaJ6+ueMwG089dBwg9Y= X-Google-Smtp-Source: ABdhPJzzD8OR34I7i2Uj1kDqt/Llg83loh4vTNVDLOESYtDSEEF07aD7t8vlyLLgD1yIk0e2FP2Cdw== X-Received: by 2002:a1c:750b:: with SMTP id o11mr5761258wmc.188.1619629627086; Wed, 28 Apr 2021 10:07:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v4 29/30] hw/mips: Restrict non-virtualized machines to TCG Date: Wed, 28 Apr 2021 19:04:09 +0200 Message-Id: <20210428170410.479308-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only the malta and loongson3-virt machines support KVM. Restrict the other machines to TCG: - mipssim - magnum - pica61 - fuloong2e - boston Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 1195716dc73..dd0101ad4d8 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,12 +1,15 @@ mips_ss =3D ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) -mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c',= 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c= ')) -mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) -mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) =20 +if 'CONFIG_TCG' in config_all +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) +mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) +mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) +endif + hw_arch +=3D {'mips': mips_ss} --=20 2.26.3 From nobody Fri Apr 26 21:15:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619629639; cv=none; d=zohomail.com; s=zohoarc; b=KRBYeSkP7R7ThiVJ1y3mwRq4sPeXEj699Hgowh8cDlsRkPi8CQz5AD9DuglUkq7xE7BwNuj5HHGWw1lxFL40v4AeXapNHb8yg7kIULRXLVUrgK1wzDyyIjW3zwDophQob5Vq7+vHKqX2T9UqccscHSuhhrFpXZiKbKJ1UFNKGqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619629639; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hAxtd3FVfWCgth1vFkPSMi25H2dRcEPTe7zUFtCCWjA=; b=B7ljB/9AtuJDU6oA9aC8hYIaOa3RbwQGFrYEgXFWiuWVSbO+2SL934YqOjyU2tIp7u8C07eheDmzvV5MKfDaQdlczkfFwc1qjIQqLFzzLEGcBtbc2I5cUCd+xBbGiE3IGKaR78A56FMBgLBFbBz2aKVyHk07oatYK92eYTasQyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1619629639168228.3006741977979; Wed, 28 Apr 2021 10:07:19 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id x7so63800628wrw.10 for ; Wed, 28 Apr 2021 10:07:18 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id p10sm438233wrr.58.2021.04.28.10.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 10:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hAxtd3FVfWCgth1vFkPSMi25H2dRcEPTe7zUFtCCWjA=; b=CnkQ2Op8ogWF5y1SwU+LaQktzNys7YUqKNNyFydopx23A8Ty7f6LFhgZanDzfgFgV9 KCuHyGzcmj1+J+sY4XHGGYM1VoCCc+LKqyzKg5rr5xrirPAAmvOZ2iF0wthfNglw/4Q6 52V3KiL/tWIZiqMe5Ngbmn8J13iJGiHLtkTQVml93V19CmKBLaLT8ZRhtEkP9RfO00IO UPlLWuSw1CcL75wCCIGvszrcMOIyqkjGjC6Xi6FZoP2gAsVr9CzEsT50M01pPJyAppoe GCAs035gfBOoEmCRo8/5C82udNq5293wfEwetsKnKDH/IOe6TANwAB/Z3YF62dMapUQh omBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=hAxtd3FVfWCgth1vFkPSMi25H2dRcEPTe7zUFtCCWjA=; b=hfyMaVgwYVYXFs/qa3qC6nXyDz57e2ZiDPwRjcU1QXbFw2izcIdHbkS7lrN6kd1Av7 Q6pLgm0tCG1YstiE058Wh47y6PwukWLy2QJaWDGXAg9idEidqpRPXy3meGnZnrWEdRVR 8JWgEKKiuIG2Vv9tVf1fKshIA3utGFjnegl7qx3x9qo3rTWChUJmbmblU/mwiEtyIg4q 0+F9pd8O8+VUyh9C5p7FVtABllViI58klhNBStMOysDNt21gZAdZ3CECZYhTEjLgkgIm cOZkP1+1KuMvSjHHrLTVh1ntMr+AFCrffGBtQO/EseZFc+pDT483GfK1EGB6LJ+pPcBD XAJg== X-Gm-Message-State: AOAM531jDk2mD+XvIdCfTDxjboZbg2WrAqFHq5EcrLR8xu3O+lryzJjS qJ9J+w8aan09di8pgve9NZs= X-Google-Smtp-Source: ABdhPJw/lQxgIIG9D+U7YFLeRLILz+qlin6PANt55ffntMy9grNhHiYfN5E9PtJyJfLDH47whEoDwQ== X-Received: by 2002:a5d:6787:: with SMTP id v7mr29038579wru.386.1619629637005; Wed, 28 Apr 2021 10:07:17 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Thomas Huth , Willian Rampazzo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Wainer dos Santos Moschetta Subject: [PATCH v4 30/30] gitlab-ci: Add KVM mips64el cross-build jobs Date: Wed, 28 Apr 2021 19:04:10 +0200 Message-Id: <20210428170410.479308-31-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428170410.479308-1-f4bug@amsat.org> References: <20210428170410.479308-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add a new job to cross-build the mips64el target without the TCG accelerator (IOW: only KVM accelerator enabled). Only build the mips64el target which is known to work and has users. Reviewed-by: Richard Henderson Acked-by: Thomas Huth Reviewed-by: Willian Rampazzo Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 2d95784ed51..e44e4b49a25 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -176,6 +176,14 @@ cross-s390x-kvm-only: IMAGE: debian-s390x-cross ACCEL_CONFIGURE_OPTS: --disable-tcg =20 +cross-mips64el-kvm-only: + extends: .cross_accel_build_job + needs: + job: mips64el-debian-cross-container + variables: + IMAGE: debian-mips64el-cross + ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=3Dmips64el-softmmu + cross-win32-system: extends: .cross_system_build_job needs: --=20 2.26.3