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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id b15sm111735wrt.57.2021.04.28.07.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 07:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VXwJMgfTCzcmDZmdzUQlG/w+wYVj2e6Bgl1h2XHKQyk=; b=gWJd0NojUE6Ff/prtcHoxbqdHF6AMpDDPs+pZp2yHmuGrgRAZOhYOrBP0toC+FOzlQ KE5VSP5N9yOawhXBipyitM3vd3qTUCVJnKbYX3ZaWosA+KpZuifPiEyhvAbDQMFibfin n4L2shCRDK13xn+dXMvZL1e/wrRjGhv8LqBe+SQuajRsQyAs7V/P6Qn6bfx9RI+EI9Mj ZUTGmNZkUK91HyYpH3VP5zfO2OVIuUAsW0PK4upcJeKtL8xqkbncmBeqbPejYnh8Hbjo FJRxaPmFrgyMdtw9Ubf6xDzB9hGkllo6ZKr904Mn64/GPpEU67Otr1MU9b2BwoQOVxQ/ uEIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VXwJMgfTCzcmDZmdzUQlG/w+wYVj2e6Bgl1h2XHKQyk=; b=cMaBsfPN3Ug6cLkBUUhFqlIJKCCzQNiIEbmu8SmlXD+Gj7Me8HTBvg+6WHmzRVlZLv g7VxL+9BAU91qcV1/Xe7p5/gyUPyLqz5Ijkh4QEby9dB5qTWiL3jclWyIsF0VT8doWex IzBXzAeH2ClczCXCeLzZxZKL4gK6n89YN0+GvwmvaBrIecDtat3MkfK/LA6Hc3UEu6ca SlBy+/yMbdH3zRGtSCYXF345mpXsk4g07nyrr9beNglnSgRFQvuPiLcm2QaLTb3OgR/i +n7qSQ4pLMohnmlpfI4pYvwPAXWv5SQb++BaYVZGhmQDafbPkPIrXMbaZZMiruktezQr H7GQ== X-Gm-Message-State: AOAM532oRCAVWCSeMSe/A5z6t4nN4tsvCmpQCa7aUk9+pMV6o3l6vme1 2DPV1igbzvDeHAj1LZmsUBI= X-Google-Smtp-Source: ABdhPJyYla6o1vno5mXOdK79LrCSlzpfU+4DIsTEnz8X4OVWrD601kjIZXjd4vWOSZTT1mBQCxZqHg== X-Received: by 2002:adf:f6c5:: with SMTP id y5mr37210090wrp.121.1619619427511; Wed, 28 Apr 2021 07:17:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: KONRAD Frederic , Mark Cave-Ayland , Richard Henderson , Fabien Chouteau , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/4] hw/sparc: Allow building without the leon3 machine Date: Wed, 28 Apr 2021 16:16:51 +0200 Message-Id: <20210428141655.387430-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428141655.387430-1-f4bug@amsat.org> References: <20210428141655.387430-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) When building without the leon3 machine, we get this link failure: /usr/bin/ld: target_sparc_int32_helper.c.o: in function `leon3_irq_manage= r': target/sparc/int32_helper.c:172: undefined reference to `leon3_irq_ack' This is because the leon3_irq_ack() is declared in hw/sparc/leon3.c, which is only build when CONFIG_LEON3 is selected. Fix by moving the leon3_cache_control_int() / leon3_irq_manager() (which are specific to the leon3 machine) to hw/sparc/leon3.c. Move the trace events along (but don't rename them). leon3_irq_ack() is now locally used, declare it static to reduce its scope. Reviewed-by: Richard Henderson Reviewed-by: KONRAD Frederic Tested-by: KONRAD Frederic Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu.h | 6 ------ hw/sparc/leon3.c | 37 ++++++++++++++++++++++++++++++++++++- target/sparc/int32_helper.c | 37 ------------------------------------- hw/sparc/trace-events | 2 ++ target/sparc/trace-events | 4 ---- 5 files changed, 38 insertions(+), 48 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4b2290650be..ff8ae73002a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp); int cpu_cwp_dec(CPUSPARCState *env1, int cwp); void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); =20 -/* int_helper.c */ -void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); - /* sun4m.c, sun4u.c */ void cpu_check_irqs(CPUSPARCState *env); =20 -/* leon3.c */ -void leon3_irq_ack(void *irq_manager, int intno); - #if defined (TARGET_SPARC64) =20 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7e16eea9e67..98e3789cf84 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -137,7 +137,36 @@ static void main_cpu_reset(void *opaque) env->regbase[6] =3D s->sp; } =20 -void leon3_irq_ack(void *irq_manager, int intno) +static void leon3_cache_control_int(CPUSPARCState *env) +{ + uint32_t state =3D 0; + + if (env->cache_control & CACHE_CTRL_IF) { + /* Instruction cache state */ + state =3D env->cache_control & CACHE_STATE_MASK; + if (state =3D=3D CACHE_ENABLED) { + state =3D CACHE_FROZEN; + trace_int_helper_icache_freeze(); + } + + env->cache_control &=3D ~CACHE_STATE_MASK; + env->cache_control |=3D state; + } + + if (env->cache_control & CACHE_CTRL_DF) { + /* Data cache state */ + state =3D (env->cache_control >> 2) & CACHE_STATE_MASK; + if (state =3D=3D CACHE_ENABLED) { + state =3D CACHE_FROZEN; + trace_int_helper_dcache_freeze(); + } + + env->cache_control &=3D ~(CACHE_STATE_MASK << 2); + env->cache_control |=3D (state << 2); + } +} + +static void leon3_irq_ack(void *irq_manager, int intno) { grlib_irqmp_ack((DeviceState *)irq_manager, intno); } @@ -181,6 +210,12 @@ static void leon3_set_pil_in(void *opaque, int n, int = level) } } =20 +static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int i= ntno) +{ + leon3_irq_ack(irq_manager, intno); + leon3_cache_control_int(env); +} + static void leon3_generic_hw_init(MachineState *machine) { ram_addr_t ram_size =3D machine->ram_size; diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 817a463a179..d008dbdb65c 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -136,40 +136,3 @@ void sparc_cpu_do_interrupt(CPUState *cs) } #endif } - -#if !defined(CONFIG_USER_ONLY) -static void leon3_cache_control_int(CPUSPARCState *env) -{ - uint32_t state =3D 0; - - if (env->cache_control & CACHE_CTRL_IF) { - /* Instruction cache state */ - state =3D env->cache_control & CACHE_STATE_MASK; - if (state =3D=3D CACHE_ENABLED) { - state =3D CACHE_FROZEN; - trace_int_helper_icache_freeze(); - } - - env->cache_control &=3D ~CACHE_STATE_MASK; - env->cache_control |=3D state; - } - - if (env->cache_control & CACHE_CTRL_DF) { - /* Data cache state */ - state =3D (env->cache_control >> 2) & CACHE_STATE_MASK; - if (state =3D=3D CACHE_ENABLED) { - state =3D CACHE_FROZEN; - trace_int_helper_dcache_freeze(); - } - - env->cache_control &=3D ~(CACHE_STATE_MASK << 2); - env->cache_control |=3D (state << 2); - } -} - -void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) -{ - leon3_irq_ack(irq_manager, intno); - leon3_cache_control_int(env); -} -#endif diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index 355b07ae057..dfb53dc1a24 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -19,3 +19,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 # leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d" leon3_reset_irq(int intno) "Reset CPU IRQ %d" +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" diff --git a/target/sparc/trace-events b/target/sparc/trace-events index 6a064e23275..e925ddd1cc0 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -15,10 +15,6 @@ int_helper_set_softint(uint32_t softint) "new 0x%08x" int_helper_clear_softint(uint32_t softint) "new 0x%08x" int_helper_write_softint(uint32_t softint) "new 0x%08x" =20 -# int32_helper.c -int_helper_icache_freeze(void) "Instruction cache: freeze" -int_helper_dcache_freeze(void) "Data cache: freeze" - # win_helper.c win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active ps= tate bits=3D0x%x" win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "= change_pstate: switching regs old=3D0x%x new=3D0x%x" --=20 2.26.3 From nobody Fri May 17 21:37:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id l21sm7942942wme.10.2021.04.28.07.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 07:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bIBz+cc+PVq4jBndEUgHGuyOnipUh6TZscrO0OVvRs8=; b=mjjJNynvyp4y92hztoB939rY+Zho2Man4waOTdBnwiUNSlcd8V+Jl9UvPwe1KUwSwy 8drjHEKRX4x3bi3pAlrteZQbdG9EWsTiqwoIUzg4iy9JiUpAZolflTpu0dHyK1HPBNy0 NIxyV8i9rJj+ZNREeBXC+7bz3U0Ag4a7cgP4KPxPod1VcbYZW+pntmJgqzR7jIloyBEW N2ySWqyHGjevwIHP9Yt1J7VcqYx3pU9GdH3r6MqxWdknNjdH136mn+iQt6dW3iclf4rz tkfI4v4FqZPvp2owjFFYLcD1O/Lt09Gk7Bqh5x0+XyDVOP4x5sRSQOV9xxNemE+vHrKM qPpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=bIBz+cc+PVq4jBndEUgHGuyOnipUh6TZscrO0OVvRs8=; b=O6nbErqSIIGxAR7RBmSAdWRffh1htYSQVDprqBJluzSeqpwKS1D/fKZspbGb3xCQly xWkBOJH3dq5yKUCz6vagiBcWAFJvnloainiMWw3XvC65omCi8QQtKZhDqwsLenXKzVvb 6Qw7uhR1k6JtxLsbchSKah6YmvjapLLBMGzBj98izx0W3iTud4FVOjGZJyYP4XMxjbFj Jjm1FHQ07KaXSHRflkQwPQWBi39/wXSGK2R2GWeluySeEDF9ejb6sfVB9DJzAFdvZkd7 fMcVt2QSKRI2ohKJz03v1Hpn6zJZnnIFNVC8TLrTnfJSzG3kd0KtvRb6blLr6W983HKE FSmA== X-Gm-Message-State: AOAM533s252TzByd3O05UmhgAVvD6VenQyOZguEoi7S6XgEXMn8iq3Ik Jy+mCfyEvBKy1WEFS8LKKO0= X-Google-Smtp-Source: ABdhPJwv15OUsqzhdM/CaGq/yCrI9WDUt+XqwQgIo71iZXSKd4h5UYjGniUYMA3A3IH0JsZi5QlGPw== X-Received: by 2002:a7b:c444:: with SMTP id l4mr31727210wmi.36.1619619432120; Wed, 28 Apr 2021 07:17:12 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: KONRAD Frederic , Mark Cave-Ayland , Richard Henderson , Fabien Chouteau , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header Date: Wed, 28 Apr 2021 16:16:52 +0200 Message-Id: <20210428141655.387430-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428141655.387430-1-f4bug@amsat.org> References: <20210428141655.387430-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: KONRAD Frederic Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- hw/sparc64/sparc64.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index e3f9219a101..cc0b9bd30d3 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "hw/boards.h" -#include "hw/char/serial.h" #include "hw/sparc/sparc64.h" #include "qemu/timer.h" #include "sysemu/reset.h" --=20 2.26.3 From nobody Fri May 17 21:37:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619619438; cv=none; d=zohomail.com; s=zohoarc; b=Gga7ZjAlBpEjtQfpuMfQELBT3fI7fiHUY5rEd7mJyGoERmNUaWPUSG51LuMzl7/ON7mUpkj/N/s/9mufgIMg3yorHSK3/wxiggY++DjEEAU6pJdgj3bdvqDuNXJ4EzrdmxV6iEq91ly6vU0eYBG22YorK/dCEj9LdEgtzojwgOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619619438; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h/nIb3IjINN2mrXWPh2f9m2AgY9HURbh9xQILDV1MKc=; b=GY8bo+qEbJx4gvEytW4kGZDEdWMvJVzn4u2n09L3IKbC8AFNhhj3OC56HCZXuSEONyQCfLFG2wk+OaUnZ+D1LK+Gp1Kw12RZmYq3YCzGp1+lzkDcQXTM6g3bPLkqaSVdBxkNcqtGjX2O1wwXqWdTflz/Z1uJ/4KJV/fKjtgTrPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1619619438882701.3799885030769; Wed, 28 Apr 2021 07:17:18 -0700 (PDT) Received: by mail-wm1-f43.google.com with SMTP id y124-20020a1c32820000b029010c93864955so9359607wmy.5 for ; Wed, 28 Apr 2021 07:17:17 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id o1sm77653wrw.95.2021.04.28.07.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 07:17:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h/nIb3IjINN2mrXWPh2f9m2AgY9HURbh9xQILDV1MKc=; b=fVt5zTNthBSgsTxrPQbo8i145acibOlMaQYVHhsyK/6Dhm/L+2GU7peHW6pRC1x2Kv PCMma2NuNDxweIZAxVYO5BbBLgbHYiA3la6zYv/2fMjCOl9oRoNCqwKRBH8D0q+MNnqi r6II8WmgvOqVsIhWHIKljhzM8h59G6ooxIpkk/Pwk0xwANmrKQq6QC/sWHDoN+LaYrtU mQD7a+g1ergUeosFGSKfjHAUtCPOJif+GMdb99VJFierj5/w430veapYO388JR2PZybs FZ51igxbYxNMKoy1NC+Y1xlxlt4ZUTsLPVWy0BGK/zINWD//X6tJaovFOoFUPFjpeIk9 K6gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=h/nIb3IjINN2mrXWPh2f9m2AgY9HURbh9xQILDV1MKc=; b=Ew7gSfgs2ptTu6KTKv/je/mtdT4b96vJBmU5xW57f2tRsskJyJcnya/pG+/vlqWDv1 aAykn4WWdlHeTpOvqmKyr10lK3g0BCYGm3DeXrg/Eeyp/GacBNCILSPGkJrks39uomMZ I6od95uWdk0HBtuF6a5s90784Sque1WxcJWUSuTCooUPhpyisIDkFEEaFiSHcQoUcwqk exJyGivLkfFyfA8YpkU09+tDJET55hQJygkH6ZFDuQVCYEwU/JNQVK93RKCCQPHLdba8 onYYK+5VTVQ/xDQt3JWLPF8xPOkwtWhiK9cT/QAqrAYIVGolwUZfylT7FTvkzwuwIUvz TFGg== X-Gm-Message-State: AOAM530mPvgJBoOU2g3Cg3oQgE3cSWieRWBgHEeHq9OdGCHfGQaxQez9 HHgcX6DT4w1t+8TuqnTfHpY= X-Google-Smtp-Source: ABdhPJy8+CnENi0qNMz/AzxpDjlAWCBgHyPSrk+5kHj90ygYGU1+MUGbf6AuTR5DqD5JuBLsynrbzQ== X-Received: by 2002:a05:600c:2315:: with SMTP id 21mr15898745wmo.39.1619619436738; Wed, 28 Apr 2021 07:17:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: KONRAD Frederic , Mark Cave-Ayland , Richard Henderson , Fabien Chouteau , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl Date: Wed, 28 Apr 2021 16:16:53 +0200 Message-Id: <20210428141655.387430-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428141655.387430-1-f4bug@amsat.org> References: <20210428141655.387430-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: KONRAD Frederic Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- hw/sparc64/sparc64.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index cc0b9bd30d3..fd29a79edc0 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env) return; } cs =3D env_cpu(env); - /* check if TM or SM in SOFTINT are set - setting these also causes interrupt 14 */ + /* + * check if TM or SM in SOFTINT are set + * setting these also causes interrupt 14 + */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { pil |=3D 1 << 14; } =20 - /* The bit corresponding to psrpil is (1<< psrpil), the next bit - is (2 << psrpil). */ + /* + * The bit corresponding to psrpil is (1<< psrpil), + * the next bit is (2 << psrpil). + */ if (pil < (2 << env->psrpil)) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); --=20 2.26.3 From nobody Fri May 17 21:37:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619619443; cv=none; d=zohomail.com; s=zohoarc; b=eNv1vLrQ5NR4KrRQjAFO1ep9M3PMlOBasCPMkbC0DY4756xCkCCDEyQkq+Ul9BxBE/aEIrJnZo75mfz/Z29lZWGWycQvZFyit50K+G6nBSGzQkbtdtCYCvPa4hZeZBmQOueDpWHOUXvfszLhwjTswckwMIR8QJA6x2MQ3mkgQtE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619619443; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vqgsjuSJIEYWEWPcK57p29/yxcMDDnB0zu7h3NrXs3Q=; b=CR7aSc3e4zRt8TjoQ8sqUZcOb4o5tXk4CkqlTbUYpnyWwon48XugxPngb/9phWo4YHHK3bg3yVGCBuMVSdeaj0S9MjRcVoUfMNStOvE2HWITv+kVfrVrUbti7yshGfazVdZcPpqy13JMBogu303dln8qjI9YAMQKGp195NKpuUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 1619619443715259.30004752114917; Wed, 28 Apr 2021 07:17:23 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id k14so13329589wrv.5 for ; Wed, 28 Apr 2021 07:17:22 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id t2sm7173937wmg.38.2021.04.28.07.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 07:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vqgsjuSJIEYWEWPcK57p29/yxcMDDnB0zu7h3NrXs3Q=; b=BPEMT3MiKpfuPMo2uXoi7FoRdwiMPc3cn1IuuY17qGelAYAcjcdvOM8qJyqP/tPXgD 9yFIw0wQ5lkEoQjYWOU3X5sEUmLokitQ4o2kJAn+SbTLLajTMFA+kLEbXq5G9Meh2MX/ hePPJB8m9RD0dKRrfci9NLAACo+eqZA3DNNIOxhIiXPrjrrPdYKPAfVHRW4lAkiPV8Bq w02ipyFXM6XMykNl5U9np+2t/EvRPXQwTo0/YYUpzDzFtfX8MssefK/xaeXdmFhPJpqc Veq96647YhGRnUZdq/A5VmZO6/hdHfmsGGH6TOZMCTiteDkYd54IKT9x93XpjTkarNxc UDeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vqgsjuSJIEYWEWPcK57p29/yxcMDDnB0zu7h3NrXs3Q=; b=Jwfz0GIH5AjssGhGduNQNlCnsWRpU7p57+IKxbHg7NBrmt/gIUU9n+ocEHI+wttuJ/ tpjHtsEHeONePyKEG1k/Xt8RzA51zcpI+vWmD4Ds0s6Pw+9ruV10qQb7wbZpKmtbgS1n deZp6WBq1JFcl2+8hPAs69t7BzaWSgZrG2Yt4TGlYl/tGh9jW36pwab5kNdhjlyy9aDE W8owG6ZH/tN/4UD+36d5jmFt37C74Mo7hfQvkNoQY1cfE1KThl/p42pqPHguU+XkKhqL ozAppwew3NoHeqbpjZK7JYYUJD5XcOTVEWOySwe+fvEzLHYBfzU2CzTNFv0b2ELr5fZv vN0g== X-Gm-Message-State: AOAM531p09ib9Xr2kXLh9vh/Exw807AgWRfug/cJMyMrh90B3LiE45/b 0wWBB8phpa2i7ed8NdMJa9M= X-Google-Smtp-Source: ABdhPJw+lbQExbK/TEH7ptrEBPLMb85ggfXym4qhGFrrhKOEVFALNlS0as4KsZwa1k1+hG1KTpR66g== X-Received: by 2002:adf:d0c8:: with SMTP id z8mr36959040wrh.68.1619619441426; Wed, 28 Apr 2021 07:17:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: KONRAD Frederic , Mark Cave-Ayland , Richard Henderson , Fabien Chouteau , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/4] hw/sparc*: Move cpu_check_irqs() to target/sparc/ Date: Wed, 28 Apr 2021 16:16:54 +0200 Message-Id: <20210428141655.387430-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210428141655.387430-1-f4bug@amsat.org> References: <20210428141655.387430-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since cpu_check_irqs() doesn't reference to anything outside of CPUSPARCState, it better belongs to the architectural code in target/, rather than the hardware specific code in hw/. Note: while we moved the trace events, we don't rename them. Remark: this allows us to build the leon3 machine stand alone, fixing this link failure (because cpu_check_irqs is defined in hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected): /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr': target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs' Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- hw/sparc/sun4m.c | 32 ------------------ hw/sparc64/sparc64.c | 66 ------------------------------------- target/sparc/int32_helper.c | 33 +++++++++++++++++++ target/sparc/int64_helper.c | 66 +++++++++++++++++++++++++++++++++++++ hw/sparc/trace-events | 2 -- hw/sparc64/trace-events | 4 --- target/sparc/trace-events | 8 +++++ 7 files changed, 107 insertions(+), 104 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 1a00816d9a8..2edf913d945 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -159,38 +159,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr, } } =20 -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - if (env->pil_in && (env->interrupt_index =3D=3D 0 || - (env->interrupt_index & ~15) =3D=3D TT_EXTINT)) { - unsigned int i; - - for (i =3D 15; i > 0; i--) { - if (env->pil_in & (1 << i)) { - int old_interrupt =3D env->interrupt_index; - - env->interrupt_index =3D TT_EXTINT | i; - if (old_interrupt !=3D env->interrupt_index) { - cs =3D env_cpu(env); - trace_sun4m_cpu_interrupt(i); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { - cs =3D env_cpu(env); - trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); - env->interrupt_index =3D 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env =3D &cpu->env; diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index fd29a79edc0..8654e955eb1 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -34,72 +34,6 @@ =20 #define TICK_MAX 0x7fffffffffffffffULL =20 -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - uint32_t pil =3D env->pil_in | - (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ - if (env->ivec_status & 0x20) { - return; - } - cs =3D env_cpu(env); - /* - * check if TM or SM in SOFTINT are set - * setting these also causes interrupt 14 - */ - if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { - pil |=3D 1 << 14; - } - - /* - * The bit corresponding to psrpil is (1<< psrpil), - * the next bit is (2 << psrpil). - */ - if (pil < (2 << env->psrpil)) { - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); - env->interrupt_index =3D 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - return; - } - - if (cpu_interrupts_enabled(env)) { - - unsigned int i; - - for (i =3D 15; i > env->psrpil; i--) { - if (pil & (1 << i)) { - int old_interrupt =3D env->interrupt_index; - int new_interrupt =3D TT_EXTINT | i; - - if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_inter= rupt - && ((cpu_tsptr(env)->tt & 0x1f0) =3D=3D TT_EXTINT))) { - trace_sparc64_cpu_check_irqs_noset_irq(env->tl, - cpu_tsptr(env)->tt, - new_interrupt); - } else if (old_interrupt !=3D new_interrupt) { - env->interrupt_index =3D new_interrupt; - trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, - new_interrupt); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softi= nt, - env->interrupt_index); - env->interrupt_index =3D 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUState *cs =3D CPU(cpu); diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index d008dbdb65c..82e8418e465 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" #include "exec/log.h" @@ -64,6 +65,38 @@ static const char *excp_name_str(int32_t exception_index) return excp_names[exception_index]; } =20 +void cpu_check_irqs(CPUSPARCState *env) +{ + CPUState *cs; + + /* We should be holding the BQL before we mess with IRQs */ + g_assert(qemu_mutex_iothread_locked()); + + if (env->pil_in && (env->interrupt_index =3D=3D 0 || + (env->interrupt_index & ~15) =3D=3D TT_EXTINT)) { + unsigned int i; + + for (i =3D 15; i > 0; i--) { + if (env->pil_in & (1 << i)) { + int old_interrupt =3D env->interrupt_index; + + env->interrupt_index =3D TT_EXTINT | i; + if (old_interrupt !=3D env->interrupt_index) { + cs =3D env_cpu(env); + trace_sun4m_cpu_interrupt(i); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + } + } + } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { + cs =3D env_cpu(env); + trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); + env->interrupt_index =3D 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu =3D SPARC_CPU(cs); diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 7fb8ab211ca..793e57c536d 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -62,6 +62,72 @@ static const char * const excp_names[0x80] =3D { }; #endif =20 +void cpu_check_irqs(CPUSPARCState *env) +{ + CPUState *cs; + uint32_t pil =3D env->pil_in | + (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); + + /* We should be holding the BQL before we mess with IRQs */ + g_assert(qemu_mutex_iothread_locked()); + + /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ + if (env->ivec_status & 0x20) { + return; + } + cs =3D env_cpu(env); + /* + * check if TM or SM in SOFTINT are set + * setting these also causes interrupt 14 + */ + if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { + pil |=3D 1 << 14; + } + + /* + * The bit corresponding to psrpil is (1<< psrpil), + * the next bit is (2 << psrpil). + */ + if (pil < (2 << env->psrpil)) { + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); + env->interrupt_index =3D 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + return; + } + + if (cpu_interrupts_enabled(env)) { + + unsigned int i; + + for (i =3D 15; i > env->psrpil; i--) { + if (pil & (1 << i)) { + int old_interrupt =3D env->interrupt_index; + int new_interrupt =3D TT_EXTINT | i; + + if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_inter= rupt + && ((cpu_tsptr(env)->tt & 0x1f0) =3D=3D TT_EXTINT))) { + trace_sparc64_cpu_check_irqs_noset_irq(env->tl, + cpu_tsptr(env)->tt, + new_interrupt); + } else if (old_interrupt !=3D new_interrupt) { + env->interrupt_index =3D new_interrupt; + trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, + new_interrupt); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + } + } + } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softi= nt, + env->interrupt_index); + env->interrupt_index =3D 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu =3D SPARC_CPU(cs); diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index dfb53dc1a24..d3a30a816aa 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -1,8 +1,6 @@ # See docs/devel/tracing.txt for syntax documentation. =20 # sun4m.c -sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" -sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" =20 diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index a0b29987d2b..b85d14c30c8 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int siz= e) "addr: 0x%"PRIx64" sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "x= late 0x%"PRIx64" =3D> pa 0x%"PRIx64" tte: 0x%"PRIx64 =20 # sparc64.c -sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interr= upt 0x%x)" -sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not= setting CPU IRQ: TL=3D%d current 0x%x >=3D pending 0x%x" -sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU = IRQ %d old=3D0x%x new=3D0x%x" -sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t so= ftint, int intno) "Interrupts disabled, pil=3D0x%08x pil_in=3D0x%08x softin= t=3D0x%08x current interrupt 0x%x" sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d" sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d" sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled" diff --git a/target/sparc/trace-events b/target/sparc/trace-events index e925ddd1cc0..75e7093d5f3 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -10,10 +10,18 @@ mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx,= uint64_t prim_context, u mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_cont= ext, uint64_t sec_context, uint64_t address) "tl=3D%d mmu_idx=3D%d primary = context=3D0x%"PRIx64" secondary context=3D0x%"PRIx64" address=3D0x%"PRIx64 mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32= _t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx6= 4" -> 0x%"PRIx64", mmu_idx=3D%d tl=3D%d primary context=3D0x%"PRIx64" secon= dary context=3D0x%"PRIx64 =20 +# int32_helper.c +sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" +sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" + # int64_helper.c int_helper_set_softint(uint32_t softint) "new 0x%08x" int_helper_clear_softint(uint32_t softint) "new 0x%08x" int_helper_write_softint(uint32_t softint) "new 0x%08x" +sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interr= upt 0x%x)" +sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not= setting CPU IRQ: TL=3D%d current 0x%x >=3D pending 0x%x" +sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU = IRQ %d old=3D0x%x new=3D0x%x" +sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t so= ftint, int intno) "Interrupts disabled, pil=3D0x%08x pil_in=3D0x%08x softin= t=3D0x%08x current interrupt 0x%x" =20 # win_helper.c win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active ps= tate bits=3D0x%x" --=20 2.26.3