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charset="utf-8" From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 ++++++++++++++++++++ target/riscv/translate.c | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 19aa3b4769..2edfc59712 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -407,6 +407,8 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +/* If PointerMasking should be applied */ +FIELD(TB_FLAGS, PM_ENABLED, 10, 1) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 @@ -464,6 +466,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + if (riscv_has_ext(env, RVJ)) { + int priv =3D cpu_mmu_index(env, false); + bool pm_enabled =3D false; + switch (priv) { + case PRV_U: + pm_enabled =3D env->mmte & U_PM_ENABLE; + break; + case PRV_S: + pm_enabled =3D env->mmte & S_PM_ENABLE; + break; + case PRV_M: + pm_enabled =3D env->mmte & M_PM_ENABLE; + break; + default: + g_assert_not_reached(); + } + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); + } #endif =20 *pflags =3D flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2e815a5912..37706d56d5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; +/* globals for PM CSRs */ +static TCGv pm_mask[4]; +static TCGv pm_base[4]; =20 #include "exec/gen-icount.h" =20 @@ -64,6 +67,10 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + /* PointerMasking extension */ + bool pm_enabled; + TCGv pm_mask; + TCGv pm_base; CPUState *cs; } DisasContext; =20 @@ -90,13 +97,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) } =20 /* - * Temp stub: generates address adjustment for PointerMasking + * Generates address adjustment for PointerMasking */ static void gen_pm_adjust_address(DisasContext *s, TCGv_i64 dst, TCGv_i64 src) { - tcg_gen_mov_i64(dst, src); + if (!s->pm_enabled) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else { + tcg_gen_andc_i64(dst, src, s->pm_mask); + tcg_gen_or_i64(dst, dst, s->pm_base); + } } =20 /* @@ -657,6 +670,10 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + int priv =3D cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK; + ctx->pm_mask =3D pm_mask[priv]; + ctx->pm_base =3D pm_base[priv]; ctx->cs =3D cs; } =20 @@ -777,4 +794,19 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); +#ifndef CONFIG_USER_ONLY + /* Assign PM CSRs to tcg globals */ + pm_mask[PRV_U] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmma= sk"); + pm_base[PRV_U] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmba= se"); + pm_mask[PRV_S] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmma= sk"); + pm_base[PRV_S] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmba= se"); + pm_mask[PRV_M] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmma= sk"); + pm_base[PRV_M] =3D + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmba= se"); +#endif } --=20 2.20.1