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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id 6sm4623270wmg.9.2021.04.27.12.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Apr 2021 12:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AeVh7vHBr9M4J89rTy7icLCpfwOC8AVr50lKe1Nh3oU=; b=LFQqUHW5dTzP1haZPcCWcaP+0lTeSU/PXTInst/h/sW5hVptnmVTYDuGPamO82dgNj /JbRf8S/vqIrz4n0ImwD1qrHdbGeu+buoqItDCd6TXt8LNn0KUwRnRGcoZvJ/nW2stjF 1+PccntJNmYAVUrN1seJ9QmG0LAUxqfeKrhCUNzAgUCbjijsUufDDY6u1aqHCSVLpOHw nQtp7oUqlIz5c3eKApi0avsS51bEzqx9QDxc3XK8XBAOJVW6XMSpPNAdMyU5VL9pn066 6/hHKHZq0i8mAFxSxcy9u4ygkPPhciZoH2cKXY7vfoygyegfizVwZiSAVMQasRXx/aCX QTdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AeVh7vHBr9M4J89rTy7icLCpfwOC8AVr50lKe1Nh3oU=; b=mNMeeSibw/0ka+zq77enOg4cnYeeiIBvMMhpNYBEPEgslw+2x5xwBk4xRuDeYEWV0r JwH/x6gmBlTanq3+eE+36qWsGjSbYwBvJ3FdZIjacLQsc8H28T/rfAiI87nmlk3xvvhV 4IW+3AfZCNsyPHA9068QSiOylcauG8/F1ZSjzwir3y6htjvcs2mFBkf+4hvLYAT8nh4z hu6lJMZZ9ab3gemT8DHUvTYhqfbqTpEXuk8I509ETrCBGFDWksdFcCdMjKtJRzEy6k/m JnIVs8O4/pMLAkve91BCkmwsKvDT94kf5xWo6JmplMAUunls/a3hL++m+JVtSl7RnpW6 kZLA== X-Gm-Message-State: AOAM532vACIS15AZ6GfIe8XQAqpxNeNGF7c+icmuHiUnJ8ls7nJa0LjZ Yqco54y928S5aZ7m1vjFWmM= X-Google-Smtp-Source: ABdhPJxppGJRk4tsbUrj1A7fP7lFSG0f6FZuU/C1lGyxOALjEEGRL9pUvNBnuVO4mzD0Dh7EmjMJBQ== X-Received: by 2002:a05:600c:19d1:: with SMTP id u17mr25756666wmq.111.1619551625947; Tue, 27 Apr 2021 12:27:05 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Richard Henderson , Thomas Huth , KONRAD Frederic , Artyom Tarasenko , Fabien Chouteau , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] hw/sparc: Allow building the leon3 machine stand-alone Date: Tue, 27 Apr 2021 21:26:57 +0200 Message-Id: <20210427192658.266933-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210427192658.266933-1-f4bug@amsat.org> References: <20210427192658.266933-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) When building only the leon3 machine, we get this link failure: /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr': target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs' This is because cpu_check_irqs() is defined in hw/sparc/sun4m.c, which is only built if the base sun4m machines are built (with the CONFIG_SUN4M selector). Fix by moving cpu_check_irqs() out of hw/sparc/sun4m.c and build it unconditionally. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc/irq.c | 61 ++++++++++++++++++++++++++++++++++++++++++++ hw/sparc/sun4m.c | 32 ----------------------- hw/sparc/meson.build | 1 + 3 files changed, 62 insertions(+), 32 deletions(-) create mode 100644 hw/sparc/irq.c diff --git a/hw/sparc/irq.c b/hw/sparc/irq.c new file mode 100644 index 00000000000..e34639f266e --- /dev/null +++ b/hw/sparc/irq.c @@ -0,0 +1,61 @@ +/* + * QEMU Sun4m & Sun4d & Sun4c IRQ handling + * + * Copyright (c) 2003-2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "hw/irq.h" +#include "cpu.h" +#include "trace.h" + +void cpu_check_irqs(CPUSPARCState *env) +{ + CPUState *cs; + + /* We should be holding the BQL before we mess with IRQs */ + g_assert(qemu_mutex_iothread_locked()); + + if (env->pil_in && (env->interrupt_index =3D=3D 0 || + (env->interrupt_index & ~15) =3D=3D TT_EXTINT)) { + unsigned int i; + + for (i =3D 15; i > 0; i--) { + if (env->pil_in & (1 << i)) { + int old_interrupt =3D env->interrupt_index; + + env->interrupt_index =3D TT_EXTINT | i; + if (old_interrupt !=3D env->interrupt_index) { + cs =3D env_cpu(env); + trace_sun4m_cpu_interrupt(i); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + } + } + } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { + cs =3D env_cpu(env); + trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); + env->interrupt_index =3D 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 1a00816d9a8..2edf913d945 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -159,38 +159,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr, } } =20 -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - if (env->pil_in && (env->interrupt_index =3D=3D 0 || - (env->interrupt_index & ~15) =3D=3D TT_EXTINT)) { - unsigned int i; - - for (i =3D 15; i > 0; i--) { - if (env->pil_in & (1 << i)) { - int old_interrupt =3D env->interrupt_index; - - env->interrupt_index =3D TT_EXTINT | i; - if (old_interrupt !=3D env->interrupt_index) { - cs =3D env_cpu(env); - trace_sun4m_cpu_interrupt(i); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { - cs =3D env_cpu(env); - trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); - env->interrupt_index =3D 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env =3D &cpu->env; diff --git a/hw/sparc/meson.build b/hw/sparc/meson.build index 19c442c90d9..470159ff659 100644 --- a/hw/sparc/meson.build +++ b/hw/sparc/meson.build @@ -1,4 +1,5 @@ sparc_ss =3D ss.source_set() +sparc_ss.add(files('irq.c')) sparc_ss.add(when: 'CONFIG_LEON3', if_true: files('leon3.c')) sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m.c')) sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m_iommu.c')) --=20 2.26.3 From nobody Fri May 17 22:15:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619551633; cv=none; d=zohomail.com; s=zohoarc; b=nYk4fRUQE3TiK6fax2GcDeP/IBWIuMzSJnVgdobCXKzuzcg4zct3CNYlx1/ZeM+TrqcY6RicJMNXlIaAwbOgJZuk9HzvElXRxfnhufmv7MO9XovJP3vByTowsrvXk4FaRsIH0H0DnGl0eKd5bVWIZnLRirpXByxEnRRgQO8u6As= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619551633; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zejWrx5whd529kSVIv21rXOnhEDRYb09IbWdv8XWcM0=; b=OAwZw4bmDaDEiZ52MY0+O2dYo520Ql1W3a6ByCUPupjKcNFYx2tXpt2NLbpXG4wLgvApM2SMy6wJXYbk0i1PNAg7MHCLG/0fvUwI2hIEY1xK+0Mf57qEChnmTXzTbRFCIPj/aSvxmC8PekD+3kUD+sKCOHndrfLTWr54tb07egc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1619551633035827.3747634653339; Tue, 27 Apr 2021 12:27:13 -0700 (PDT) Received: by mail-wr1-f46.google.com with SMTP id t18so3017245wry.1 for ; Tue, 27 Apr 2021 12:27:12 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id y5sm5287409wrm.61.2021.04.27.12.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Apr 2021 12:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zejWrx5whd529kSVIv21rXOnhEDRYb09IbWdv8XWcM0=; b=rganQD5ImbiEvkmGcs3L9IAYBBLHbN4arFaHeoxNVZhdfYw/Sgg9h2AVBjwQaANb+X JVUisjCChwcyujkAhFnThmnW5ngW/gykumjm1ErMYmyhKSqqFTndhNBRnHMghLXKGh43 gNk9Jrr38/oD1YLcVYWQPJukTBlim0jNbI65lYxX/6m0Ebzqbc4LhDpAgU4Qthj29pb1 vTceCd/LFnNvcWEXEWFzbAiLHmZBrQ2AM/wvDqPG9WNyo6Sw6Vtm0Cf36xvnsBFYLQgS PKEzhqF9+h6uZLUr7TpfHKWjxOVQ71NPgO0Zy5mQOnW12G93lTQYSQAHKrZfVvopqe5L FrFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zejWrx5whd529kSVIv21rXOnhEDRYb09IbWdv8XWcM0=; b=b3KXYUYo5TWe5RjXR2TJ8MiFNAc7W8JPE2CrqssYGbG4jXwc/mkOSfDkLLzz4EZ/2t wLde8S7MoNjWVhXuS9qlNJE9kb22qLhrElesdRPvxXGuab2wkP5BVFpzYG8yITRZsqDP 1ip+4gNaOvRcHEssYmnMbrQFidIV/YzozG7YwiKbCcGzDCvKcNf0dvmB74xXrroCGzRy dAWhwXbhdJ5UOR7NY9Y4pKn3Og7sKrfAZJzYQLlCPuLMfKNnU84NXbtygCmwMcVjODEQ WIJLHvGEM4W0XLxIAt7BHHYKf37BfmSnX0n/uTWKV7duLwl1Yt+iyg836Ifz+NFcf0AJ 5i6w== X-Gm-Message-State: AOAM530X0HwGM+tduUb79Gvk1gGKvfvlckWutUQ3p48d7rTF1e4GXo39 sBUYHMmb9/gAgGr3L3/yJEE= X-Google-Smtp-Source: ABdhPJw7PFDZuK6kYKWtuJzBxTUOB64H88dzL/uC4EtGEuxk8nNhIx4g6AaPH7D1oV1Fdx6uoVHPTw== X-Received: by 2002:adf:ea06:: with SMTP id q6mr7348474wrm.34.1619551631222; Tue, 27 Apr 2021 12:27:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Richard Henderson , Thomas Huth , KONRAD Frederic , Artyom Tarasenko , Fabien Chouteau , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 2/2] hw/sparc: Allow building without the leon3 machine Date: Tue, 27 Apr 2021 21:26:58 +0200 Message-Id: <20210427192658.266933-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210427192658.266933-1-f4bug@amsat.org> References: <20210427192658.266933-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) When building without the leon3 machine, we get this link failure: /usr/bin/ld: target_sparc_int32_helper.c.o: in function `leon3_irq_manage= r': target/sparc/int32_helper.c:172: undefined reference to `leon3_irq_ack' This is because the leon3_irq_ack() is declared in hw/sparc/leon3.c, which is only build when CONFIG_LEON3 is selected. Fix by moving the leon3_cache_control_int() / leon3_irq_manager() (which are specific to the leon3 machine) to hw/sparc/leon3.c. Move the trace events along (but don't rename them). leon3_irq_ack() is now locally used, declare it static to reduce its scope. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: KONRAD Frederic Reviewed-by: Richard Henderson Tested-by: KONRAD Frederic --- RFC: The problem is we have hardware specific code in the architectural translation code. I wish there was a better alternative rather than moving this code to hw/sparc/. --- target/sparc/cpu.h | 6 ------ hw/sparc/leon3.c | 37 ++++++++++++++++++++++++++++++++++++- target/sparc/int32_helper.c | 37 ------------------------------------- hw/sparc/trace-events | 2 ++ target/sparc/trace-events | 4 ---- 5 files changed, 38 insertions(+), 48 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4b2290650be..ff8ae73002a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp); int cpu_cwp_dec(CPUSPARCState *env1, int cwp); void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); =20 -/* int_helper.c */ -void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); - /* sun4m.c, sun4u.c */ void cpu_check_irqs(CPUSPARCState *env); =20 -/* leon3.c */ -void leon3_irq_ack(void *irq_manager, int intno); - #if defined (TARGET_SPARC64) =20 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7e16eea9e67..98e3789cf84 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -137,7 +137,36 @@ static void main_cpu_reset(void *opaque) env->regbase[6] =3D s->sp; } =20 -void leon3_irq_ack(void *irq_manager, int intno) +static void leon3_cache_control_int(CPUSPARCState *env) +{ + uint32_t state =3D 0; + + if (env->cache_control & CACHE_CTRL_IF) { + /* Instruction cache state */ + state =3D env->cache_control & CACHE_STATE_MASK; + if (state =3D=3D CACHE_ENABLED) { + state =3D CACHE_FROZEN; + trace_int_helper_icache_freeze(); + } + + env->cache_control &=3D ~CACHE_STATE_MASK; + env->cache_control |=3D state; + } + + if (env->cache_control & CACHE_CTRL_DF) { + /* Data cache state */ + state =3D (env->cache_control >> 2) & CACHE_STATE_MASK; + if (state =3D=3D CACHE_ENABLED) { + state =3D CACHE_FROZEN; + trace_int_helper_dcache_freeze(); + } + + env->cache_control &=3D ~(CACHE_STATE_MASK << 2); + env->cache_control |=3D (state << 2); + } +} + +static void leon3_irq_ack(void *irq_manager, int intno) { grlib_irqmp_ack((DeviceState *)irq_manager, intno); } @@ -181,6 +210,12 @@ static void leon3_set_pil_in(void *opaque, int n, int = level) } } =20 +static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int i= ntno) +{ + leon3_irq_ack(irq_manager, intno); + leon3_cache_control_int(env); +} + static void leon3_generic_hw_init(MachineState *machine) { ram_addr_t ram_size =3D machine->ram_size; diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 817a463a179..d008dbdb65c 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -136,40 +136,3 @@ void sparc_cpu_do_interrupt(CPUState *cs) } #endif } - -#if !defined(CONFIG_USER_ONLY) -static void leon3_cache_control_int(CPUSPARCState *env) -{ - uint32_t state =3D 0; - - if (env->cache_control & CACHE_CTRL_IF) { - /* Instruction cache state */ - state =3D env->cache_control & CACHE_STATE_MASK; - if (state =3D=3D CACHE_ENABLED) { - state =3D CACHE_FROZEN; - trace_int_helper_icache_freeze(); - } - - env->cache_control &=3D ~CACHE_STATE_MASK; - env->cache_control |=3D state; - } - - if (env->cache_control & CACHE_CTRL_DF) { - /* Data cache state */ - state =3D (env->cache_control >> 2) & CACHE_STATE_MASK; - if (state =3D=3D CACHE_ENABLED) { - state =3D CACHE_FROZEN; - trace_int_helper_dcache_freeze(); - } - - env->cache_control &=3D ~(CACHE_STATE_MASK << 2); - env->cache_control |=3D (state << 2); - } -} - -void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) -{ - leon3_irq_ack(irq_manager, intno); - leon3_cache_control_int(env); -} -#endif diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index 355b07ae057..dfb53dc1a24 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -19,3 +19,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 # leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d" leon3_reset_irq(int intno) "Reset CPU IRQ %d" +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" diff --git a/target/sparc/trace-events b/target/sparc/trace-events index 6a064e23275..e925ddd1cc0 100644 --- a/target/sparc/trace-events +++ b/target/sparc/trace-events @@ -15,10 +15,6 @@ int_helper_set_softint(uint32_t softint) "new 0x%08x" int_helper_clear_softint(uint32_t softint) "new 0x%08x" int_helper_write_softint(uint32_t softint) "new 0x%08x" =20 -# int32_helper.c -int_helper_icache_freeze(void) "Instruction cache: freeze" -int_helper_dcache_freeze(void) "Data cache: freeze" - # win_helper.c win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active ps= tate bits=3D0x%x" win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "= change_pstate: switching regs old=3D0x%x new=3D0x%x" --=20 2.26.3