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Tue, 27 Apr 2021 11:08:55 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-346-pOVXJ9ogOeaWIR0xYMqROw-1; Tue, 27 Apr 2021 11:08:51 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D1E93107ACCA; Tue, 27 Apr 2021 15:08:48 +0000 (UTC) Received: from sirius.home.kraxel.org (ovpn-112-203.ams2.redhat.com [10.36.112.203]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5C9491001901; Tue, 27 Apr 2021 15:08:48 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 4EBCF18007B0; Tue, 27 Apr 2021 17:08:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1619536133; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iRN0sWOjlaApJR3LalQp1kXOI3OmFWRgtSQ9fOzQ8m8=; b=iLnxaPNR/7PNlZcXfvtjhfnY0sk32ZENgqxlXoJRGZjlzuIF4zjnIG3KkviGDPSlh8R6iD G5fXy4xkHo4ysqVkF69iExUgxBEZ/A2Vr5IiqOiG6l+mZZWEompSHb5t4hw8qIumVBmBZl 31Lcgxe8OuiLa+kxTW0mw1GiGP6aI4U= X-MC-Unique: pOVXJ9ogOeaWIR0xYMqROw-1 From: Gerd Hoffmann To: qemu-devel@nongnu.org Subject: [PATCH v2 8/8] edid: add support for DisplayID extension (5k resolution) Date: Tue, 27 Apr 2021 17:08:24 +0200 Message-Id: <20210427150824.638359-9-kraxel@redhat.com> In-Reply-To: <20210427150824.638359-1-kraxel@redhat.com> References: <20210427150824.638359-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=kraxel@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.218, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konstantin Nazarov , Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Konstantin Nazarov The Detailed Timing Descriptor has only 12 bits to store the resolution. This limits the guest to 4095 pixels. This patch adds support for the DisplayID extension, that has 2 full bytes for that purpose, thus allowing 5k resolutions and above. Based-on: <20210303152948.59943-2-akihiko.odaki@gmail.com> Signed-off-by: Konstantin Nazarov Message-Id: <20210315114639.91953-3-mail@knazarov.com> [ kraxel: minor workflow tweaks ] Signed-off-by: Gerd Hoffmann --- hw/display/edid-generate.c | 78 +++++++++++++++++++++++++++++++++++--- hw/display/vga-pci.c | 2 +- 2 files changed, 74 insertions(+), 6 deletions(-) diff --git a/hw/display/edid-generate.c b/hw/display/edid-generate.c index bdd01571fc9b..f2b874d5e358 100644 --- a/hw/display/edid-generate.c +++ b/hw/display/edid-generate.c @@ -229,8 +229,8 @@ static void edid_desc_ranges(uint8_t *desc) desc[7] =3D 30; desc[8] =3D 160; =20 - /* max dot clock (1200 MHz) */ - desc[9] =3D 1200 / 10; + /* max dot clock (2550 MHz) */ + desc[9] =3D 2550 / 10; =20 /* no extended timing information */ desc[10] =3D 0x01; @@ -336,15 +336,61 @@ uint32_t qemu_edid_dpi_to_mm(uint32_t dpi, uint32_t r= es) return res * 254 / 10 / dpi; } =20 +static void init_displayid(uint8_t *did) +{ + did[0] =3D 0x70; /* display id extension */ + did[1] =3D 0x13; /* version 1.3 */ + did[2] =3D 4; /* length */ + did[3] =3D 0x03; /* product type (0x03 =3D=3D standalone display devic= e) */ + edid_checksum(did + 1, did[2] + 4); +} + +static void qemu_displayid_generate(uint8_t *did, uint32_t refresh_rate, + uint32_t xres, uint32_t yres, + uint32_t xmm, uint32_t ymm) +{ + Timings timings; + generate_timings(&timings, refresh_rate, xres, yres); + + did[0] =3D 0x70; /* display id extension */ + did[1] =3D 0x13; /* version 1.3 */ + did[2] =3D 23; /* length */ + did[3] =3D 0x03; /* product type (0x03 =3D=3D standalone display devic= e) */ + + did[5] =3D 0x03; /* Detailed Timings Data Block */ + did[6] =3D 0x00; /* revision */ + did[7] =3D 0x14; /* block length */ + + did[8] =3D timings.clock & 0xff; + did[9] =3D (timings.clock & 0xff00) >> 8; + did[10] =3D (timings.clock & 0xff0000) >> 16; + + did[11] =3D 0x88; /* leave aspect ratio undefined */ + + stw_le_p(did + 12, 0xffff & (xres - 1)); + stw_le_p(did + 14, 0xffff & (timings.xblank - 1)); + stw_le_p(did + 16, 0xffff & (timings.xfront - 1)); + stw_le_p(did + 18, 0xffff & (timings.xsync - 1)); + + stw_le_p(did + 20, 0xffff & (yres - 1)); + stw_le_p(did + 22, 0xffff & (timings.yblank - 1)); + stw_le_p(did + 24, 0xffff & (timings.yfront - 1)); + stw_le_p(did + 26, 0xffff & (timings.ysync - 1)); + + edid_checksum(did + 1, did[2] + 4); +} + void qemu_edid_generate(uint8_t *edid, size_t size, qemu_edid_info *info) { uint8_t *desc =3D edid + 54; uint8_t *xtra3 =3D NULL; uint8_t *dta =3D NULL; + uint8_t *did =3D NULL; uint32_t width_mm, height_mm; uint32_t refresh_rate =3D info->refresh_rate ? info->refresh_rate : 75= 000; uint32_t dpi =3D 100; /* if no width_mm/height_mm */ + uint32_t large_screen =3D 0; =20 /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D set defaults =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 @@ -360,6 +406,9 @@ void qemu_edid_generate(uint8_t *edid, size_t size, if (!info->prefy) { info->prefy =3D 768; } + if (info->prefx >=3D 4096 || info->prefy >=3D 4096) { + large_screen =3D 1; + } if (info->width_mm && info->height_mm) { width_mm =3D info->width_mm; height_mm =3D info->height_mm; @@ -377,6 +426,12 @@ void qemu_edid_generate(uint8_t *edid, size_t size, edid_ext_dta(dta); } =20 + if (size >=3D 384 && large_screen) { + did =3D edid + 256; + edid[126]++; + init_displayid(did); + } + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D header information = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 /* fixed */ @@ -441,9 +496,12 @@ void qemu_edid_generate(uint8_t *edid, size_t size, =20 /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D descriptor blocks =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 - edid_desc_timing(desc, refresh_rate, info->prefx, info->prefy, - width_mm, height_mm); - desc =3D edid_desc_next(edid, dta, desc); + if (!large_screen) { + /* The DTD section has only 12 bits to store the resolution */ + edid_desc_timing(desc, refresh_rate, info->prefx, info->prefy, + width_mm, height_mm); + desc =3D edid_desc_next(edid, dta, desc); + } =20 xtra3 =3D desc; edid_desc_xtra3_std(xtra3); @@ -472,12 +530,22 @@ void qemu_edid_generate(uint8_t *edid, size_t size, desc =3D edid_desc_next(edid, dta, desc); } =20 + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D display id extensions= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ + + if (did && large_screen) { + qemu_displayid_generate(did, refresh_rate, info->prefx, info->pref= y, + width_mm, height_mm); + } + /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D finish up =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 edid_checksum(edid, 127); if (dta) { edid_checksum(dta, 127); } + if (did) { + edid_checksum(did, 127); + } } =20 size_t qemu_edid_size(uint8_t *edid) diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c index 48d29630ab77..62fb5c38c1fd 100644 --- a/hw/display/vga-pci.c +++ b/hw/display/vga-pci.c @@ -49,7 +49,7 @@ struct PCIVGAState { qemu_edid_info edid_info; MemoryRegion mmio; MemoryRegion mrs[4]; - uint8_t edid[256]; + uint8_t edid[384]; }; =20 #define TYPE_PCI_VGA "pci-vga" --=20 2.30.2