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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id d13sm1552982wrx.29.2021.04.27.03.35.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Apr 2021 03:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HU/4yCgl1rj3i5y1lhl7YgDAybnUSgnMfeYGKSw62FU=; b=cH82a4Mzxf7eAQt0esKPyI3zm+AmlSbW/+I17AT91JDrVgJaUNHK5GcLjMKUbpASGB oUg335RNeWbzzK+mbatALd91hRJKZjkZPv2mpjPjfNhJymwC2O5G88IT4Sxh7hyz7NLX 8W1PM8cLC9MbSfj01Bcnox04KdhuFaN5qN2n7Wtjg+5muDGMxSv3HepQSX9t8/D3zowM RxSv1g8LeHFZuXI+ElpLA64EWTN5Dk65Azh3Qja4KcrE3OVYeA8vJWlly3w23wE6hETn IYs3ZGeY0juzViiMHitM6rUboQRt3RZqV83gm6jFEEtfVmHTP0sKzT4t1VEBUf4j+17P hSNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=HU/4yCgl1rj3i5y1lhl7YgDAybnUSgnMfeYGKSw62FU=; b=XQ+8gJJziEovN3l62SGb4WmgNj5ZJynWs3kR0LeHfaJ/p2iUOirt+IFr0wIgtQd+Tp +rXWdzv7k2dA60yXpfYj0NPg6kCE0CXwnszuV4y+FZ85T9EJ5wegV4t43RoOdR5gwVZ3 Ok4Mtmp9qHdXIsyvb5x8vVMKqtg534BP/wQ8daPY69sCKaPmv8mnrxw8vu8NM+4EWYGL xEF1E4ZBb22HqNaKM9xTlqvmjHlt0i0DHJaKpJH0NKu25py/+W94Zpf/HkGIE4zlRcLF oJXVASZpZk4eUY26tff1F8hqkGvP+Uvk1rGjdYQhkaIWUtAPHlczOwJBlaVlBQGlAB5y gKIw== X-Gm-Message-State: AOAM5333QA6knSjo0XR1xPQp0xux+0+uwNeUGc2eeJ6BsU5I7OhRMmuG vkXIPSAkTswBujF5R5jufTs= X-Google-Smtp-Source: ABdhPJxiSIkD37z/sQ+ck+DqeDhPEa72eZBp2wyv8XM3JxiEVBQdo2qel7aZQtM0+fWKtwVVtVlAzA== X-Received: by 2002:a05:600c:4f13:: with SMTP id l19mr3703516wmq.47.1619519757865; Tue, 27 Apr 2021 03:35:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , 1926277@bugs.launchpad.net, Aleksandar Rikalo , Jiaxun Yang , "Edgar E . Iglesias" , Aurelien Jarno Subject: [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE Date: Tue, 27 Apr 2021 12:35:55 +0200 Message-Id: <20210427103555.112652-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) According to the 'MIPS MT Application-Speci=EF=AC=81c Extension' manual: If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction. Add the VPEConf0.MVP bit and modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit if executed on a master VPE. Reported-by: Hansni Bu Buglink: https://bugs.launchpad.net/qemu/+bug/1926277 Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 1 + target/mips/cp0_helper.c | 32 ++++++++++++++++++-------------- 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..bd22fac6959 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -114,6 +114,7 @@ struct CPUMIPSMVPContext { #define CP0MVPC0_PTLBE 16 #define CP0MVPC0_TCA 15 #define CP0MVPC0_PVPE 10 +#define CP0MVPC0_MVP 1 #define CP0MVPC0_PTC 0 int32_t CP0_MVPConf1; #define CP0MVPC1_CIM 31 diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index aae2af6eccc..1e39e28808a 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env) CPUState *other_cs =3D first_cpu; target_ulong prev =3D env->mvp->CP0_MVPControl; =20 - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - /* Turn off all VPEs except the one executing the dvpe. */ - if (&other_cpu->env !=3D env) { - other_cpu->env.mvp->CP0_MVPControl &=3D ~(1 << CP0MVPCo_EVP); - mips_vpe_sleep(other_cpu); + if (env->mvp->CP0_MVPConf0 & (1 << CP0MVPC0_MVP)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + /* Turn off all VPEs except the one executing the dvpe. */ + if (&other_cpu->env !=3D env) { + other_cpu->env.mvp->CP0_MVPControl &=3D ~(1 << CP0MVPCo_EV= P); + mips_vpe_sleep(other_cpu); + } } } return prev; @@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env) CPUState *other_cs =3D first_cpu; target_ulong prev =3D env->mvp->CP0_MVPControl; =20 - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + if (env->mvp->CP0_MVPConf0 & (1 << CP0MVPC0_MVP)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); =20 - if (&other_cpu->env !=3D env - /* If the VPE is WFI, don't disturb its sleep. */ - && !mips_vpe_is_wfi(other_cpu)) { - /* Enable the VPE. */ - other_cpu->env.mvp->CP0_MVPControl |=3D (1 << CP0MVPCo_EVP); - mips_vpe_wake(other_cpu); /* And wake it up. */ + if (&other_cpu->env !=3D env + /* If the VPE is WFI, don't disturb its sleep. */ + && !mips_vpe_is_wfi(other_cpu)) { + /* Enable the VPE. */ + other_cpu->env.mvp->CP0_MVPControl |=3D (1 << CP0MVPCo_EVP= ); + mips_vpe_wake(other_cpu); /* And wake it up. */ + } } } return prev; --=20 2.26.3