From nobody Fri May 17 19:31:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1619511072; cv=none; d=zohomail.com; s=zohoarc; b=mmx7xIT6Mo4XRbl7eb3yoK/BHVMhYszggFNnqKjHjDcp3DHuivUflYrITg3iTLrHKZeyH83cL2FjTYiLvKzDQVS/3GeKNf/6F3JmCuXPBzaVf3rByngd1QndTrRh/op8F1r6kkOd+zKziZbewQFE+zrmE1VCpHOH7+TppmHS1Us= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619511072; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=gd+aLdhp4S8r+Gr1UrhEbfYgo9c9ww/ldvadWP+eFL4=; b=JuprxqOqXfQBTIau2VN6Z0ansYqsLM2OtFmssD8spwSUQLXoaU6h66CIQ5qjE/pWiI37frkVFM1RFD5nO4vX/e11y9VWu6AAqacqAkf+/rFXMb4MHOVKG+8Cs64RmGLxd5vqeKdJSpcP0sORZcV/fjGjhdw971c0owFUu0jekxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1619511072224212.86176039245163; Tue, 27 Apr 2021 01:11:12 -0700 (PDT) Received: from localhost ([::1]:44022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lbIoI-0007PI-9R for importer@patchew.org; Tue, 27 Apr 2021 04:11:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lbInP-0006un-22 for qemu-devel@nongnu.org; Tue, 27 Apr 2021 04:10:15 -0400 Received: from mga06.intel.com ([134.134.136.31]:32266) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lbInM-0007Qx-Uu for qemu-devel@nongnu.org; Tue, 27 Apr 2021 04:10:14 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2021 01:10:10 -0700 Received: from clx-ap-likexu.sh.intel.com ([10.239.48.108]) by fmsmga002.fm.intel.com with ESMTP; 27 Apr 2021 01:10:07 -0700 IronPort-SDR: O5nspSHZ3iZIyZX7yoV4hTJfLHqu77bq6c7VAEYpgTgrmMVxnuwJC5qIaBxvtAyr1T2vHpXW+b 1l8Jbw16g+sQ== X-IronPort-AV: E=McAfee;i="6200,9189,9966"; a="257772827" X-IronPort-AV: E=Sophos;i="5.82,254,1613462400"; d="scan'208";a="257772827" IronPort-SDR: sGbEaj+6M1sbxOiDxcF2mVKvjebr5hJh0R2S+CHmBt1UOrFT/td6jn6eRWjDa14v9IUBYlO1Ol nJzwdlakZtig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,254,1613462400"; d="scan'208";a="457518850" From: Like Xu To: Paolo Bonzini , Eduardo Habkost Subject: [PATCH v2] target/i386: add "-cpu, lbr-fmt=*" support to enable guest LBR Date: Tue, 27 Apr 2021 16:09:48 +0800 Message-Id: <20210427080948.439432-1-like.xu@linux.intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=like.xu@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei.w.wang@intel.com, Marcelo Tosatti , Richard Henderson , qemu-devel@nongnu.org, Like Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The last branch recording (LBR) is a performance monitor unit (PMU) feature on Intel processors that records a running trace of the most recent branches taken by the processor in the LBR stack. The QEMU could configure whether it's enabled or not for each guest via CLI. The LBR feature would be enabled on the guest if: - the KVM is enabled and the PMU is enabled and, - the msr-based-feature IA32_PERF_CAPABILITIES is supporterd on KVM and, - the supported returned value for lbr_fmt from this msr is not zero and, - the requested guest vcpu model does support FEAT_1_ECX.CPUID_EXT_PDCM, - the configured lbr-fmt value is the same as the host lbr_fmt value OR use the QEMU option "-cpu host,migratable=3Dno". Signed-off-by: Like Xu --- target/i386/cpu.c | 34 ++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 10 ++++++++++ target/i386/kvm/kvm.c | 10 ++++++++-- 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ad99cad0e7..9c8e54aa6f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6623,6 +6623,10 @@ static void x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) } =20 for (w =3D 0; w < FEATURE_WORDS; w++) { + if (w =3D=3D FEAT_PERF_CAPABILITIES) { + continue; + } + uint64_t host_feat =3D x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features =3D env->features[w]; @@ -6630,6 +6634,27 @@ static void x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) mark_unavailable_features(cpu, w, unavailable_features, prefix); } =20 + uint64_t host_perf_cap =3D + x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); + if (!cpu->lbr_fmt && !cpu->migratable) { + cpu->lbr_fmt =3D host_perf_cap & PERF_CAP_LBR_FMT; + if (cpu->lbr_fmt) { + info_report("vPMU: The value of lbr-fmt has been adjusted " + "to 0x%lx and guest LBR is enabled.", + host_perf_cap & PERF_CAP_LBR_FMT); + } + } else { + uint64_t requested_lbr_fmt =3D cpu->lbr_fmt & PERF_CAP_LBR_FMT; + if (requested_lbr_fmt && kvm_enabled()) { + if (requested_lbr_fmt !=3D (host_perf_cap & PERF_CAP_LBR_FMT))= { + cpu->lbr_fmt =3D 0; + warn_report("vPMU: The supported lbr-fmt value on the host= " + "is 0x%lx and guest LBR is disabled.", + host_perf_cap & PERF_CAP_LBR_FMT); + } + } + } + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && kvm_enabled()) { KVMState *s =3D CPU(cpu)->kvm_state; @@ -6734,6 +6759,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) } } =20 + if (cpu->lbr_fmt) { + if (!cpu->enable_pmu) { + error_setg(errp, "LBR is unsupported since guest PMU is disabl= ed."); + return; + } + env->features[FEAT_PERF_CAPABILITIES] |=3D cpu->lbr_fmt; + } + /* mwait extended info: needed for Core compatibility */ /* We always wake on interrupt even if host does not have the capabili= ty */ cpu->mwait.ecx |=3D CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; @@ -7300,6 +7333,7 @@ static Property x86_cpu_properties[] =3D { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), + DEFINE_PROP_UINT8("lbr-fmt", X86CPU, lbr_fmt, 0), =20 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_NOTIFY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916878..b12c879fc4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -354,6 +354,7 @@ typedef enum X86Seg { #define ARCH_CAP_TSX_CTRL_MSR (1<<7) =20 #define MSR_IA32_PERF_CAPABILITIES 0x345 +#define PERF_CAP_LBR_FMT 0x3f =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -1726,6 +1727,15 @@ struct X86CPU { */ bool enable_pmu; =20 + /* + * Configure LBR_FMT bits on IA32_PERF_CAPABILITIES MSR. + * This can't be enabled by default yet because it doesn't have + * ABI stability guarantees, as it is only allowed to pass all + * LBR_FMT bits returned by kvm_arch_get_supported_msr_feature() + * (that depends on host CPU and kernel capabilities) to the guest. + */ + uint8_t lbr_fmt; + /* LMCE support can be enabled/disabled via cpu option 'lmce=3Don/off'= . It is * disabled by default to avoid breaking migration between QEMU with * different LMCE configurations. diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7fe9f52710..aa926984ae 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2732,8 +2732,14 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, Feat= ureWordArray f) MSR_IA32_PERF_CAPABILITIES); =20 if (kvm_perf_cap) { - kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, - kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); + kvm_perf_cap =3D (cpu->migratable) ? + (kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]) : kvm_perf_cap; + + if (!cpu->lbr_fmt) { + kvm_perf_cap &=3D ~PERF_CAP_LBR_FMT; + } + + kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, kvm_perf_cap); } } =20 --=20 2.30.2