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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id z66sm464116wmc.4.2021.04.26.12.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Apr 2021 12:35:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1619465755; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/NBJrN/GlacMceBg1qLAcbh146RyM7XsMz2+vmFelAU=; b=a7aVwo0pmpruDVLEI/jgxKi06uActu6hBFUVdUw7XP/zI0PoYpxTQvh7jSheaPbig52X7/ 1PBGOBfxnFbwBam2AVKP9W4KU5az+rRdnnNOCsSNp5BAHLaITuahMWC/hGZWA/czbD6zvc G9jHsxkrcya+TedVCysXtiogS2qOc7Y= X-MC-Unique: cbuONM_MMDSruE5R3l_gNQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/NBJrN/GlacMceBg1qLAcbh146RyM7XsMz2+vmFelAU=; b=pe54ioctOhPTZ9Wycm1t7yvbvOf6wav8eKU44qQAgAZJ7t1GLeJ2RKoL/g/QTp2F2r N8aUbqxEFXohmrYTEWN6GsqXRcZv++FZyct/3jQ8hhjQXYUvmY59KATrIgC4wJFcpod+ wyJ6UoyqF8WzKZnA8A23aRo/zBaSb1Ml242u97P/ZP/HRzv/iM3z2Ajp69G4mM9Fp+k0 zW28jveYTO8xVnZ1jcAU9JbmRAIhCvk1TdcOXGlKrbzavfK/JqDM2q56n/gndBS/ws8o ZlTjJPnwxlr3MDLSMsdyGFiSt5Pru4QFojjHC2eJMZzjhdXknJ4y9icCcKeagVr9eZyI 7HjQ== X-Gm-Message-State: AOAM53177AkteLPHhA1+eowkMl4yoz/FT4njDcOfFN3r5BBecx6HyM4o sQdKoBScHv674o7bbgItDbpt8YfnwJIqajzw3CgYNaD+4s1UNQEP9iNLO9rnFwNhhirBa7M8cdB o1QkLUFWfrwfUHA== X-Received: by 2002:adf:e7c2:: with SMTP id e2mr5882926wrn.180.1619465751927; Mon, 26 Apr 2021 12:35:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyumkVOaHD3aoGHNGy6imfLuSzZSB+RGcJEgtKiYDmsVoADFCUmJ8o9mNaeKN1+mXVVQ6HPvw== X-Received: by 2002:adf:e7c2:: with SMTP id e2mr5882895wrn.180.1619465751734; Mon, 26 Apr 2021 12:35:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , qemu-riscv@nongnu.org, Laszlo Ersek , qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Richard Henderson , Helge Deller , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann Subject: [PATCH 6/7] hw/{arm,hppa,riscv}: Add fw_cfg arch-specific stub Date: Mon, 26 Apr 2021 21:35:19 +0200 Message-Id: <20210426193520.4115528-7-philmd@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210426193520.4115528-1-philmd@redhat.com> References: <20210426193520.4115528-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) The ARM, HPPA and RISC-V architectures don't declare any fw_cfg specific key. To simplify the buildsys machinery and allow building QEMU without the fw_cfg device (in the next commit), first add a per-architecture empty stub defining the fw_cfg_arch_key_name(). Update the MAINTAINERS section to cover the various target-specific fw_cfg.c files. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/fw_cfg.c | 19 +++++++++++++++++++ hw/hppa/fw_cfg.c | 19 +++++++++++++++++++ hw/riscv/fw_cfg.c | 19 +++++++++++++++++++ MAINTAINERS | 2 +- hw/arm/meson.build | 1 + hw/hppa/meson.build | 1 + hw/riscv/meson.build | 1 + 7 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 hw/arm/fw_cfg.c create mode 100644 hw/hppa/fw_cfg.c create mode 100644 hw/riscv/fw_cfg.c diff --git a/hw/arm/fw_cfg.c b/hw/arm/fw_cfg.c new file mode 100644 index 00000000000..de2bca9c76c --- /dev/null +++ b/hw/arm/fw_cfg.c @@ -0,0 +1,19 @@ +/* + * QEMU fw_cfg helpers (ARM specific) + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Author: + * Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/mips/fw_cfg.h" +#include "hw/nvram/fw_cfg.h" + +const char *fw_cfg_arch_key_name(uint16_t key) +{ + return NULL; +} diff --git a/hw/hppa/fw_cfg.c b/hw/hppa/fw_cfg.c new file mode 100644 index 00000000000..322b03068c7 --- /dev/null +++ b/hw/hppa/fw_cfg.c @@ -0,0 +1,19 @@ +/* + * QEMU fw_cfg helpers (HPPA specific) + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Author: + * Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/mips/fw_cfg.h" +#include "hw/nvram/fw_cfg.h" + +const char *fw_cfg_arch_key_name(uint16_t key) +{ + return NULL; +} diff --git a/hw/riscv/fw_cfg.c b/hw/riscv/fw_cfg.c new file mode 100644 index 00000000000..8e3d2a8bdea --- /dev/null +++ b/hw/riscv/fw_cfg.c @@ -0,0 +1,19 @@ +/* + * QEMU fw_cfg helpers (RISC-V specific) + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Author: + * Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/mips/fw_cfg.h" +#include "hw/nvram/fw_cfg.h" + +const char *fw_cfg_arch_key_name(uint16_t key) +{ + return NULL; +} diff --git a/MAINTAINERS b/MAINTAINERS index 36055f14c59..ab8f030d4c0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2162,7 +2162,7 @@ R: Laszlo Ersek R: Gerd Hoffmann S: Supported F: docs/specs/fw_cfg.txt -F: hw/nvram/fw_cfg*.c +F: hw/*/fw_cfg*.c F: stubs/fw_cfg.c F: include/hw/nvram/fw_cfg.h F: include/standard-headers/linux/qemu_fw_cfg.h diff --git a/hw/arm/meson.build b/hw/arm/meson.build index be39117b9b6..fd278de916f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -1,6 +1,7 @@ arm_ss =3D ss.source_set() arm_ss.add(files('boot.c'), fdt) arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c')) +arm_ss.add(when: 'CONFIG_FW_CFG', if_true: files('fw_cfg.c')) arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build index 1deae83aee8..10494cc24b7 100644 --- a/hw/hppa/meson.build +++ b/hw/hppa/meson.build @@ -1,4 +1,5 @@ hppa_ss =3D ss.source_set() hppa_ss.add(when: 'CONFIG_DINO', if_true: files('pci.c', 'machine.c', 'din= o.c', 'lasi.c')) +hppa_ss.add(when: 'CONFIG_FW_CFG', if_true: files('fw_cfg.c')) =20 hw_arch +=3D {'hppa': hppa_ss} diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 275c0f7eb7c..ab4d3adb924 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -8,5 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) +riscv_ss.add(when: 'CONFIG_FW_CFG', if_true: files('fw_cfg.c')) =20 hw_arch +=3D {'riscv': riscv_ss} --=20 2.26.3