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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Pull out the fpa11 emulation to a helper function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/arm/cpu_loop.c | 153 +++++++++++++++++++++++--------------- 1 file changed, 94 insertions(+), 59 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 989d03cd89..106909c7d8 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -224,6 +224,92 @@ static bool insn_is_linux_bkpt(uint32_t opcode, bool i= s_thumb) } } =20 +static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) +{ + TaskState *ts =3D env_cpu(env)->opaque; + int rc =3D EmulateAll(opcode, &ts->fpa, env); + + if (rc =3D=3D 0) { + /* Illegal instruction */ + return false; + } + if (rc > 0) { + /* Everything ok. */ + env->regs[15] +=3D 4; + return true; + } + + /* FP exception */ + int arm_fpe =3D 0; + + /* Translate softfloat flags to FPSR flags */ + if (-rc & float_flag_invalid) { + arm_fpe |=3D BIT_IOC; + } + if (-rc & float_flag_divbyzero) { + arm_fpe |=3D BIT_DZC; + } + if (-rc & float_flag_overflow) { + arm_fpe |=3D BIT_OFC; + } + if (-rc & float_flag_underflow) { + arm_fpe |=3D BIT_UFC; + } + if (-rc & float_flag_inexact) { + arm_fpe |=3D BIT_IXC; + } + + /* Exception enabled? */ + FPSR fpsr =3D ts->fpa.fpsr; + if (fpsr & (arm_fpe << 16)) { + target_siginfo_t info; + + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + + /* ordered by priority, least first */ + if (arm_fpe & BIT_IXC) { + info.si_code =3D TARGET_FPE_FLTRES; + } + if (arm_fpe & BIT_UFC) { + info.si_code =3D TARGET_FPE_FLTUND; + } + if (arm_fpe & BIT_OFC) { + info.si_code =3D TARGET_FPE_FLTOVF; + } + if (arm_fpe & BIT_DZC) { + info.si_code =3D TARGET_FPE_FLTDIV; + } + if (arm_fpe & BIT_IOC) { + info.si_code =3D TARGET_FPE_FLTINV; + } + + info._sifields._sigfault._addr =3D env->regs[15]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } else { + env->regs[15] +=3D 4; + } + + /* Accumulate unenabled exceptions */ + if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) { + fpsr |=3D BIT_IXC; + } + if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) { + fpsr |=3D BIT_UFC; + } + if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) { + fpsr |=3D BIT_OFC; + } + if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) { + fpsr |=3D BIT_DZC; + } + if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) { + fpsr |=3D BIT_IOC; + } + ts->fpa.fpsr =3D fpsr; + return true; +} + void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); @@ -244,9 +330,7 @@ void cpu_loop(CPUARMState *env) case EXCP_NOCP: case EXCP_INVSTATE: { - TaskState *ts =3D cs->opaque; uint32_t opcode; - int rc; =20 /* we handle the FPU emulation here, as Linux */ /* we get the opcode */ @@ -263,64 +347,15 @@ void cpu_loop(CPUARMState *env) goto excp_debug; } =20 - rc =3D EmulateAll(opcode, &ts->fpa, env); - if (rc =3D=3D 0) { /* illegal instruction */ - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->regs[15]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } else if (rc < 0) { /* FP exception */ - int arm_fpe=3D0; - - /* translate softfloat flags to FPSR flags */ - if (-rc & float_flag_invalid) - arm_fpe |=3D BIT_IOC; - if (-rc & float_flag_divbyzero) - arm_fpe |=3D BIT_DZC; - if (-rc & float_flag_overflow) - arm_fpe |=3D BIT_OFC; - if (-rc & float_flag_underflow) - arm_fpe |=3D BIT_UFC; - if (-rc & float_flag_inexact) - arm_fpe |=3D BIT_IXC; - - FPSR fpsr =3D ts->fpa.fpsr; - //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); - - if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ - info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; - - /* ordered by priority, least first */ - if (arm_fpe & BIT_IXC) info.si_code =3D TARGET_FPE_F= LTRES; - if (arm_fpe & BIT_UFC) info.si_code =3D TARGET_FPE_F= LTUND; - if (arm_fpe & BIT_OFC) info.si_code =3D TARGET_FPE_F= LTOVF; - if (arm_fpe & BIT_DZC) info.si_code =3D TARGET_FPE_F= LTDIV; - if (arm_fpe & BIT_IOC) info.si_code =3D TARGET_FPE_F= LTINV; - - info._sifields._sigfault._addr =3D env->regs[15]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &inf= o); - } else { - env->regs[15] +=3D 4; - } - - /* accumulate unenabled exceptions */ - if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) - fpsr |=3D BIT_IXC; - if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) - fpsr |=3D BIT_UFC; - if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) - fpsr |=3D BIT_OFC; - if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) - fpsr |=3D BIT_DZC; - if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) - fpsr |=3D BIT_IOC; - ts->fpa.fpsr=3Dfpsr; - } else { /* everything OK */ - /* increment PC */ - env->regs[15] +=3D 4; + if (emulate_arm_fpa11(env, opcode)) { + break; } + + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->regs[15]; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; case EXCP_SWI: --=20 2.25.1 From nobody Sat May 18 04:46:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 23 Apr 2021 09:54:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/4] linux-user/arm: Do not emulate fpa11 in thumb mode Date: Fri, 23 Apr 2021 09:54:11 -0700 Message-Id: <20210423165413.338259-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210423165413.338259-1-richard.henderson@linaro.org> References: <20210423165413.338259-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These antiquated instructions are arm-mode only. Buglink: https://bugs.launchpad.net/bugs/1925512 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/arm/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 106909c7d8..e2a1496b9f 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -347,7 +347,7 @@ void cpu_loop(CPUARMState *env) goto excp_debug; } =20 - if (emulate_arm_fpa11(env, opcode)) { + if (!env->thumb && emulate_arm_fpa11(env, opcode)) { break; } =20 --=20 2.25.1 From nobody Sat May 18 04:46:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619197448; cv=none; d=zohomail.com; s=zohoarc; b=GOM7av+EQJJ8IVENvm6r2XT9FjtbinfA4+3Z4OlPU9ywXuWOL3DJj6rVqBLB2Bv4ifOrIVYHbgKrYjgPkAqZx03D8YuMOWxzwJq+ZqZcQbJVrmoaVLUqHE2HYjw3XyrMc7H6HaHEAtetoZPnes8PFlI7+JnJg+TufFuZ60h0C/Y= ARC-Message-Signature: i=1; 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Fri, 23 Apr 2021 09:54:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/4] linux-user/arm: Do not fill in si_code for fpa11 exceptions Date: Fri, 23 Apr 2021 09:54:12 -0700 Message-Id: <20210423165413.338259-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210423165413.338259-1-richard.henderson@linaro.org> References: <20210423165413.338259-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" There is no such decoding in linux/arch/arm/nwfpe/fpmodule.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/arm/cpu_loop.c | 26 ++++++-------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index e2a1496b9f..5f61d25717 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -262,29 +262,15 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint3= 2_t opcode) /* Exception enabled? */ FPSR fpsr =3D ts->fpa.fpsr; if (fpsr & (arm_fpe << 16)) { - target_siginfo_t info; + target_siginfo_t info =3D { }; =20 + /* + * The kernel's nwfpe emulator does not pass a real si_code. + * It merely uses send_sig(SIGFPE, current, 1). + */ info.si_signo =3D TARGET_SIGFPE; - info.si_errno =3D 0; + info.si_code =3D TARGET_SI_KERNEL; =20 - /* ordered by priority, least first */ - if (arm_fpe & BIT_IXC) { - info.si_code =3D TARGET_FPE_FLTRES; - } - if (arm_fpe & BIT_UFC) { - info.si_code =3D TARGET_FPE_FLTUND; - } - if (arm_fpe & BIT_OFC) { - info.si_code =3D TARGET_FPE_FLTOVF; - } - if (arm_fpe & BIT_DZC) { - info.si_code =3D TARGET_FPE_FLTDIV; - } - if (arm_fpe & BIT_IOC) { - info.si_code =3D TARGET_FPE_FLTINV; - } - - info._sifields._sigfault._addr =3D env->regs[15]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } else { env->regs[15] +=3D 4; --=20 2.25.1 From nobody Sat May 18 04:46:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1619197234; cv=none; d=zohomail.com; s=zohoarc; b=I1LAHpC28hithTnD3OVrpftuDhPy0kIUEwoIAoXz3+XhZsHdeLF30oU7nrNdEIWdDn/nE0JwFusX7QURnrYdXQCg9BZgPR3S5kHgHrSNspiwD+XoyluRyh7sfn84kk0zPQM+1/TwuFl/dpgw2j4EkMbLNz6hElNe+gSR6anpO4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619197234; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use bit masking instead of an if tree. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/arm/cpu_loop.c | 50 ++++++++++++++------------------------- 1 file changed, 18 insertions(+), 32 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 5f61d25717..69632d15be 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -228,6 +228,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_= t opcode) { TaskState *ts =3D env_cpu(env)->opaque; int rc =3D EmulateAll(opcode, &ts->fpa, env); + int raise, enabled; =20 if (rc =3D=3D 0) { /* Illegal instruction */ @@ -240,28 +241,31 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint3= 2_t opcode) } =20 /* FP exception */ - int arm_fpe =3D 0; + rc =3D -rc; + raise =3D 0; =20 /* Translate softfloat flags to FPSR flags */ - if (-rc & float_flag_invalid) { - arm_fpe |=3D BIT_IOC; + if (rc & float_flag_invalid) { + raise |=3D BIT_IOC; } - if (-rc & float_flag_divbyzero) { - arm_fpe |=3D BIT_DZC; + if (rc & float_flag_divbyzero) { + raise |=3D BIT_DZC; } - if (-rc & float_flag_overflow) { - arm_fpe |=3D BIT_OFC; + if (rc & float_flag_overflow) { + raise |=3D BIT_OFC; } - if (-rc & float_flag_underflow) { - arm_fpe |=3D BIT_UFC; + if (rc & float_flag_underflow) { + raise |=3D BIT_UFC; } - if (-rc & float_flag_inexact) { - arm_fpe |=3D BIT_IXC; + if (rc & float_flag_inexact) { + raise |=3D BIT_IXC; } =20 - /* Exception enabled? */ - FPSR fpsr =3D ts->fpa.fpsr; - if (fpsr & (arm_fpe << 16)) { + /* Accumulate unenabled exceptions */ + enabled =3D ts->fpa.fpsr >> 16; + ts->fpa.fpsr |=3D raise & ~enabled; + + if (raise & enabled) { target_siginfo_t info =3D { }; =20 /* @@ -275,24 +279,6 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32= _t opcode) } else { env->regs[15] +=3D 4; } - - /* Accumulate unenabled exceptions */ - if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) { - fpsr |=3D BIT_IXC; - } - if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) { - fpsr |=3D BIT_UFC; - } - if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) { - fpsr |=3D BIT_OFC; - } - if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) { - fpsr |=3D BIT_DZC; - } - if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) { - fpsr |=3D BIT_IOC; - } - ts->fpa.fpsr =3D fpsr; return true; } =20 --=20 2.25.1