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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id f8sm4722323wmc.8.2021.04.22.12.40.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u97TgdNmVP+rrDy4303u5Ji0DugOVEo4Yv+WSGhNYX4=; b=IdRRB6pgR0gC+P54bW9ofjGGmCAETSs06cABzcq/oeA/IarUvZiiUgKRP2O7c8PuqG NMFpaj3lqUtGmIEJuLs2hvvr5k0I68XXmUk1GsRGZDvZCl+h9BXtePsNxyi6uHFA2u1E NJKJi0QCm6pPF1H+OxkqbjdF1fASc/T4gPosdLgh+FRgd4eMxR35qJWJVadu89Xh6iHn DExnZIKcObdypaUJwVKYRJW/tE4narXzkSVE8xKz8wP1jLaFJvXMOvcfljvpP4SnzYc5 eWw5OZQ7BOq5WIaMhWqRHgzDbzt8EoNmNPirz+kcEc6wgU1Vk5Ol/P2DRTS/rZyuefjB a/aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=u97TgdNmVP+rrDy4303u5Ji0DugOVEo4Yv+WSGhNYX4=; b=RzOi95B+7fheiAMBlhwREKTLeRpnoi+QBwmdltEvOjxIvlHIKtQ2m2QGN9KByHzEqu qQZWOkvgERNDyogi/U/SAdLWoumCXawKzPsPH0p0Fu4ukWepDdyWkpBYHDaYZOdIGW7P hEdgZNWSVh9JxPgiKgd4p85plAlgcp0cysmSkFeni0ATABSoKVVFqUtwIgISHLqOs8Nz dpXjtG02zsHoQqiK5s54Q1r1SPxqXZDU2X+daHaEUy7dhxG70TxT0t4xZaQTFB1zbWQ9 RgfxzryTbqF/WsFlkVFCb5tvFJbCqmc+4/HfzEbjflSA0Jvwlgs/9gwBbyI/00F8ASyU zNAQ== X-Gm-Message-State: AOAM533JmgoaI7IhLwuUkd0IT2KvrpiZRAr6BDKjS9+A0hQ/uEDFi32g yv2fvgjD0jKZAwlRBFYhjS0= X-Google-Smtp-Source: ABdhPJzHd+NrrI9QUSC7WCoToPcf2rK6Cja77TDbeXx+eKv15K3/mGwz1LweKfRLB2Xi/sl74/8unQ== X-Received: by 2002:adf:e8cf:: with SMTP id k15mr40347wrn.112.1619120419753; Thu, 22 Apr 2021 12:40:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini Subject: [PATCH v6 14/18] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps Date: Thu, 22 Apr 2021 21:38:58 +0200 Message-Id: <20210422193902.2644064-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7095bc4192..28c4fc541a2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index bdc76d580e9..52a05ea9b3e 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c74390aafbf..c44229205ff 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cbfdb9d0b70..e030890c11b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fd7788907ea..70b0108b748 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -7434,7 +7435,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3