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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id l14sm4193994wmq.4.2021.04.22.12.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JQ0OTstwzXipk72lX8fvK3spe8ZEv2YAFM7sdltFU54=; b=XsECYQeA0vYxkQKq3dzRp0V6pd8KYBOChMaWmud3e5WYTrowIfSlwCL8arCzXQrffX nJzorNLQxBGMWTnnOFYJ68t6oLMP0rpgwNwocTsqmQrEP5ga5/SPlGP1IKjaepAWb1L0 87FFxSPeFYYAGGtK9Vy0FBFezSkbfTmV0DTFqR4R1UV3bjBiUHfABorbuRPB5ndusEZT eNYL0Rzq7wNEX2QKAzdBFjlSKwQ/TiNI1Qv3AFZAyTsvUNiiC/Oggjf8Xcq8X0y2YkTD wauDC4lIswKGkuwqtG4ahH0aczGqFdCwZCzhdFo9oM7Z2MbuRU2uHRcr79FraOx9d7xX NPQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JQ0OTstwzXipk72lX8fvK3spe8ZEv2YAFM7sdltFU54=; b=pFZhwfO4JJaXc/Ko3kBqUWvd2IGA0aO5CodD0DiTNUJdyUR7vcFMcsMIdn2s60bj8R /8K2tNA9RL0iJBsnl/HIy/WYMYQk5ofifu54a7i8jFrb60IJ8t0WAPws/XwRkAD4staK bah221X4XgV+9mXBO0w+vb6VMvY4Ar92SeFdy0C9LbLHrpplZMlmMBdymG4gK78E/Nqg jxQ4FxEhcuypKYXjQASFSByru8birZsBd1u/Wh2oePVh6X52EOLLqNF1bykZZx5kjXnl MeZa9TcWD1R2poM6mJZvvEmlVHmmTwMiWoVQhuOwoDX2jE6vQgNr4Cz/qXeoLyYe9dV/ SGdA== X-Gm-Message-State: AOAM533JgvMz/mhZvYmHFldtUFFzjlEp1JcL8R1jrit395I71ypOfitK 2iUPOWdqKKTDqbFsl6PJYLlQ/yUW7i3Ffw== X-Google-Smtp-Source: ABdhPJxkIHTLlIrnfc0PfGxVKlmYsgsR1VXA0r88c172xrSDPBQBIB4uLohA0bTO4AXzsKO6bcBVLA== X-Received: by 2002:adf:a1cd:: with SMTP id v13mr17583wrv.332.1619120349602; Thu, 22 Apr 2021 12:39:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v6 01/18] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Thu, 22 Apr 2021 21:38:45 +0200 Message-Id: <20210422193902.2644064-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c68bc3ba8af..9338e80aa4b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -580,18 +580,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -603,12 +593,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -617,17 +602,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..4dce35f832f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu, error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120356; cv=none; d=zohomail.com; s=zohoarc; b=FM4ZEgA2npVTsYkYsLp4+gxnZPtXOA7IMM31W8rZRRKp4R85Yt2pYUiaIoHPWeA6noi1igyM/JO9j4c2ztjinUfpKtwLkYdmBT/V6oNMRg9ByE/KB7xwiqn7fl4kDW9OrYgtVLQFDk3V46nUoFqr2moHgQuCU5X2cSWgHl0y1xw= ARC-Message-Signature: i=1; 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Tsirkin" Subject: [PATCH v6 02/18] cpu: Introduce cpu_virtio_is_big_endian() Date: Thu, 22 Apr 2021 21:38:46 +0200 Message-Id: <20210422193902.2644064-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Similarly to commit bf7663c4bd8 ("cpu: introduce CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method name to hint this handler shouldn't be called anywhere but from the virtio code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 9 +++++++++ hw/core/cpu.c | 8 ++++++-- hw/virtio/virtio.c | 4 +--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9338e80aa4b..08af2c383a5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -604,6 +604,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr ad= dr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ =20 /** diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 4dce35f832f..daaff56a79e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +bool cpu_virtio_is_big_endian(CPUState *cpu) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->virtio_is_big_endian) { + return cc->virtio_is_big_endian(cpu); + } return target_words_bigendian(); } =20 @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; - k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 07f4e60b309..8a364496fd5 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - CPUClass *cc =3D CPU_GET_CLASS(current_cpu); - - if (cc->virtio_is_big_endian(current_cpu)) { + if (cpu_virtio_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619120362; cv=none; d=zohomail.com; s=zohoarc; b=EoZG0Ayk0c3loycdYGqnPgLl8nKIDmCI5whhHzAOtU+e5GnL+ebnT7a/zrfev8K9NTVBzM9rxqqQCDvq12Q49Zy4DBGwY7LA4n5/dM8JFbqyOmm5Bx1nn/HX9srDiB2H2BkuY29OEWuEK71QHx6iiYYjywuhVbPvIMBM0pCdPaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120362; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J6YQeevinF+UxncXXirBs+TNeTtBEGxrSMPU7gVD3MU=; b=dgOPd+YVHrEbanUFgxBgOELYZnXE01t9njtzQY3X/MV13CWhUZhxnP5CN29s+gGD6fq6e4uct/fajEk2xO3WBISlEkBrOcNp3r5gKwfwMbslnBg1K3M1wVGdS1RgHD/JOV2LJrNLo9I3SvDDh/YxjFcg7HEa5IYw7hJ+HeHgn8U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1619120362814931.2310996212008; Thu, 22 Apr 2021 12:39:22 -0700 (PDT) Received: by mail-wm1-f42.google.com with SMTP id n10-20020a05600c4f8ab0290130f0d3cba3so4701557wmq.1 for ; Thu, 22 Apr 2021 12:39:22 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id c15sm5287828wrr.3.2021.04.22.12.39.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J6YQeevinF+UxncXXirBs+TNeTtBEGxrSMPU7gVD3MU=; b=R/moRZZ4c/y/LytyMN+wjV1mwDXDkhoT85uL0akSO41gWVv/C1vgmSDNZRwlyTLfde cOvNizbIUk/d6t5ZcJa1y8rNyl8aZ74AjJrbmHoYnahICZECo6Cu+lI0+DZ/nUXIPHVt YfQfFuTysTK2y1YPFhL0LVrP5tKrV9WWpuSPGrC/mX7FDOxA5T7waLP2REqFL0zTp1x2 IQylqtu3R7/1EILg1Gl1JOpln3KlnZVIfwj6z4sd7bMjNcGY0N/DPUyVyi++f+H4rixv duCFlWwe4l5qRlSOOZnaDoFP9LRtigOjHVVwuAu2zlk1sUAo54Pnc6UHYSPLWIZftjrO 6guQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J6YQeevinF+UxncXXirBs+TNeTtBEGxrSMPU7gVD3MU=; b=oUfJ4N6eGPXQoxrz+xwy7kZe62n3+DOIV1ZkFy6hUlroJc5RImYLdnv/97+Q5Q2viW gopXecVKpHErAVdy1TkHvE2/3Xn6c3sOObOI/73+XjbVzPMDzkIW2N5sQ1r1Vk7mG/JN WijiQ+P4OQlL6KcQpYRMZwSLyhJ6iog8C7alC3yfcMlTK5AzIIqrUYd3zQfSqe2B/WG3 BrNU2qrcvWkHfxb4Y5qw4keV0yXgauND+gN5m0EZt3qBCU2djtDKsz9gvNP5uBc1xBUv CFy07nJv2mjCvqX2jujejZhmBpTZ1wssOtodGjPB/nsypDb6z+HWUx59rVa2qN4xT3R4 tDAQ== X-Gm-Message-State: AOAM530VbBX7wGere5HmZsXCm6GahYf+0vEM5KakB8L2etPUCj/XjBgP GTSMsJtcTtCUG9dT+G+Sd50= X-Google-Smtp-Source: ABdhPJxItIbUjNhRpmmaJBQYrpeQf7tDHu/V9XV4sBbnuZw+wZyqong/VFrRstYleBeofBXfBdXplg== X-Received: by 2002:a1c:2857:: with SMTP id o84mr1650722wmo.181.1619120360024; Thu, 22 Apr 2021 12:39:20 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v6 03/18] cpu: Directly use cpu_write_elf*() fallback handlers in place Date: Thu, 22 Apr 2021 21:38:47 +0200 Message-Id: <20210422193902.2644064-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:440: k->write_elf32_qemunote =3D cpu_common_write_elf32_= qemunote; hw/core/cpu.c:441: k->write_elf32_note =3D cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote =3D cpu_common_write_elf64_= qemunote; hw/core/cpu.c:443: k->write_elf64_note =3D cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note =3D arm_cpu_write_elf64_no= te; target/arm/cpu.c:2305: cc->write_elf32_note =3D arm_cpu_write_elf32_no= te; target/i386/cpu.c:7425: cc->write_elf64_note =3D x86_cpu_write_elf64_n= ote; target/i386/cpu.c:7426: cc->write_elf64_qemunote =3D x86_cpu_write_elf= 64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note =3D x86_cpu_write_elf32_n= ote; target/i386/cpu.c:7428: cc->write_elf32_qemunote =3D x86_cpu_write_elf= 32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note =3D ppc64_= cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note =3D ppc32_= cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note =3D s390_cpu_write_elf64_= note; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 43 ++++++++++++------------------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index daaff56a79e..a9ee2c74ec5 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_qemunote) { + return 0; + } return (*cc->write_elf32_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_note) { + return -1; + } return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_qemunote) { + return 0; + } return (*cc->write_elf64_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_note) { + return -1; + } return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - - static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) { return 0; @@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; - k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; - k->write_elf32_note =3D cpu_common_write_elf32_note; - k->write_elf64_qemunote =3D cpu_common_write_elf64_qemunote; - k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120369; cv=none; d=zohomail.com; s=zohoarc; b=CjcTwYd2z2eUinJ+nNEiBWCi4o1vW6dfMCQdu+ptJu2kE7U/cT9Jch28qHpkpNJxanZvic0cq+INKH5Hr+ig/NChJrb421vMcxhzfmGky2GFRq9uXmKpw2lG7BeGo9CesYrK4v85Zj/tPDnTkv9el8n95PPFNI8z+MYuDZSk1E4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120369; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y73DhisXrZCkQN7S3qTtV5uihkPH6tpgdxs7MXvhbiA=; b=Lj3rhvjaadre/9D9VHQqYwHAvWhZDzVz5rE86K465xqHkE5R0er1ATleVnK0thUZw1Bugjf3LPVD2/Dia6KKqpEsmvxPmd8WaE/8VcLL53+5OHbG6c+S06qnxOuUyjGe7a3G6WUJCWktVRhGJm09ZrTPwoGiX3mu9qqexeMhxeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1619120369385755.9902958830453; Thu, 22 Apr 2021 12:39:29 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id x7so45908186wrw.10 for ; Thu, 22 Apr 2021 12:39:26 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id t63sm4692739wma.20.2021.04.22.12.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y73DhisXrZCkQN7S3qTtV5uihkPH6tpgdxs7MXvhbiA=; b=pNr6/qa9lboCYvjEvNJDtJja3LMS+tGT7vQRd5q/INNliVyvNJdkn9qs0WhikHDZoX /q0HTEfrk1K5sqZ/ohzb8Ebykx/okt5ycDLkSdQUnrcJyB2TGE8iByH+KJFDLMGyzVv4 sDqY/LXaR9DY2DiMZtPGTVThUbv94k0DweMctT6VLs5h1ovTQNJS4THqfVZxX8FulVQ/ LxRsxM7O6DBOEbMuvxurH36Q9bDuodTTZPWKLZkF/rvY9Qmdqsdj1BMDSjptNnhwGKMs 8guGPA8+yUyGlmctG4AvoSUh/yz8ZwEj5G16legaeE9i3+PaxaomFDgk87sKdmyVIpUI OFXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Y73DhisXrZCkQN7S3qTtV5uihkPH6tpgdxs7MXvhbiA=; b=QfClsNbDJniMoqZG+d9MCfxR/EM8lIlzQtwhR9yj4i3DKe9QDklwrciuKTdLszaa19 DGAb+Jtkdhp6Fd/dZpwJX+aJph82vAZPfUIuHqL6l+RFblwennlA7mYHGGEhqP6II3DN 8ib2f62xvKr2WD1spu6ldXiXc4ty0U2AWysaZrneUqSKLyXRtj4j9odOmLFelpgrwAPJ fPP6qhIEy0rbVD2c6wNt7U0O7YAeq9rcYuPIZnTZCWcleNbyOdwFRFgjtqg+5Vf2//Iq H7lP5/pCmaXOachRRN1+G1NWle+SK1df18ddIbTCIPartELr3PKGw7+sKt2tLt2gc6Pf dBNw== X-Gm-Message-State: AOAM531H87IynzkUvN4KMOGf0bqpZwnb2yxeTcIt3whgG6Ty4tyjOj+e 6aMbwCK5PaCK288BNfMNuIA= X-Google-Smtp-Source: ABdhPJwJEZM1S3DhwhbP1ayv2uAsUBBJscKSE5VW0fsRFool14C3rGlWC/j/SvKr8UxCkkrrVvLjvw== X-Received: by 2002:a05:6000:1567:: with SMTP id 7mr5486wrz.47.1619120365658; Thu, 22 Apr 2021 12:39:25 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v6 04/18] cpu: Directly use get_paging_enabled() fallback handlers in place Date: Thu, 22 Apr 2021 21:38:48 +0200 Message-Id: <20210422193902.2644064-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled =3D cpu_common_get_paging_ena= bled; target/i386/cpu.c:7418: cc->get_paging_enabled =3D x86_cpu_get_paging_= enabled; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index a9ee2c74ec5..1de00bbb474 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->get_paging_enabled(cpu); -} + if (cc->get_paging_enabled) { + return cc->get_paging_enabled(cpu); + } =20 -static bool cpu_common_get_paging_enabled(const CPUState *cpu) -{ return false; } =20 @@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120372; cv=none; d=zohomail.com; s=zohoarc; b=AcCReCzfVJr4uBbhPST8Gr2KlZCv9XVmyiS3TBBAvajCNlmvAOwitYRpHOn6keKrb973b8IU5524SnGoM1ezGDZSW/NO0jemS8vTjyp+ve6Sjk3CVhCYBWho2vtG0iJIHzVsiAmVc75aUMLuiEw5+yx3eqJeuCO9lwWDjauwAy0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120372; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AsKH3RYUFA9evmZE7qWhREuizy9iouUOsbLguH/0Dwo=; b=lrhhuqS/xOqSrm1hH2h4ZttSVPeMJkyFCsrnbW/8kLiR5jQVbf9Z3QYdCK3tubHcuLqSrqR3weCg1GyoZYR3um3DeicmH7DowbGEnDjuZWkgNxwe/FgNRItu4sf3hXMmL1opWtGpSJc/4nIAqef+yCyc3lca/McZDuY5TUFJMMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1619120372525523.5355192918107; Thu, 22 Apr 2021 12:39:32 -0700 (PDT) Received: by mail-wm1-f51.google.com with SMTP id o9-20020a1c41090000b029012c8dac9d47so3892155wma.1 for ; Thu, 22 Apr 2021 12:39:31 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id d10sm5168077wri.41.2021.04.22.12.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AsKH3RYUFA9evmZE7qWhREuizy9iouUOsbLguH/0Dwo=; b=c1otoi1WCXL6aNmuI6x5KXVJZOrEybgYc1TzaE25gCbJQKRm27GMyzgzjb2AYFrGFb mxZVVQiyEgzyrPF9vZ1wBXH1NlNBIy3uRymvro3LAaG1HTt36brCmIiE1ec+9GIUZgHV C2rt50wrYHSuh3C7TorkXFRyG+oi6ma1IOhpDmm755w1wK6Y5qvw33uDanUAOuC9fZvg y7JPK4w8uPq9yVn7TOu36zfhcwgE3sACA8NzCc2larv0WAjmPcma9BqJrDEgV5hi+9/D 6zvE/mt+6HGwz/Rg/z8IqZ5175pINYMvNNIpwlv2ToUesEfy9PyWwAZyYZVvKS26v60t VNyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AsKH3RYUFA9evmZE7qWhREuizy9iouUOsbLguH/0Dwo=; b=Qp/iXzJTCqulHA8uFv6ewmmyUMwkLKUj/9aeGFitUaIxqibtzlDcKu2iFrUCYTuy4U 0ufh0hd0icTslryblfCMIZOzByYr+/OOLbAjx2+30ycIK1fcCZxASLzJ6UvFs8iYLY9M mclaGsLsSENnvTraT1L/GgBXAnUD3Ht6wMa0UgnzPezsbGxLz3V3xW4Fh8ptfT+Ar9QY vfHyrmEW+b+nhh0kUPG2zxeEMvO1QvQQGHfR15fjBOpVyp4Iqnj0YtoknO6A8io9x7Cs zozFqeyH5OgTb8cWPAu5gJU2lppdteyNl0IEJEsc+14KNtEhW1/R+8G245KZmBkBx0Ux jIwg== X-Gm-Message-State: AOAM530/b35NkQqmxYpxpyLYLfiOs2YJVANwvcehssuYHPR3ajpC/dZu e3hDPE5xDJMRJIRLYHq5EGU= X-Google-Smtp-Source: ABdhPJxuKKgioOw/Ijp+w6NdSrrFnSOogH9XGu3pGAxKm7eRkzIJ/hI7iQ6RzIMA/+3ZMHVf25qo+w== X-Received: by 2002:a7b:ce09:: with SMTP id m9mr382732wmc.150.1619120370730; Thu, 22 Apr 2021 12:39:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v6 05/18] cpu: Directly use get_memory_mapping() fallback handlers in place Date: Thu, 22 Apr 2021 21:38:49 +0200 Message-Id: <20210422193902.2644064-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping =3D cpu_common_get_memory_map= ping; target/i386/cpu.c:7422: cc->get_memory_mapping =3D x86_cpu_get_memory_= mapping; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1de00bbb474..5abf8bed2e4 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappin= gList *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->get_memory_mapping(cpu, list, errp); -} + if (cc->get_memory_mapping) { + cc->get_memory_mapping(cpu, list, errp); + return; + } =20 -static void cpu_common_get_memory_mapping(CPUState *cpu, - MemoryMappingList *list, - Error **errp) -{ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 @@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120377; cv=none; d=zohomail.com; s=zohoarc; b=YlQ8frFrRRbtW892G2DV20WT/i0KDHrJd+hDueiPD5uTe5DzohpSkFAIYsVryFG3dBEpWVom4kZiCseIZronLKOu9RFhUJj5g/E1lO32C56uBrGrwrbTI8C6RIy5qjsbBxB7lXjLImRbT8DnmILJkJNESKz9iQpjzc5BVR5+jcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120377; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kR/07YuyIEQWuHZD87qpk3O+O1bGxZyn441vbmFYrqk=; b=PBXc3isegFv3gCuqfisi/ma9QiTWADK7I1NWMoKhYZxkSzAMMp24EMCDnkyq+qvqjyEHdgtu6RnDBpmICZV9RxUZxRrQ74mmmwlqBaalbfwNPqEeYW1qAbRvJTTV4COQRTzlKQ/rqSS3igsPfEnJrkvLq+QlZlyb+dOxgcdbgHk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.zohomail.com with SMTPS id 1619120377704130.1286985663437; Thu, 22 Apr 2021 12:39:37 -0700 (PDT) Received: by mail-wm1-f41.google.com with SMTP id y5-20020a05600c3645b0290132b13aaa3bso1026wmq.1 for ; Thu, 22 Apr 2021 12:39:37 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id s14sm5052614wrm.51.2021.04.22.12.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kR/07YuyIEQWuHZD87qpk3O+O1bGxZyn441vbmFYrqk=; b=B61HVxiHPvc2L1Q3rWC05ArMLEC43GpyOd0QNbmsgh0jYMsLaJgyRnSufjZCxpCZfc QeaDb5jYj1O4HVDDsPP0FyykEPfXuebljtGPmWaZZpNPdg1zPlQXSPLne8wo5g+rhgqL MSxc6R2OuWrGvoRkhmaLycS9PYT6d2EUF5jdtBJKfPt+nWNHjKHav8DKAXHzTGAnWvBX vly7gcCrJDfF5HdaQ3Hwbqt+Fr+1KmHeaWSJCGtdlY68hzmwF0VzTJkD0K1/dHPMv69R BL4NPQNRM0xwuG0m0vgDrK75saORy2Og6N6BaBWsgI3u+ag3JoaGI6cpC8Fc8qakhxxl m6pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kR/07YuyIEQWuHZD87qpk3O+O1bGxZyn441vbmFYrqk=; b=HujokbXWfjQ3rIXhirgyQc/XeFjRbVHyZYY1S41VAl4Ondtp9cdKsZwwaJq9JELGl8 fQfh7pVPq8Fhm6+DZZVboe7KObeCfef6uiRG5/WaP39yGCjzcR8SxS3gz3nQ10H+v3vk AWAcxtyZZPGrf9JJYEz3gbesP8l9Ajfjq02PO6k84n/uNxpG6xLpfIgQG8lJ6CUTcsTj I15a/T0lToULNDUYIFNUPv4NXwiWgF1rsRcyolh1AmNpq2yGR+H65xmPFgEgOWz5GUQd 8dlyYAttkCPrU3/ui/zpp3nv0+paRHYRTa5ljzbQfZJa6n+Xo6DPAymPdTvv7T88JyAR MH/Q== X-Gm-Message-State: AOAM530VAUeLEBQybk/CmIR8Zrwy0jVgf+jmnZnIMYQSkP0ZVAcch8Iz FUHUFqwapXPHqh5IT1WQnvY= X-Google-Smtp-Source: ABdhPJzk+c0E3j8WXodKdxjcpUdgd3h2Ptl8ACAVLC1Zse3Q3pZjVjVabU66yn5XYMaQ5ZckFQVqrg== X-Received: by 2002:a7b:c7c8:: with SMTP id z8mr1754764wmk.112.1619120375904; Thu, 22 Apr 2021 12:39:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yoshinori Sato , Guan Xuetao , Max Filippov Subject: [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation Date: Thu, 22 Apr 2021 21:38:50 +0200 Message-Id: <20210422193902.2644064-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry, and assert in cpu_exec_realizefn() that dc->vmsd not set under user emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- cpu.c | 1 + target/sh4/cpu.c | 5 +++-- target/unicore32/cpu.c | 4 ++++ target/xtensa/cpu.c | 4 +++- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/cpu.c b/cpu.c index bfbe5a66f95..4fed04219df 100644 --- a/cpu.c +++ b/cpu.c @@ -138,6 +138,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) #endif /* CONFIG_TCG */ =20 #ifdef CONFIG_USER_ONLY + assert(qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL); assert(cc->vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..35d4251aaf3 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail =3D &(env->movcal_backup); } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; +#endif =20 #include "hw/core/tcg-cpu-ops.h" =20 @@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_sh_cpu; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 59; - - dc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..a74ac7b6140 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -115,10 +115,12 @@ static void uc32_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_uc32_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; +#endif =20 #include "hw/core/tcg-cpu-ops.h" =20 @@ -146,7 +148,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; +#ifndef CONFIG_USER_ONLY dc->vmsd =3D &vmstate_uc32_cpu; +#endif cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..a66527e2d45 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -176,10 +176,12 @@ static void xtensa_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; +#endif =20 #include "hw/core/tcg-cpu-ops.h" =20 @@ -216,9 +218,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_xtensa_cpu; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619120383; cv=none; d=zohomail.com; s=zohoarc; b=n2N3kIrtf7mVgrr1OJG2DQO8L/4iOOssQypOosWgPyYrE2TGQOU9tavE+We5lfGQjDpUvQCIFlJQu0n/UBc2V9OP7eA5FJq8V7F1hGB4VLi7qv0x0Y0wKkYoWo16tXE9UJh3hWq86NHhYtUz3kh+Kh65sAktddyiwWoff7hZI54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120383; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BMW/DG33xhlbjWUsaqVzUdZIFTJ6NXEk+Ef5RupUShU=; b=gzdtOVU/ozicFCF/tZL9jbVhW0EpiC/Cvi6TfAfy81Lz4LZKwq3YK8T59TDySs6S17+AMJ/GECgzHbwsFAZx0dpEAUyx4Jr6t6GbbG3nC6wH2Mx5JtqZY20LKBzEI7LqULek6Ufd2xsh5KiaComUBR+oP7QjSAla/vVCWxz+BgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.zohomail.com with SMTPS id 1619120383615260.6110543130641; Thu, 22 Apr 2021 12:39:43 -0700 (PDT) Received: by mail-wm1-f47.google.com with SMTP id w7-20020a1cdf070000b0290125f388fb34so3915032wmg.0 for ; Thu, 22 Apr 2021 12:39:43 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id i15sm5484288wru.12.2021.04.22.12.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BMW/DG33xhlbjWUsaqVzUdZIFTJ6NXEk+Ef5RupUShU=; b=o8nhOKlI3i0SGPgQwrz9Acu7N4pDw4huGjb0uwmRYD+KbeTP7l2+/nd2R858dhai0G ILRyNhPefSKsUBTlkd3+EQK/EqDpjKY/yUa1B/7OkJe5zcD9qJ1vVSYa52NtP3dIGqRr kXm/maQvl7TQuliMPFWeNLvQv/EhRsg+46K186UYchlVa28d+xssszg9B57LwallOqAC DiuBJj1Z1ACVe6sIvcf8EMGwQSWiFQEIypinrqDZ6CgxzWaW0J/tdHsww6EP+xD07E9N +BEsM4cQCfyzTKlP7vXVcxCnZmDpICWkq+lFXHMs29+pOcStQCDT5XLR1zAVQPQR7x5T JouQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BMW/DG33xhlbjWUsaqVzUdZIFTJ6NXEk+Ef5RupUShU=; b=hWpcWGNJoIs44Aaypu0cAlWKS/qrvA8Vqs89iPs0O70aCGR3k9Awjd6TkbUK539Pex iLUZu5ADPqC7WMalc23l38umRuRAJmaDB2+rCWikm1r4P2pCS1wt8BdL4q8NicgR+ZqS J7ymh+U/JjB8iyGVWmiEFZZnslz86EBKg1NTB8H9K2TXjroyuXCv6THUwQUwsT+89+P5 o1ZbMRbT8CElviRNQ9yFF36hUqGdK3gun0dQsIJjbT/SK9wnIJ7JPU72Ch08z7aZWbcV vuZIyCzbnHrWwwrDTA4M1hDsO0hllP8ys7dZZHw4UChOOQ3KZQQLO2MbmaWGEn3CFI+q UnVw== X-Gm-Message-State: AOAM530xkf1GBKknwmnsYxyAoR+CyNu62DURzWAOazAMu2sTK5vEOoM9 /AlgG6zU7AhzZg8xOO8IlNA= X-Google-Smtp-Source: ABdhPJxQHShL/+nWoSsA7zxzCAhXLCp5WRpyNAyj+fZlD6eec/uFLDDTeStLIjPGsl1CFUjxNEXrpA== X-Received: by 2002:a7b:c012:: with SMTP id c18mr1734447wmb.94.1619120381709; Thu, 22 Apr 2021 12:39:41 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Michael Rolnik , Paolo Bonzini , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd Date: Thu, 22 Apr 2021 21:38:51 +0200 Message-Id: <20210422193902.2644064-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Quoting Peter Maydell [*]: There are two ways to handle migration for a CPU object: (1) like any other device, so it has a dc->vmsd that covers migration for the whole object. As usual for objects that are a subclass of a parent that has state, the first entry in the VMStateDescription field list is VMSTATE_CPU(), which migrates the cpu_common fields, followed by whatever the CPU's own migration fields are. (2) a backwards-compatible mechanism for CPUs that were originally migrated using manual "write fields to the migration stream structures". The on-the-wire migration format for those is based on the 'env' pointer (which isn't a QOM object), and the cpu_common part of the migration data is elsewhere. cpu_exec_realizefn() handles both possibilities: * for type 1, dc->vmsd is set and cc->vmsd is not, so cpu_exec_realizefn() does nothing, and the standard "register dc->vmsd for a device" code does everything needed * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common directly to handle the cpu-common fields, and the cc->vmsd to handle the per-CPU stuff You can't change a CPU from one type to the other without breaking migration compatibility, which is why some guest architectures are stuck on the cc->vmsd form. New targets should use dc->vmsd. To avoid new targets to start using type (2), rename cc->vmsd as cc->legacy_vmsd. The correct field to implement is dc->vmsd (the DeviceClass one). See also commit b170fce3dd0 ("cpu: Register VMStateDescription through CPUState") for historic background. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html Cc: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 5 +++-- cpu.c | 12 ++++++------ target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 12 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 08af2c383a5..10dd16531ba 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -122,7 +122,8 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. + * @legacy_vmsd: Legacy state description for migration. + * Do not use in new targets, use #DeviceClass::vmsd instead. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -177,7 +178,7 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; + const VMStateDescription *legacy_vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/cpu.c b/cpu.c index 4fed04219df..c1c9cdebc3e 100644 --- a/cpu.c +++ b/cpu.c @@ -139,13 +139,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) =20 #ifdef CONFIG_USER_ONLY assert(qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL); - assert(cc->vmsd =3D=3D NULL); + assert(cc->legacy_vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } @@ -155,10 +155,10 @@ void cpu_exec_unrealizefn(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 #ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); + assert(cc->legacy_vmsd =3D=3D NULL); #else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->legacy_vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->legacy_vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0dd623e5909..3062e8c702e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1982,7 +1982,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; + cc->legacy_vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..37a8ebcc86f 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; + cc->legacy_vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ad99cad0e7c..f85ae518dd4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7431,7 +7431,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; + cc->legacy_vmsd =3D &vmstate_x86_cpu; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..c0388142528 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_lm32_cpu; + cc->legacy_vmsd =3D &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bde..11604954504 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -720,7 +720,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; + cc->legacy_vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..3c81a088eaa 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_moxie_cpu; + cc->legacy_vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->tcg_ops =3D &moxie_tcg_ops; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b6..70be7e8287a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -624,7 +624,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ - cc->vmsd =3D &vmstate_riscv_cpu; + cc->legacy_vmsd =3D &vmstate_riscv_cpu; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..197c4b87f30 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -517,7 +517,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; + cc->legacy_vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; #endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..ba497561bfa 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; + cc->legacy_vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index c03a7c4f526..110a68a867e 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10920,7 +10920,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id l9sm5256228wrz.7.2021.04.22.12.39.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A0SewrfFia3MN/Y1Mrlk9GQqVPEPPPTWV4cIuNY98mI=; b=XvIfzh9s4D3rNvJhfhGz6qxDpz1QQYKnKaq5uUTj+X2t6H17sXF0dvUn5WpZDGJfIU yVoW2W7Rgk3fIOZ5jpxx0XluMOW3COULK7P/NMabvOjvUsBzQrWH9RqNubRy0FosQMd4 /sJcxnRP+M9wVpXowIdaJMKoIfFXfmGgykrBzWKaZ5P45a+kpsJN0ZQMZNLcTsovIebB u44U0DPboGnNVSIfmJrdmr+PfqieIqtDQxrgX99pFKTUpcNWZGcNJm8ODL/wEHvQal/3 Z2nUYbR3vGadI52ah6baO2Gd8L4LQpLAqX/6NU/5MZhFxRleiVq/abNW28GQBqBV3GRh lcHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=A0SewrfFia3MN/Y1Mrlk9GQqVPEPPPTWV4cIuNY98mI=; b=T4ZzsPbosAPlh1t4wIBYPEArZEcJLOT7YV+AgIClQpTDCv0maVspLAjIizMCzQlSs7 ATfVaNuDK1lBSoSaB43kNttK+1siYWnNbZEcdEMu9NoKoLF6RePuzCwdzP6H2DqPC6Dh ZaVtGO8tPKVRqyeQNAQX74Y2wtZ3N81zkheAe0/3UXVSfaZ6iXDjJUksWlptGOiiWhb3 xD4Ls6AgVGBkqK8iNZTx/Q397AaC5Rws4xpVdNP6MrpmozvEDbhetY4FHHF1a+EftrDp I0APfw8kZPt1lxGCsfV4VelDw+DhhBve+nETbsnQp7bKJwJNyOsUYHvKA5cjlf0OKEr6 hGGQ== X-Gm-Message-State: AOAM530HwMFhyhMrhmd861Vrwk/CQz8iwnx38oaUuMPcLA1nZ/24NZCS 3P296fS+s01B58SbuqcdOM8= X-Google-Smtp-Source: ABdhPJzp2UUVNaX5pMQpfMuNrFnNcC60VYSIrLYYeKrMHteHYRUXryfs92M8dfHvYlH0RL6TY/2dQw== X-Received: by 2002:adf:f504:: with SMTP id q4mr21359wro.304.1619120386990; Thu, 22 Apr 2021 12:39:46 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Rolnik , Michael Walle , Anthony Green Subject: [PATCH v6 08/18] cpu/{avr,lm32,moxie}: Set DeviceClass vmsd field (not CPUClass one) Date: Thu, 22 Apr 2021 21:38:52 +0200 Message-Id: <20210422193902.2644064-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) See rationale in previous commit. Targets should use the vmsd field of DeviceClass, not CPUClass. As migration is not important on the avr/lm32/moxie targets, break the migration compatibility and set the DeviceClass vmsd field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/moxie/cpu.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 37a8ebcc86f..3353bcb9fc7 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vms_avr_cpu; + dc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c0388142528..e27c1a8bc97 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_lm32_cpu; + dc->vmsd =3D &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 3c81a088eaa..e5da3fa3f17 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_moxie_cpu; + dc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->tcg_ops =3D &moxie_tcg_ops; --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120398; cv=none; d=zohomail.com; s=zohoarc; b=eNFfrKFdXdB0sFAv6jHIpG30NUFSz6MHIaIgZz7fF3+GH2UpsdxjFlnCzC0hKT7scljAtl1yMimp+a90ZR2ZzCUSqhKszkDlg1BkTGHbepoA+KSOJrbRKdNJ10jEhvZiuKJ3F65sD7zjO8xwJjSRPR3LsRe/8P45C1+/hgDB5ko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120398; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a4MHO0sAjPu1j4vS2GRsLm7Hf4W1jjvtSticZ+mNDUM=; b=WzYT/OhEsAnkka+vvPSEOC6Qp8gxDVKzpK2Hbddf5r7C968V+0zIFD/6hyRNUKxa2HDtC17h1gG0Ffa5ezwi9pRHQJxS0iYGd2DckT4DU5lRbGiRZflr2kPoTw64bAsi7pjh9o84cpDor2NQIQ4SITLMwj0K84GSHlvq0eYS6io= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1619120398359843.1644498918049; Thu, 22 Apr 2021 12:39:58 -0700 (PDT) Received: by mail-wm1-f50.google.com with SMTP id n127so12925184wmb.5 for ; Thu, 22 Apr 2021 12:39:54 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l20sm5301995wmg.33.2021.04.22.12.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a4MHO0sAjPu1j4vS2GRsLm7Hf4W1jjvtSticZ+mNDUM=; b=GTu0e8Bp5+vhPuJIJuFaWMmWUuY/lzxngtTQlH5X4oI/JxEVWg/81/XYiS2rvU7Yo0 nmhsXkIddVrk0b+upIMOBDABjrGrQy5i6rq8icy4VRWAfYvq9mjL5pCtj3TESyyQvhB7 a/2xrfixQPjVN1Gs4hG9ziy+1gxdMW8QwPYnfEVzOEp3Csl97J1JGZ3h5JbU+/eWMqLP xcfDjeeFszmS8GOGaG6gaF5NGlDFhk1hyTt8D66DAt/PsoqDQsFyL69rv4fFTFuCJ5Cs ibs7GfGhthCrQv3HST/6v35i2+kf+G1krzvwHpqLUsxU9KGZF1Xl8K3gbHCkXw1YwfMd aLww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=a4MHO0sAjPu1j4vS2GRsLm7Hf4W1jjvtSticZ+mNDUM=; b=sWiWje/0tTo+Xk5S219ZLlwm3QIPNH3LAkvYuWxUV3pE5O8MKxdTQQGhVVCPFvwThT XR4O+9VElQmXXIKlXGCmHHXxwcZkxd9c+qY8pMGWvPWmknNpZ0SP6zNAQwLLOqHZkfvK JNh+3izRTMX8LVlY3BtFCsmRJ5kSqr7gmzPKlMBjWZb/x/Y88f0xDFMj7mOeaph1iN9C clGB6yKaupuz94L46h01YVvmWW/f5cD81fdij+GZ369paM/EIixena1qkIS5he6M0zVT DIEuIUkbOvupkBqte/fKyZaxfqH+y35cS/JIfZo5lh8p7QvJjqMBi1IoxpiPPO9GhTQy IlDg== X-Gm-Message-State: AOAM533c0acPdWE4l2HQiNXHJYbU/le9DAEWy1oBaiSjtU3PQDuhshab dyy0NP2Se2CvrlTY8XgZ3HQ= X-Google-Smtp-Source: ABdhPJwUXM2nwf483lvZxNNIPwtwMBwSGDA0CTGAAAZnQZm5GJ+cTcLaXbfYuaJV12+/LUoQk6zAcg== X-Received: by 2002:a7b:c30e:: with SMTP id k14mr1710332wmj.128.1619120393221; Thu, 22 Apr 2021 12:39:53 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Michael Rolnik , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , Cornelia Huck , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v6 09/18] cpu: Introduce SysemuCPUOps structure Date: Thu, 22 Apr 2021 21:38:53 +0200 Message-Id: <20210422193902.2644064-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce a structure to hold handler specific to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +++++ include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++ target/alpha/cpu.c | 6 ++++++ target/arm/cpu.c | 6 ++++++ target/avr/cpu.c | 4 ++++ target/cris/cpu.c | 6 ++++++ target/hppa/cpu.c | 6 ++++++ target/i386/cpu.c | 6 ++++++ target/lm32/cpu.c | 6 ++++++ target/m68k/cpu.c | 6 ++++++ target/microblaze/cpu.c | 6 ++++++ target/mips/cpu.c | 6 ++++++ target/moxie/cpu.c | 4 ++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 6 ++++++ target/riscv/cpu.c | 6 ++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 6 ++++++ target/sh4/cpu.c | 4 ++++ target/sparc/cpu.c | 6 ++++++ target/tricore/cpu.c | 4 ++++ target/unicore32/cpu.c | 4 ++++ target/xtensa/cpu.c | 4 ++++ target/ppc/translate_init.c.inc | 6 ++++++ 24 files changed, 148 insertions(+) create mode 100644 include/hw/core/sysemu-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 10dd16531ba..23b718a4a51 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 +#include "hw/core/sysemu-cpu-ops.h" + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -191,6 +193,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; }; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h new file mode 100644 index 00000000000..e54a08ea25e --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..cd01d34d92f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps alpha_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps alpha_tcg_ops =3D { @@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; + cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3062e8c702e..c1943194cf1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1943,6 +1943,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps arm_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, @@ -1986,6 +1991,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; + cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3353bcb9fc7..5c8bb9b3fec 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) qemu_fprintf(f, "\n"); } =20 +static const struct SysemuCPUOps avr_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps avr_tcg_ops =3D { @@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; dc->vmsd =3D &vms_avr_cpu; + cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..394df655c9f 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps cris_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps crisv10_tcg_ops =3D { @@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; + cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..6605c42e509 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps hppa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps hppa_tcg_ops =3D { @@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; + cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f85ae518dd4..0920eeef1e7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7391,6 +7391,11 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps i386_sysemu_ops =3D { +}; +#endif + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -7432,6 +7437,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->legacy_vmsd =3D &vmstate_x86_cpu; + cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index e27c1a8bc97..2b40f2b2559 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps lm32_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps lm32_tcg_ops =3D { @@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_lm32_cpu; + cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index a14874b4da2..600812d682b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -503,6 +503,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }; #endif =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps m68k_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps m68k_tcg_ops =3D { @@ -535,6 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; + cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..c6a10b1a52b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *c= pu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mb_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps mb_tcg_ops =3D { @@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; + cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 11604954504..0bbaff3b57a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -680,6 +680,11 @@ static Property mips_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mips_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_mips_cpu; + cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index e5da3fa3f17..e7bf5298c67 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) return oc; } =20 +static const struct SysemuCPUOps moxie_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps moxie_tcg_ops =3D { @@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) dc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; + cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; } =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..296ccc0ed3c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,11 @@ static Property nios2_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps nios2_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps nios2_tcg_ops =3D { @@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..cd8e3ae6754 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps openrisc_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps openrisc_tcg_ops =3D { @@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; + cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70be7e8287a..c465695f00d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -581,6 +581,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState = *cs, const char *xmlname) return NULL; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps riscv_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps riscv_tcg_ops =3D { @@ -625,6 +630,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->legacy_vmsd =3D &vmstate_riscv_cpu; + cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..bbee1cb913f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps rx_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps rx_tcg_ops =3D { @@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 +#ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &rx_sysemu_ops; +#endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 197c4b87f30..7503b9e0c8b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps s390_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->legacy_vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; + cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 35d4251aaf3..85e15ec9954 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -223,6 +223,9 @@ static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; + +static const struct SysemuCPUOps sh4_sysemu_ops =3D { +}; #endif =20 #include "hw/core/tcg-cpu-ops.h" @@ -259,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &sh4_sysemu_ops; dc->vmsd =3D &vmstate_sh_cpu; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ba497561bfa..743a7287a4f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sparc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_sparc_cpu; + cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..8865fa18fce 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const struct SysemuCPUOps tricore_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps tricore_tcg_ops =3D { @@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index a74ac7b6140..60ae917f0ee 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; + +static const struct SysemuCPUOps uc32_sysemu_ops =3D { +}; #endif =20 #include "hw/core/tcg-cpu-ops.h" @@ -149,6 +152,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &uc32_sysemu_ops; dc->vmsd =3D &vmstate_uc32_cpu; #endif cc->tcg_ops =3D &uc32_tcg_ops; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a66527e2d45..d0bf06696e4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,9 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; + +static const struct SysemuCPUOps xtensa_sysemu_ops =3D { +}; #endif =20 #include "hw/core/tcg-cpu-ops.h" @@ -217,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &xtensa_sysemu_ops; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_xtensa_cpu; #endif diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 110a68a867e..b15abc36851 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10878,6 +10878,11 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps ppc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -10921,6 +10926,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_ppc_cpu; + cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120400; cv=none; d=zohomail.com; s=zohoarc; b=KMJjOGZ3k4cExVtEWf3XnJ2MLcA3egxIKlY9J+FaHEdO4O2UK7saownjmGSAEGvsmFbhmm+8ngJ9IVj9I0a6MWcKZ+3DVaJebv2O05OaIZWYCjPbZdSP5r7Qh0du8NHGDFtEfhGfGHZZp/6d5Hf8Y1gSvJ4ezvszDkZ/Blzxr5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120400; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id b15sm7470096wmj.46.2021.04.22.12.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:39:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=geK1FL9BfBSzKYrYLCYKzr+Rs4N62lLrBU0a9dBAM/U=; b=Nl0YtqttuvNibxtHdC7V16eAWQoec2etPKOGpgf9XnFgw4C678GtTngNMKIiTzwgeM ysjbRL7zNSX6Mk8+DWxFHffkkxUu+K6Y5zGdqNG9NK+BEKz0moFkflHLHCEVKnHSBjlV J6PjIko6hwiH3QjaagwQlhPran8zaVizTmdu2qCHxcuiObrJ9lg1jyW/x7+MZIGQJUZ3 SGq5kDTu5Ae7Z66ZqVZGy/2FgzqXhVt6i9hG6okcxh2hxdCaztx2pGs2EmEnyOO2UbvR pkYat6iuR7BxCV2wPNqHTGS+d/HIJihSOs7ryrq8mwsDZnENloiskjiahSQ3aReyY0iQ 4QFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=geK1FL9BfBSzKYrYLCYKzr+Rs4N62lLrBU0a9dBAM/U=; b=QTH6zNAcO4df78w2xmfxD2/iGyAts7gsQEFymsJ8iJ4348XC/S525awR2/RS3PJ3aT vMw+T8Ajf8IBCWeMI7vztOWmzeetVd07FugYyDnW8+rqCJttrn0+02Nc0gRo8EkHOsaS I5Ib27gCxue8pq6plJ2bH69fNQ3SI8IpZ/c+gNMCwOihJQmMD2rFUPnHtFe5MuZwwBKf qcQ6R3Ovv2PVhogd2f1ExdsgKsk6yxaQynGkP2UeNtNw8h6j2JV9z1I6NHGeKxbX8M6G 2x8eYiC30xYpmnaTCBIIO8tU6GuIAf5pHwjoC40Klz4NrIDKPtk7+FYmb/TT0/VpzFkr Fsvw== X-Gm-Message-State: AOAM532P1AUVhcDptmStQE17/ciyg97ouWnadwthOTcWPF/UZxY2IiNZ 5kQTLfiA1ZsU5LbVDWhgn5U= X-Google-Smtp-Source: ABdhPJwYdZr7z0HYSrTBAyjxzjX0b+lskkju9d4QCTNNev0Yk05gG/E4yHj5mgdsQlFlN3Ae2OAzdw== X-Received: by 2002:a5d:6487:: with SMTP id o7mr36460wri.152.1619120398751; Thu, 22 Apr 2021 12:39:58 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps Date: Thu, 22 Apr 2021 21:38:54 +0200 Message-Id: <20210422193902.2644064-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. - Move the CPUClass::vmsd field to SysemuCPUOps, - restrict VMSTATE_CPU() macro to sysemu, - vmstate_dummy is now unused, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Since v3: Merged in patch 1 (Eduardo) therefore removed Richard R-b. 'vmsd' is not a 'system operation' prototype but a const pointer field, so it belongs to a const structure, but maybe this structure could be better named than SysemuCPUOps? This field comes from: commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4 Author: Andreas F=C3=A4rber Date: Sun Jan 20 20:23:22 2013 +0100 cpu: Register VMStateDescription through CPUState In comparison to DeviceClass::vmsd, CPU VMState is split in two, "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1. Therefore add a CPU-specific CPUClass::vmsd field. Unlike the legacy CPUArchState registration, rather register CPUState. --- include/hw/core/cpu.h | 8 ++------ include/hw/core/sysemu-cpu-ops.h | 5 +++++ include/migration/vmstate.h | 2 -- cpu.c | 15 +++++++-------- stubs/vmstate.c | 2 -- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/riscv/cpu.c | 4 ++-- target/s390x/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 12 files changed, 22 insertions(+), 26 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 23b718a4a51..bdc702894bf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,8 +124,6 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @legacy_vmsd: Legacy state description for migration. - * Do not use in new targets, use #DeviceClass::vmsd instead. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -180,7 +178,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *legacy_vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); @@ -1058,10 +1055,8 @@ bool target_words_bigendian(void); #ifdef NEED_CPU_H =20 #ifdef CONFIG_SOFTMMU + extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy -#endif =20 #define VMSTATE_CPU() { = \ .name =3D "parent_obj", = \ @@ -1070,6 +1065,7 @@ extern const VMStateDescription vmstate_cpu_common; .flags =3D VMS_STRUCT, = \ .offset =3D 0, = \ } +#endif /* CONFIG_SOFTMMU */ =20 #endif /* NEED_CPU_H */ =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e54a08ea25e..a10d9fbdd16 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @legacy_vmsd: Legacy state for migration. + * Do not use in new targets, use #DeviceClass::vmsd ins= tead. + */ + const VMStateDescription *legacy_vmsd; } SysemuCPUOps; =20 #endif /* SYSEMU_CPU_OPS_H */ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 075ee800960..8df7b69f389 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,8 +194,6 @@ struct VMStateDescription { const VMStateDescription **subsections; }; =20 -extern const VMStateDescription vmstate_dummy; - extern const VMStateInfo vmstate_info_bool; =20 extern const VMStateInfo vmstate_info_int8; diff --git a/cpu.c b/cpu.c index c1c9cdebc3e..47eb8c40775 100644 --- a/cpu.c +++ b/cpu.c @@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); +#endif =20 cpu_list_add(cpu); =20 @@ -139,26 +141,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) =20 #ifdef CONFIG_USER_ONLY assert(qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL); - assert(cc->legacy_vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->legacy_vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu); + if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd= , cpu); } #endif /* CONFIG_USER_ONLY */ } =20 void cpu_exec_unrealizefn(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 -#ifdef CONFIG_USER_ONLY - assert(cc->legacy_vmsd =3D=3D NULL); -#else - if (cc->legacy_vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->legacy_vmsd, cpu); + if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/stubs/vmstate.c b/stubs/vmstate.c index cc4fe41dfc2..8513d9204e4 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,8 +1,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" =20 -const VMStateDescription vmstate_dummy =3D {}; - int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c1943194cf1..9b598bf10a8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_arm_cpu, }; #endif =20 @@ -1987,7 +1988,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->legacy_vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0920eeef1e7..eb96dd42556 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif =20 @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->legacy_vmsd =3D &vmstate_x86_cpu; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0bbaff3b57a..4023d487669 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_mips_cpu, }; #endif =20 @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_mips_cpu; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c465695f00d..5514e23c1d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + /* For now, mark unmigratable: */ + .legacy_vmsd =3D &vmstate_riscv_cpu, }; #endif =20 @@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->legacy_vmsd =3D &vmstate_riscv_cpu; cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7503b9e0c8b..131e7dfdf82 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_s390_cpu, }; #endif =20 @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 743a7287a4f..543853c24dc 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_sparc_cpu, }; #endif =20 @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_sparc_cpu; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index b15abc36851..e3f2f2fefa3 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_ppc_cpu, }; #endif =20 @@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_ppc_cpu; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.3 From nobody Sun Jun 9 01:22:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120405; cv=none; d=zohomail.com; s=zohoarc; b=O9hBjJwdi0TtCGtaxY2pPoRT2hw9EQ4JqlJEsM5+J3UqI4zT/FAGTE/Ihk3yuGiJxdZKylNcPNruwW/SSmAKYN1sBK/AUBQx7+Vi19il27FMSi7f6qEv+Oh0lvbYNoTxZduVbarZpufFs3c9l3J90yLK/3dsRBUw/bSZNj1sdaI= ARC-Message-Signature: i=1; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id t20sm7400937wmi.35.2021.04.22.12.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A7inHjxFSKegRWGQqqs5t49oYCgVN7h+qmqFdyyUm4Q=; b=QM8MVmniMaHl+Smm4+9C6OMCS1gKU8GkwU7VJFvD5hxpjWTyMbyrrKuCOkOtAaSw1l qiSw0qkbSs9cyshkROaR54VRAkCdd9gd2dtde29XeksJEGTtEStk95K8P8ZGPSTnVQJ8 l1iWlSb4StayRAoSKy1hRCAe/6ZXoI9XxrV3tjPOvKbLT+hYK2BmFUdNKo8KcU5pfn/N wuOZ31Wodcv6aTxceD+ipbYd1oNDo2wXtnmpdhJCOi535KYqAhaZmHiBW3x4+tpG3yWr yZOtc2exog/pSZvkmSCUIq0IojG+DYB1cqFOf4QvMcYzihiuboqRq4whbZ/3VLVuXnau VKvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=A7inHjxFSKegRWGQqqs5t49oYCgVN7h+qmqFdyyUm4Q=; b=W44GfWqMyjYfR10CKvKBGQ6TDWG12yfXCYocdG7+gxkh/VNR8RK5pdvQXPyzX33zN7 sBtvs7Z+1vKP6r8PQEEGL1CHdPZFIUZ4KP9za/Y+PPHAe9aXQM1pFuCS2lL/dfQ6Gevv 3FCtehFy5BXsIspx8SdYOSCd17uKHhvO4y6qPv56eILRVaRoOK+1IZdm+fkAEcpVDqV+ AxWuwvqIiEon7tgoSAS977c4g8NTuby/OvkedXNEOic/G039QruHIJQuibq0SGouYQb0 iJa3g+/xGFm/kkK17S5CBbyTiZfVQKrBGh2L0y22qA7T5qLQKB2geqiDWrbNLeCv055v 7kxg== X-Gm-Message-State: AOAM53234cZ7z93c1B+tQdKJuM5Jw2yMxm0mImiIthoroe+s8ZDiN4om zcHsnWZFf85Rss5w6QEaFXE= X-Google-Smtp-Source: ABdhPJyz8+qZuYkN1TG5YmX3iGnFsdfMx87Xvu89fA5FS6dk7qDgpMDXn41eKhld43zlQARb0EuXLg== X-Received: by 2002:adf:bc49:: with SMTP id a9mr2725wrh.109.1619120403721; Thu, 22 Apr 2021 12:40:03 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , David Gibson , Greg Kurz Subject: [PATCH v6 11/18] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps Date: Thu, 22 Apr 2021 21:38:55 +0200 Message-Id: <20210422193902.2644064-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) VirtIO devices are only meaningful with system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 ----- include/hw/core/sysemu-cpu-ops.h | 8 ++++++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/ppc/translate_init.c.inc | 4 +--- 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bdc702894bf..e3c702b8b74 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,10 +89,6 @@ struct AccelCPUClass; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurab= le - * CPUs can use the default implementation of this method. This method sho= uld - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -151,7 +147,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index a10d9fbdd16..1c325d62b94 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,14 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this me= thod. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); /** * @legacy_vmsd: Legacy state for migration. * Do not use in new targets, use #DeviceClass::vmsd ins= tead. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 5abf8bed2e4..09eaa3fa49f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->virtio_is_big_endian) { - return cc->virtio_is_big_endian(cpu); + if (cc->sysemu_ops->virtio_is_big_endian) { + return cc->sysemu_ops->virtio_is_big_endian(cpu); } return target_words_bigendian(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b598bf10a8..d071ae72ba3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .legacy_vmsd =3D &vmstate_arm_cpu, }; #endif @@ -1988,7 +1989,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e3f2f2fefa3..8d6bc6c0087 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .legacy_vmsd =3D &vmstate_ppc_cpu, }; #endif @@ -10948,9 +10949,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_core_xml_file =3D "power64-core.xml"; #else cc->gdb_core_xml_file =3D "power-core.xml"; -#endif -#ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif cc->disas_set_info =3D ppc_disas_set_info; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id o17sm4522281wmq.47.2021.04.22.12.40.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uLpgUUvTtmkbS378/dgmetDuRLNqY34+bULmG92CLFU=; b=b8OAqAl9ljQ5ZYTsPIy6IFqdLayCI/yYsKDOC9fZHCO/poQfztK8RSq3K9FdmStWrE Y8qByfa9glVNiWKx9Br+7OsqD9PrfR5qiT2fQX6+oqGg02AP5FsuXB6xDSsaPLN4o21h uQLBvB1Ot1sZUcxGiOF9hjjv5fgfFO81pd4nJB1IkjY2VEKMJen7eMgp+k32Cxnx9+iT 5HM1hh81nqw3aZ29DLTqhzfOQGY8vz30+JSQ9T8bbv8weukT+341TPBPoebRwnJFvtGc J3LDVtsXCXqgtVhHvCPrJEyDlGF7YRQCb3KYmPIL3Za2ZfkeKk928Z3YCwX1uMI9+eXJ I+tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=uLpgUUvTtmkbS378/dgmetDuRLNqY34+bULmG92CLFU=; b=jFPO3mDhNbIOpjXe9dHsdco70khFeLNUke8JWb2hOjWQYeCF1Y39iA9CHgDcm4ugNl 5i81lBlY5mTopY8+WMG12CzBxcrCrDBUe6W7hh3wRtIE0qFmpnUguAysPJianrMtjqjW L8i7G1j9dC1PDG8G9zNuyxgp56ekBdBnGIlT3SMRwuQkQnec+0pi7hKP0aqnwAe1o0SD wGIYpDGZATJuRHEYcpsuV4bHq+OUud/nW6EqLax/jX3nCfyQ0LDw6hjqqsuI4I6A05lp FWf5GNmS88xgqRiUsGbq9vYELbUMe4Sn948pOEJuBMaFZDfmIJCqbw530fNfAHHaZ79Z eVJw== X-Gm-Message-State: AOAM532r4mtTWs1dwqtaZcTz3lYXMvY9W/j2RPBbrwTKDkgoc0Kjt0vq 6HLfM7/WjhUJuDV4ls8KP1s= X-Google-Smtp-Source: ABdhPJzY13FoHhOEcp8xqb/Skv7Z4klTFux9/UotxkAZJtjnjEAHsebHcjQo7cCcvwWHr/VUgvK7pg== X-Received: by 2002:a5d:4b8e:: with SMTP id b14mr39922wrt.86.1619120408939; Thu, 22 Apr 2021 12:40:08 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , Cornelia Huck , Thomas Huth , David Hildenbrand Subject: [PATCH v6 12/18] cpu: Move CPUClass::get_crash_info to SysemuCPUOps Date: Thu, 22 Apr 2021 21:38:56 +0200 Message-Id: <20210422193902.2644064-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 1 - include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- target/s390x/cpu.c | 2 +- 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e3c702b8b74..4289cd0d78a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -150,7 +150,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 1c325d62b94..f7a91a66e06 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 09eaa3fa49f..0aebc18c41f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); GuestPanicInformation *res =3D NULL; =20 - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); + if (cc->sysemu_ops->get_crash_info) { + res =3D cc->sysemu_ops->get_crash_info(cpu); } return res; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index eb96dd42556..ab0c07fe9b4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_crash_info =3D x86_cpu_get_crash_info, .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7432,7 +7433,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->get_crash_info =3D x86_cpu_get_crash_info; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 131e7dfdf82..55d7a727602 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_crash_info =3D s390_cpu_get_crash_info, .legacy_vmsd =3D &vmstate_s390_cpu, }; #endif @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id v8sm5291456wrt.71.2021.04.22.12.40.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AZJBeeNOH22jprJnWdXZAe0tHqvL7WeWaboJ9qAD1UQ=; b=Z240BZRQryTPhCTTWoxnTx5VdWN+5rgXKu+uoKPVPn17ft+8g6X95bIEXvIWU62eRf qxUB7mxiRhQhQQdC8qKtTnslZBqi0Vakdr1qPYKXzGxcslsl0wMsMzovRj8i+2+JmdPz IRKzewboYxAc5V4a8LCvD+kS3rWtOhBzbF78blEiTZ0Lbhw7hzePBhsGuRts/62ZkqBI JZT4v6EQkBPL2a/MkcOYBFDltuSS6S/8VdYVmiH7XVhVeqoltemcH7kjfhUP01lvUige PjBuDUIJQFV0d1ZTjNKqhH/qQeH32O5K0FqqUBdONLE5O+9U6djVnxnjmdVJVu8IAcFb Kbrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AZJBeeNOH22jprJnWdXZAe0tHqvL7WeWaboJ9qAD1UQ=; b=AOJICCCgToc5W4f1lDR0bjzFDWt5ho5e7wUpsII28LHWUMm+rzuj5zMZT8y6RKdi5V bFV35XblogVJqdflGw7/REBOT+QrcubWXcW6ehkQmegpzbCMR6awlgdUaRlNDbGpep5/ 1TJsRYV43gv4GCWTnroqduxRNGvRIwPvLzVBZ6510cAFFe1RfuVzYzql7m6pIGGCvaiY kV1RElsC+FWNW9VvXbHBTmFx0G3MVUi7hPiBRq7KsDDLwiejd+Wr0EdMVtPTvBnhIRgv ypeLFCPwmTse/mPPOTM91I9q6kwvvtOGQRHgiGUw88XnYBm0kf+cVuvEhkU54NgpgmaV NMXg== X-Gm-Message-State: AOAM5336EMvAyrPonuKkr7/2DdL35p/WCiOWY/23otaGiXefife2lkjn R221h2PUfG+9knKq80jXjno= X-Google-Smtp-Source: ABdhPJwbDF4V6eFQUwDJFRJ9b0e5408t29KAt7OMNIcJouq+8/VzsshYNRRJ5XWowfaJ+2vs2egljw== X-Received: by 2002:a1c:771a:: with SMTP id t26mr398222wmi.96.1619120414533; Thu, 22 Apr 2021 12:40:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , David Hildenbrand , Cornelia Huck , Thomas Huth Subject: [PATCH v6 13/18] cpu: Move CPUClass::write_elf* to SysemuCPUOps Date: Thu, 22 Apr 2021 21:38:57 +0200 Message-Id: <20210422193902.2644064-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 17 ----------------- include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++ hw/core/cpu.c | 16 ++++++++-------- target/arm/cpu.c | 4 ++-- target/i386/cpu.c | 8 ++++---- target/riscv/cpu.c | 4 ++-- target/s390x/cpu.c | 2 +- target/ppc/translate_init.c.inc | 6 ++---- 8 files changed, 43 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4289cd0d78a..b7095bc4192 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -112,14 +112,6 @@ struct AccelCPUClass; * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -163,15 +155,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index f7a91a66e06..bdc76d580e9 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,30 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 0aebc18c41f..c74390aafbf 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_qemunote) { + if (!cc->sysemu_ops->write_elf32_qemunote) { return 0; } - return (*cc->write_elf32_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_note) { + if (!cc->sysemu_ops->write_elf32_note) { return -1; } - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); } =20 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_qemunote) { + if (!cc->sysemu_ops->write_elf64_qemunote) { return 0; } - return (*cc->write_elf64_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_note) { + if (!cc->sysemu_ops->write_elf64_note) { return -1; } - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d071ae72ba3..cbfdb9d0b70 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .write_elf32_note =3D arm_cpu_write_elf32_note, + .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .legacy_vmsd =3D &vmstate_arm_cpu, }; @@ -1989,8 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->write_elf64_note =3D arm_cpu_write_elf64_note; - cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ab0c07fe9b4..fd7788907ea 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7394,6 +7394,10 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_crash_info =3D x86_cpu_get_crash_info, + .write_elf32_note =3D x86_cpu_write_elf32_note, + .write_elf64_note =3D x86_cpu_write_elf64_note, + .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, + .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7433,10 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->write_elf64_note =3D x86_cpu_write_elf64_note; - cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; - cc->write_elf32_note =3D x86_cpu_write_elf32_note; - cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5514e23c1d2..cacec059754 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .write_elf64_note =3D riscv_cpu_write_elf64_note, + .write_elf32_note =3D riscv_cpu_write_elf32_note, /* For now, mark unmigratable: */ .legacy_vmsd =3D &vmstate_riscv_cpu, }; @@ -631,8 +633,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; - cc->write_elf64_note =3D riscv_cpu_write_elf64_note; - cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 55d7a727602..afb55be5c8c 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { .get_crash_info =3D s390_cpu_get_crash_info, + .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, }; #endif @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 8d6bc6c0087..b348b08868d 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,8 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .write_elf32_note =3D ppc32_cpu_write_elf32_note, + .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .legacy_vmsd =3D &vmstate_ppc_cpu, }; @@ -10929,10 +10931,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif -#if defined(CONFIG_SOFTMMU) - cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; - cc->write_elf32_note =3D ppc32_cpu_write_elf32_note; -#endif =20 cc->gdb_num_core_regs =3D 71; #ifndef CONFIG_USER_ONLY --=20 2.26.3 From nobody Sun Jun 9 01:22:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7095bc4192..28c4fc541a2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index bdc76d580e9..52a05ea9b3e 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c74390aafbf..c44229205ff 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cbfdb9d0b70..e030890c11b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fd7788907ea..70b0108b748 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -7434,7 +7435,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3 From nobody Sun Jun 9 01:22:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id z14sm6293246wrt.54.2021.04.22.12.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kimPdITTY4oOTcXSVRZ5/sMJGOTbvA4T6HV5zeAHBX4=; b=i7G4/RvuB0FsqaFnmk2o6fkLDGkG5/GPSyfAPaIUBFfrj1CaQ3RO/QHvA4bn8/QQnZ EAOIdvaiFeeOhfT4vcEyNk76qG3OXcZ40LyW8M4WqEjsAeRM2Uyse+YJk1LatpW4gsiU OHs7xtyMuDIb6delpTNBHLkOfDFi/OO0rDsA++nv9Ljp+0WZCbwlFW95W5Gps+WCadlb sV9q9+Q7F3lIxRGzbsg5Ed55cI6RYcHOasJIDov3CafIcYmn2M7wOVTr2rCJJsjKUIwm Ulamy2r0bg1X0N9TZL3qe1nlS6dKEyORipvT2jx6uL7ZVXa2y8naIOiqeGmqxnRgfxyG NHUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kimPdITTY4oOTcXSVRZ5/sMJGOTbvA4T6HV5zeAHBX4=; b=lSOwNrpljUzowGasmHMcxSEFB+c/Qy6IOdnvQkEoJ1QvCn3RoiIh3Rg64yq3WVv0Qp yHieYPiuxvpWnMu9o8tbW9MWv2aWgkk2Scp21sOzfTnsZNy5IsvsSSQkxC1VMJbWj2ep jDaPKbD3+WCBlSJQW9pQ56SwwMLPmYXhFC3J0C1uS7q4v2aMwvVx4T7Rq9eHr7u1RKks JNdcGLtBZrC0QlI3Z05UXcKL7kA18Y1zMZpkaL6gxI/ivWc6nlYTgBKB7ynyuX769wxP /Rqk6LOIdO3FtNVbBkHFBqnl1stHIE47mFGbpfBvwBa8gIekHfmJ+ZEZW41QyXBJaPnt He5A== X-Gm-Message-State: AOAM533emhEM95vMuEIi1h4vbvYkmKhS0wx6PadHjUWxELilYlnRJFWu pO8kvgksYUGiZW0Jn3rhQg0= X-Google-Smtp-Source: ABdhPJyEw2XF9FKop4IiRIfwu2sT/6HNWKaRVbjp23x6O7BwWlLdmi0DHq5NrVA9DzmcjgArwCxBtg== X-Received: by 2002:adf:f081:: with SMTP id n1mr2950wro.137.1619120426328; Thu, 22 Apr 2021 12:40:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Michael Rolnik , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , Cornelia Huck , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v6 15/18] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Date: Thu, 22 Apr 2021 21:38:59 +0200 Message-Id: <20210422193902.2644064-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 38 insertions(+), 33 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 28c4fc541a2..88a0a90ac7b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 52a05ea9b3e..4be4a4b4da7 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c44229205ff..6932781425a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index cd01d34d92f..979a4c0be1e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, }; #endif =20 @@ -241,7 +242,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e030890c11b..4b7d298827f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5c8bb9b3fec..a357ff0bffb 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -215,7 +216,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; dc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 394df655c9f..58193c02cbf 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, }; #endif =20 @@ -297,7 +298,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6605c42e509..0d755b8a880 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, }; #endif =20 @@ -166,7 +167,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 70b0108b748..ead0aafd9d1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 2b40f2b2559..01fbd751eb2 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps lm32_sysemu_ops =3D { + .get_phys_page_debug =3D lm32_cpu_get_phys_page_debug, }; #endif =20 @@ -245,7 +246,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_lm32_cpu; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 600812d682b..f743a86c7d5 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, }; #endif =20 @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c6a10b1a52b..8ccac373631 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, }; #endif =20 @@ -391,7 +392,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4023d487669..dd6033c576e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .legacy_vmsd =3D &vmstate_mips_cpu, }; #endif @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index e7bf5298c67..295ccde10e5 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static const struct SysemuCPUOps moxie_sysemu_ops =3D { + .get_phys_page_debug =3D moxie_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -124,7 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 296ccc0ed3c..f3b51732c29 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -209,6 +209,7 @@ static Property nios2_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, }; #endif =20 @@ -242,7 +243,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cd8e3ae6754..babe637cda6 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, }; #endif =20 @@ -208,7 +209,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cacec059754..0c350195e07 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, /* For now, mark unmigratable: */ @@ -631,7 +632,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index bbee1cb913f..e76b7708b89 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -175,6 +175,7 @@ static void rx_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; #endif =20 @@ -212,7 +213,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index afb55be5c8c..5b3551e290c 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 85e15ec9954..09de295cf91 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, }; #endif =20 @@ -261,7 +262,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; dc->vmsd =3D &vmstate_sh_cpu; #endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 543853c24dc..90658ba8e61 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .legacy_vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8865fa18fce..4572dde1486 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -143,6 +143,7 @@ static void tc27x_initfn(Object *obj) } =20 static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -173,7 +174,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 60ae917f0ee..36d712259f2 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -122,6 +122,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static const struct SysemuCPUOps uc32_sysemu_ops =3D { + .get_phys_page_debug =3D uc32_cpu_get_phys_page_debug, }; #endif =20 @@ -150,7 +151,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &uc32_sysemu_ops; dc->vmsd =3D &vmstate_uc32_cpu; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index d0bf06696e4..eb61ee55be4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, }; #endif =20 @@ -221,7 +222,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_xtensa_cpu; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index b348b08868d..dc53cc545f4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10928,7 +10929,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif =20 --=20 2.26.3 From nobody Sun Jun 9 01:22:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120433; cv=none; d=zohomail.com; s=zohoarc; b=Paq9mA90kBjhy0e4Ki5rYA6dskBirw8TsS6cyUO2T3UF11BEwIwZlYOJ7uk9+ctUeZETZpaCWQffAmYLHzUNsMUjJQ/hGpxjjTYpMdETMxGOc5CV/drgQWaPrhvGPZ3sfndIxbe78soczIbw1JaYqKT4koGpZQnEjewekZdglU8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id g84sm4533927wmf.30.2021.04.22.12.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m966GbKrCJcUqO+fuAnWPPht7OR9OhPJulfZwNFNX4c=; b=e6U+4JX0OOSuZd5s37c90oS/hEFKgL+Mydprc08dVIouGDXcVIF4FJYImOSsqVwdL1 6nuEokgLBiQl7DROmN6ueqsi62r9bWGvMzKzoIipXBVdVbpcHOf1KsiiHB47SOlzGbDn 2m5ee4P7mpmVqhr/oSEYFdOrzQqWXrln6z5J3Yip0C2usN1oB+fez6pIMjb65zZHfNW6 UvORWtKZmC9rO7NDsRf78I3JcN16zW0gk3Uu4pp9ex8wAs5mEaNtEpwj/bwKvz1rkcOP ViSf6oNR+VrrvroLmz4wQqdSwo4ED/FBVplt4ebv66PZQjExlDjGCbLgVpKMGYccY8Uv A9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=m966GbKrCJcUqO+fuAnWPPht7OR9OhPJulfZwNFNX4c=; b=Fhochku1Rh6+2pTt9ZCqOnIALPpHNzJ248ARiyQmQuEI7rtewuakckBGc3C53NlIYw MwhE48bt12LhQeM4elOZsgXf1holhYgsojkvmLV0oSn6vT3jO0Tcsv77X2gv7s25YJkG krSBS3TUusbpQjAvEWuZWsn760WFYl00zTHZ6l8RTgoLiHFUwEGbNeZCZ0Hd5ZZ4NOAZ QsVMvzgFDZ8dsU6cE2mUrXx16GPzfpkvO0PWjiDn9qQ349m9izIi7+VuImg+wyUadfJQ qdV6DhtbRyYoqs7b8ENw+OmoXXGsl+2ebwT3tYgav1aQ5HsMl+jkw8q3MAGGY4kzmeLM EqgA== X-Gm-Message-State: AOAM532EJy64pFGgeCJ0uLzca2lLdfQAg2q5jFRBd6cCKhSp+L/2l+Z2 tj+B5qRP3NKIssq8zvLQnG4= X-Google-Smtp-Source: ABdhPJw50THXM5vmBB6WPRjlXV3QXpGKmaOufqJPEXTArEXJvrP3c0c6JEYOIs33fplRxA/TMGBi5A== X-Received: by 2002:a5d:534e:: with SMTP id t14mr5965958wrv.239.1619120431581; Thu, 22 Apr 2021 12:40:31 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini Subject: [PATCH v6 16/18] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps Date: Thu, 22 Apr 2021 21:39:00 +0200 Message-Id: <20210422193902.2644064-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 88a0a90ac7b..6dd60c3ada4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -94,7 +94,6 @@ struct AccelCPUClass; * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -138,8 +137,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 4be4a4b4da7..344561b7827 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 6932781425a..339bdfadd7a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_memory_mapping) { - cc->get_memory_mapping(cpu, list, errp); + if (cc->sysemu_ops->get_memory_mapping) { + cc->sysemu_ops->get_memory_mapping(cpu, list, errp); return; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ead0aafd9d1..5d35d8e329f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.26.3 From nobody Sun Jun 9 01:22:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120438; cv=none; d=zohomail.com; s=zohoarc; b=QyKhzzVXNc5TpSS5K0/JNQc/elw/GD8kdW8A+UwzuqfIeWRaZefveN77bd1SljN3PYpWIGSWAPsYLWGbRpNN1rvThES/eRDMYtvRPuj1yGiPsWZUz4bLLxPxSSMG7B8lPHKLs1iytzOEOOU8XFrDarAqk9EP4BaNQ3DLU/a7rJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120438; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S/tuuNIpZQoRu1GShuaPUInFgchy3nLKXlFhmpoZHyQ=; b=g9o71vgWYuqOxXOC9VL4+LU3DQN8LR8gBqVO+g/DEqXjfMFH9nddTkOk7Z2XcK5kNdAfXmGpVaVmkZcDRsaewGeeQK+SKvBgnETV8DYRx2x3qImgJDa0vPkyCTzCuLUbnH5G70ZRE2Lg/pZ0fFxt6dsL+GBT4H8nDweHtz7Z7QM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1619120438630855.6925513432494; Thu, 22 Apr 2021 12:40:38 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id c4so7035880wrt.8 for ; Thu, 22 Apr 2021 12:40:38 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id d10sm5172425wri.41.2021.04.22.12.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S/tuuNIpZQoRu1GShuaPUInFgchy3nLKXlFhmpoZHyQ=; b=fnaw9do6bkoRnfJXMFMkFJTAJub+LjBh1v5V0x0mV7pfneSOF1NIZzVU6UhyRM2rDV jKy2ZDXuuyYyRlTye5JvH7FzsmaI+XqzG90Orr6Kl0kTU5Ipp4JuO3f85mJzDE4PI77F D96+8/m2tvd6ddgEXLic0xAe6wBnq1oLyZCaSkeDJRZM4YD8NUfNn2OEVTpTFmOOQEcP AF9XAKtgmNZha3dm8PTXTnAi/1sDvWknN9BvhkO1kOoE7qgcSwJ84ZbTeuGTG8s7xVFb zwSqJfaljzjSTC8mXJ2ZDO1E4FissANcvlOfzNyd+x54RfIf8blLW6EtMX826xB9J3LB E3hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=S/tuuNIpZQoRu1GShuaPUInFgchy3nLKXlFhmpoZHyQ=; b=HGzzbOeZWTe7edu6FxXR2XYhnpmn0HxqiTB8K5ehwaUHsHDrjCHM8kkPVAfEAY6MkH /R3pQakcGKZ3nTDg3FUf9h+vcfog5sRnWzTChuMedL/IWQKrzgEj0RCtmNviWZErA8iZ 7DbGuDDXGxwdupxMPuRx5k5kgC3JkNX+ARq26p+Vrz1iQJKkOtzWu2rVZLBAIU7zFjtm F9j66ayiZ2P02Jji/V73csSN1Wogpv8nnZh80OXe6v6Ei+qLcUT+5bTKH/yLKGC+6XPY 49nUcbUgE5rE//iw0GDxLXcHR2nMqSH2L9Jk9SKPHd9nAxqRSsyeSdbb121/SWuqfCQs cVUg== X-Gm-Message-State: AOAM532gi2fyF+9aHzdDS0ba9XjOhBgtchPKhFdSpNSIHjU+4hCvNddw OJ5r6wAc2TxLyRAUmzM91gI= X-Google-Smtp-Source: ABdhPJyWeFzy7j1iw7Gf55A8wmXiGXJDIqx54FI3qIdeXeic4Ftc/YwG6FF3c0ywgEwGP8r8azJAmA== X-Received: by 2002:a5d:50c5:: with SMTP id f5mr38488wrt.136.1619120436886; Thu, 22 Apr 2021 12:40:36 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Paolo Bonzini Subject: [PATCH v6 17/18] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps Date: Thu, 22 Apr 2021 21:39:01 +0200 Message-Id: <20210422193902.2644064-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6dd60c3ada4..d0187798eea 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -93,7 +93,6 @@ struct AccelCPUClass; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -136,7 +135,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 344561b7827..f0707f012b4 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 339bdfadd7a..7a8487d468f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->sysemu_ops->get_paging_enabled) { + return cc->sysemu_ops->get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5d35d8e329f..abdebdfe9b8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7162,12 +7162,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs) return cpu->apic_id; } =20 +#if !defined(CONFIG_USER_ONLY) static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 return cpu->env.cr[0] & CR0_PG_MASK; } +#endif /* !CONFIG_USER_ONLY */ =20 static void x86_cpu_set_pc(CPUState *cs, vaddr value) { @@ -7394,6 +7396,7 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_memory_mapping =3D x86_cpu_get_memory_mapping, + .get_paging_enabled =3D x86_cpu_get_paging_enabled, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7434,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3 From nobody Sun Jun 9 01:22:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619120444; cv=none; d=zohomail.com; s=zohoarc; b=MpXvB/5itIkIoPgsIYWBb3bsSBX7tArF9qXfl7AwMPYYchUMg5pbL/6/4Jco+WkZmhNZsLjMEfy240VV5ErlbCgceRXcpYOOlcxHNZnGUYfKRyaOPfYGbAR/JTlNJkyZcquI30xTWkpsIsrQQtva5hiL8UJgAQk0cdMOLMP3FiY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619120444; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8AqweBapguPmOlWDQSk9kMwa86Evn6EEtsuRuMCSv+g=; b=nxqFadU3cntuCUFDA7prC+Z8PfYc8MBdoQcBLeJojIJHaramSXFfyHJZVL3+XJzSNlZft7BfDupldJqUrqHGcYTk1r2ckiYtBASQewSEc7wihoMfX+UShy1yaXlVLEmlqV6CbTSUXTyRaHga3D94EkjHbnZhXeCf5enlmz4xwA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 1619120444983962.6725360970428; Thu, 22 Apr 2021 12:40:44 -0700 (PDT) Received: by mail-wr1-f45.google.com with SMTP id x7so45911042wrw.10 for ; Thu, 22 Apr 2021 12:40:44 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id f11sm7596634wmc.6.2021.04.22.12.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 12:40:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8AqweBapguPmOlWDQSk9kMwa86Evn6EEtsuRuMCSv+g=; b=BS2b3AC0fVgCuV5m4c/yxpBES/fNG4Or93EqeDVgRbd2QJhSSOU3HfDsO7umHir/X+ wTY6RONPPFIFp0oASZ6u/z2sAwke8uRU/LaN2EtknPlRcuGgiotyW/SKV2gHqzveX2/a 77ooq3cTz9T5JtRWlre7eExBLk15MKH3jkmS6umhe+m99mBinCyH9YxVWV17Oy232xzx DiTVnRxtxNpYgwv5aMjQWbMmPibpWd2yemNa2V+Qgtd1CAmBvU+PS6yFlp/GSvUL31Cl UhAyY5pMGnZMwImj6gmBRVMhb2LREuQhn7pUqZeF1NzuEsII6drwSrTrsuXo38njYDEF FSuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8AqweBapguPmOlWDQSk9kMwa86Evn6EEtsuRuMCSv+g=; b=qC5Yvd5bUJCXyICNklWVFdY4C9eyHc6F6n581W9QYA57fcky3a/6QXOFZ6DxXbpQtj wWaHg6L9OUD9YDgUY7gkpj0Ox1JU+ytSCBCoWnCR47dBxUdlbhWuTHepBG2sK+l9BVWR PtGKZf5bToqW0qUzUM7KqvuPKhAK2qnoxZSRmGkstmVunhj2loEA8gXuZYCFqeCpri1p eEUntvGZ331tEW76aYy/kDPtYPlUNqcXci36zDcko8d2YtGwXDgEUqEeXszr5s23Qf5r o0C3peKpe2SXucfCY3UI30MH+wCni0M6KF+0Nt6RMZaW9gaLxCSnuj0FkVj5/nx7r2DX x5QQ== X-Gm-Message-State: AOAM533PEOHIG+yMSV0wOmbntSf3o5sbNlBP28fs3GgEN4dkbqAJj1jt yl7dYqPGvrxXkhOiuGO91qw= X-Google-Smtp-Source: ABdhPJym6F2N73rzVCNKjBuNPknzVv5ID7iK8bCHWZ+dyDhIT4brKz3EPgcRcobp3uGqFEjsiaq4bg== X-Received: by 2002:adf:db4f:: with SMTP id f15mr7646wrj.99.1619120443185; Thu, 22 Apr 2021 12:40:43 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , qemu-riscv@nongnu.org, Juan Quintela , Peter Maydell , Claudio Fontana , qemu-arm@nongnu.org, Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Laurent Vivier , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Taylor Simpson , Marcel Apfelbaum , Michael Rolnik , "Edgar E. Iglesias" , Paolo Bonzini , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Cornelia Huck , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v6 18/18] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c Date: Thu, 22 Apr 2021 21:39:02 +0200 Message-Id: <20210422193902.2644064-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422193902.2644064-1-f4bug@amsat.org> References: <20210422193902.2644064-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"): We cannot in principle make the SysEmu Operations field definitions conditional on CONFIG_SOFTMMU in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the SysEmu fields to system emulation builds, is to move all sysemu operations into a separate header file, which is only included by system-specific code. This leaves just a NULL pointer in the cpu.h for the user-mode builds. Inspired-by: Claudio Fontana Reviewed-by: Taylor Simpson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 ++- target/alpha/cpu.h | 3 +++ target/arm/cpu.h | 3 +++ target/avr/cpu.h | 1 + target/cris/cpu.h | 3 +++ target/hexagon/cpu.h | 3 +++ target/hppa/cpu.h | 3 +++ target/i386/cpu.h | 3 +++ target/lm32/cpu.h | 3 +++ target/m68k/cpu.h | 3 +++ target/microblaze/cpu.h | 1 + target/mips/cpu.h | 3 +++ target/moxie/cpu.h | 3 +++ target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 3 +++ target/ppc/cpu.h | 3 +++ target/riscv/cpu.h | 3 +++ target/rx/cpu.h | 1 + target/s390x/cpu.h | 3 +++ target/sh4/cpu.h | 3 +++ target/sparc/cpu.h | 3 +++ target/tricore/cpu.h | 3 +++ target/unicore32/cpu.h | 3 +++ target/xtensa/cpu.h | 3 +++ cpu.c | 1 + hw/core/cpu.c | 1 + 26 files changed, 65 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d0187798eea..3422d405b49 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,7 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 -#include "hw/core/sysemu-cpu-ops.h" +/* see sysemu-cpu-ops.h */ +struct SysemuCPUOps; =20 /** * CPUClass: diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967b..f1218a27706 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fa..d9228d1d990 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a4..e0419649fa7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b64929096..4450f2268ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,6 +23,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define EXCP_NMI 1 #define EXCP_GURU 2 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index e04eac591c8..2a878e77f08 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState; #include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61178fa6a2a..94d2d4701c4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "exec/memory.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916878f..2f520cb6fc1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -25,6 +25,9 @@ #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ea7c01ca8b0..034183dad30 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 typedef struct CPULM32State CPULM32State; =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 402c86c8769..681dc0d1d13 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -23,6 +23,9 @@ =20 #include "exec/cpu-defs.h" #include "cpu-qom.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define OS_BYTE 0 #define OS_WORD 1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..3f5c2e048e5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -26,6 +26,7 @@ =20 typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..923ab71f8d7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -6,6 +6,9 @@ #include "fpu/softfloat-types.h" #include "hw/clock.h" #include "mips-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index bd6ab66084d..7a0a5e95d01 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -22,6 +22,9 @@ =20 #include "exec/cpu-defs.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc713..1b88b027063 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -27,6 +27,7 @@ =20 typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..2a6f9f48547 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -23,6 +23,9 @@ #include "exec/cpu-defs.h" #include "hw/core/cpu.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68d..f889c28e548 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -24,6 +24,9 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba8..90ac5097718 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,9 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7be..d9b7b63716a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -25,6 +25,7 @@ #include "cpu-qom.h" =20 #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 /* PSW define */ REG32(PSW, 0) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2464d4076c0..8f7233d97c2 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,6 +28,9 @@ #include "cpu-qom.h" #include "cpu_models.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define ELF_MACHINE_UNAME "S390X" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 01c43440822..6c3d3a29fc2 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4b2290650be..237ffc4fe66 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,9 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f8..a7636c0e870 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "tricore-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 struct tricore_boot_info; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 7a32e086ed3..de475d0fc2e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -14,6 +14,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 typedef struct CPUUniCore32State { /* Regs for current mode. */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3bd4f691c1a..ea4ee5338f3 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/cpu.c b/cpu.c index 47eb8c40775..610df6660b3 100644 --- a/cpu.c +++ b/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else +#include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #endif #include "sysemu/tcg.h" diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 7a8487d468f..da7543be514 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -35,6 +35,7 @@ #include "trace/trace-root.h" #include "qemu/plugin.h" #include "sysemu/hw_accel.h" +#include "hw/core/sysemu-cpu-ops.h" =20 CPUState *cpu_by_arch_id(int64_t id) { --=20 2.26.3