From nobody Mon Feb 9 15:24:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1619121964; cv=none; d=zohomail.com; s=zohoarc; b=KUoQDRFQWko87A9wE2a+e+kIUAVyzfSUHi0yMq0+CS8v00FKY5Cr99p6EfnpfykRPW+FceeeKW5nltF+BT4AqhtS5EX4ZjbrRPAQwbfpJaCpfyZO4amAg/V3RerL3BKWs2c5s0WsrI+d61EF30iFlt4IlxW0QUMhP4Fnrz879eY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619121964; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=dQYn7/IdcgwyIv4QOylnKiAMZAPmceUBt1jyhvzcVE8=; b=aG5VJM5MywH6CWNo6t5m0THL1TupH6MiOVqFYi6l+EMcSFTC5rzk101A8TPL34F3tpfEkw9C5sZ/caYZrdWF7eICQhIFqrYVJAGtoWUqTdz97g2qpkErXECP8jN2y/AWTBAFyHGT8EObkJrxLB3yg5BVpP4XPygaLdgsJCh6gZs= ARC-Authentication-Results: i=1; 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Thu, 22 Apr 2021 16:31:37 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id C557F800BEE; Thu, 22 Apr 2021 16:31:37 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH 1/4] target/ppc: updated build options Date: Thu, 22 Apr 2021 16:31:28 -0300 Message-Id: <20210422193131.22560-2-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> References: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 22 Apr 2021 19:31:37.0961 (UTC) FILETIME=[1CE95590:01D737AE] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, lucas.araujo@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" updated meson.build to not compile tcg-only files Signed-off-by: Lucas Mateus Castro (alqotel) --- target/ppc/meson.build | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/target/ppc/meson.build b/target/ppc/meson.build index bbfef90e08..b369a6bcd0 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -2,10 +2,17 @@ ppc_ss =3D ss.source_set() ppc_ss.add(files( 'cpu-models.c', 'cpu.c', + 'gdbstub.c', +)) + +ppc_ss.add(libdecnumber) + +ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('k= vm-stub.c')) +ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) +ppc_ss.add(when: 'CONFIG_TCG', if_true: files( 'dfp_helper.c', 'excp_helper.c', 'fpu_helper.c', - 'gdbstub.c', 'int_helper.c', 'mem_helper.c', 'misc_helper.c', @@ -13,21 +20,22 @@ ppc_ss.add(files( 'translate.c', )) =20 -ppc_ss.add(libdecnumber) - -ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('k= vm-stub.c')) -ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) =20 ppc_softmmu_ss =3D ss.source_set() ppc_softmmu_ss.add(files( 'arch_dump.c', 'machine.c', + 'monitor.c', +)) +ppc_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'mmu-hash32.c', 'mmu_helper.c', - 'monitor.c', )) + ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'compat.c', +)) +ppc_softmmu_ss.add(when: ['TARGET_PPC64', 'CONFIG_TCG'], if_true: files( 'mmu-book3s-v3.c', 'mmu-hash64.c', 'mmu-radix64.c', --=20 2.17.1 From nobody Mon Feb 9 15:24:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 22 Apr 2021 13:10:29 -0700 (PDT) Received: from localhost ([::1]:45440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZfee-0006z5-50 for importer@patchew.org; Thu, 22 Apr 2021 16:10:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZfKy-00063C-IU; Thu, 22 Apr 2021 15:50:09 -0400 Received: from [201.28.113.2] (port=23502 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZfKt-0002SN-K5; Thu, 22 Apr 2021 15:50:08 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Thu, 22 Apr 2021 16:31:38 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 6C908800BEE; Thu, 22 Apr 2021 16:31:38 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH 2/4] hw/ppc: Add kvm-only file spapr_hcall_tcg_stub.c Date: Thu, 22 Apr 2021 16:31:29 -0300 Message-Id: <20210422193131.22560-3-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> References: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 22 Apr 2021 19:31:38.0618 (UTC) FILETIME=[1D4D95A0:01D737AE] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, lucas.araujo@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This file should be used instead of spapr_hcall.c when compiling without tcg (--disable-tcg) as it does not call tcg-only functions and trips fatal error when invalid functions are called As of right now some functions are repeated here and in spapr_hcall.c, as they are static, is some other method to deal with this recommended? Also some functions should only cause a fatal error as KVM should intercept and handle their call, but as I'm not sure which ones I just did this to functions that called tcg-only code. Signed-off-by: Lucas Mateus Castro (alqotel) --- hw/ppc/spapr_hcall_tcg_stub.c | 1824 +++++++++++++++++++++++++++++++++ 1 file changed, 1824 insertions(+) create mode 100644 hw/ppc/spapr_hcall_tcg_stub.c diff --git a/hw/ppc/spapr_hcall_tcg_stub.c b/hw/ppc/spapr_hcall_tcg_stub.c new file mode 100644 index 0000000000..6682279b6e --- /dev/null +++ b/hw/ppc/spapr_hcall_tcg_stub.c @@ -0,0 +1,1824 @@ +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "sysemu/hw_accel.h" +#include "sysemu/runstate.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "helper_regs.h" +#include "hw/ppc/spapr.h" +#include "hw/ppc/spapr_cpu_core.h" +#include "mmu-hash64.h" +#include "cpu-models.h" +#include "trace.h" +#include "kvm_ppc.h" +#include "hw/ppc/fdt.h" +#include "hw/ppc/spapr_ovec.h" +#include "mmu-book3s-v3.h" +#include "hw/mem/memory-device.h" + +static bool has_spr(PowerPCCPU *cpu, int spr) +{ + /* We can test whether the SPR is defined by checking for a valid name= */ + return cpu->env.spr_cb[spr].name !=3D NULL; +} + +static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) +{ + /* + * hash value/pteg group index is normalized by HPT mask + */ + if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { + return false; + } + return true; +} + +static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) +{ + MachineState *machine =3D MACHINE(spapr); + DeviceMemoryState *dms =3D machine->device_memory; + + if (addr < machine->ram_size) { + return true; + } + if ((addr >=3D dms->base) + && ((addr - dms->base) < memory_region_size(&dms->mr))) { + return true; + } + + return false; +} + +static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + /* + * FATAL ERROR + */ + g_assert_not_reached(); + return 0; +} + +typedef enum { + REMOVE_SUCCESS =3D 0, + REMOVE_NOT_FOUND =3D 1, + REMOVE_PARM =3D 2, + REMOVE_HW =3D 3, +} RemoveResult; + +static RemoveResult remove_hpte(PowerPCCPU *cpu + , target_ulong ptex, + target_ulong avpn, + target_ulong flags, + target_ulong *vp, target_ulong *rp) +{ + /* + * FATAL ERROR + */ + *rp =3D 0; + g_assert_not_reached(); + return 0; +} + +static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + target_ulong ptex =3D args[1]; + target_ulong avpn =3D args[2]; + RemoveResult ret; + + ret =3D remove_hpte(cpu, ptex, avpn, flags, + &args[0], &args[1]); + + switch (ret) { + case REMOVE_SUCCESS: + check_tlb_flush(env, true); + return H_SUCCESS; + + case REMOVE_NOT_FOUND: + return H_NOT_FOUND; + + case REMOVE_PARM: + return H_PARAMETER; + + case REMOVE_HW: + return H_HARDWARE; + } + + g_assert_not_reached(); +} + +#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL +#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL +#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL +#define H_BULK_REMOVE_END 0xc000000000000000ULL +#define H_BULK_REMOVE_CODE 0x3000000000000000ULL +#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL +#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL +#define H_BULK_REMOVE_PARM 0x2000000000000000ULL +#define H_BULK_REMOVE_HW 0x3000000000000000ULL +#define H_BULK_REMOVE_RC 0x0c00000000000000ULL +#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL +#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL +#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL +#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL +#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL + +#define H_BULK_REMOVE_MAX_BATCH 4 + +static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spap= r, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + int i; + target_ulong rc =3D H_SUCCESS; + + for (i =3D 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { + target_ulong *tsh =3D &args[i*2]; + target_ulong tsl =3D args[i*2 + 1]; + target_ulong v, r, ret; + + if ((*tsh & H_BULK_REMOVE_TYPE) =3D=3D H_BULK_REMOVE_END) { + break; + } else if ((*tsh & H_BULK_REMOVE_TYPE) !=3D H_BULK_REMOVE_REQUEST)= { + return H_PARAMETER; + } + + *tsh &=3D H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; + *tsh |=3D H_BULK_REMOVE_RESPONSE; + + if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN))= { + *tsh |=3D H_BULK_REMOVE_PARM; + return H_PARAMETER; + } + + ret =3D remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, + (*tsh & H_BULK_REMOVE_FLAGS) >> 26, + &v, &r); + + *tsh |=3D ret << 60; + + switch (ret) { + case REMOVE_SUCCESS: + *tsh |=3D (r & (HPTE64_R_C | HPTE64_R_R)) << 43; + break; + + case REMOVE_PARM: + rc =3D H_PARAMETER; + goto exit; + + case REMOVE_HW: + rc =3D H_HARDWARE; + goto exit; + } + } + exit: + check_tlb_flush(env, true); + + return rc; +} + +static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + /* + * FATAL ERROR + */ + g_assert_not_reached(); + return 0; +} + +static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + /* + * FATAL ERROR + */ + g_assert_not_reached(); + return 0; +} + +struct SpaprPendingHpt { + /* These fields are read-only after initialization */ + int shift; + QemuThread thread; + + /* These fields are protected by the BQL */ + bool complete; + + /* These fields are private to the preparation thread if + * !complete, otherwise protected by the BQL */ + int ret; + void *hpt; +}; + +static void free_pending_hpt(SpaprPendingHpt *pending) +{ + if (pending->hpt) { + qemu_vfree(pending->hpt); + } + + g_free(pending); +} + +static void *hpt_prepare_thread(void *opaque) +{ + SpaprPendingHpt *pending =3D opaque; + size_t size =3D 1ULL << pending->shift; + + pending->hpt =3D qemu_try_memalign(size, size); + if (pending->hpt) { + memset(pending->hpt, 0, size); + pending->ret =3D H_SUCCESS; + } else { + pending->ret =3D H_NO_MEM; + } + + qemu_mutex_lock_iothread(); + + if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt =3D=3D pending) { + /* Ready to go */ + pending->complete =3D true; + } else { + /* We've been cancelled, clean ourselves up */ + free_pending_hpt(pending); + } + + qemu_mutex_unlock_iothread(); + return NULL; +} + +/* Must be called with BQL held */ +static void cancel_hpt_prepare(SpaprMachineState *spapr) +{ + SpaprPendingHpt *pending =3D spapr->pending_hpt; + + /* Let the thread know it's cancelled */ + spapr->pending_hpt =3D NULL; + + if (!pending) { + /* Nothing to do */ + return; + } + + if (!pending->complete) { + /* thread will clean itself up */ + return; + } + + free_pending_hpt(pending); +} + +/* Convert a return code from the KVM ioctl()s implementing resize HPT + * into a PAPR hypercall return code */ +static target_ulong resize_hpt_convert_rc(int ret) +{ + if (ret >=3D 100000) { + return H_LONG_BUSY_ORDER_100_SEC; + } else if (ret >=3D 10000) { + return H_LONG_BUSY_ORDER_10_SEC; + } else if (ret >=3D 1000) { + return H_LONG_BUSY_ORDER_1_SEC; + } else if (ret >=3D 100) { + return H_LONG_BUSY_ORDER_100_MSEC; + } else if (ret >=3D 10) { + return H_LONG_BUSY_ORDER_10_MSEC; + } else if (ret > 0) { + return H_LONG_BUSY_ORDER_1_MSEC; + } + + switch (ret) { + case 0: + return H_SUCCESS; + case -EPERM: + return H_AUTHORITY; + case -EINVAL: + return H_PARAMETER; + case -ENXIO: + return H_CLOSED; + case -ENOSPC: + return H_PTEG_FULL; + case -EBUSY: + return H_BUSY; + case -ENOMEM: + return H_NO_MEM; + default: + return H_HARDWARE; + } +} + +static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + int shift =3D args[1]; + SpaprPendingHpt *pending =3D spapr->pending_hpt; + uint64_t current_ram_size; + int rc; + + if (spapr->resize_hpt =3D=3D SPAPR_RESIZE_HPT_DISABLED) { + return H_AUTHORITY; + } + + if (!spapr->htab_shift) { + /* Radix guest, no HPT */ + return H_NOT_AVAILABLE; + } + + trace_spapr_h_resize_hpt_prepare(flags, shift); + + if (flags !=3D 0) { + return H_PARAMETER; + } + + if (shift && ((shift < 18) || (shift > 46))) { + return H_PARAMETER; + } + + current_ram_size =3D MACHINE(spapr)->ram_size + get_plugged_memory_siz= e(); + + /* We only allow the guest to allocate an HPT one order above what + * we'd normally give them (to stop a small guest claiming a huge + * chunk of resources in the HPT */ + if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { + return H_RESOURCE; + } + + rc =3D kvmppc_resize_hpt_prepare(cpu, flags, shift); + if (rc !=3D -ENOSYS) { + return resize_hpt_convert_rc(rc); + } + + if (pending) { + /* something already in progress */ + if (pending->shift =3D=3D shift) { + /* and it's suitable */ + if (pending->complete) { + return pending->ret; + } else { + return H_LONG_BUSY_ORDER_100_MSEC; + } + } + + /* not suitable, cancel and replace */ + cancel_hpt_prepare(spapr); + } + + if (!shift) { + /* nothing to do */ + return H_SUCCESS; + } + + /* start new prepare */ + + pending =3D g_new0(SpaprPendingHpt, 1); + pending->shift =3D shift; + pending->ret =3D H_HARDWARE; + + qemu_thread_create(&pending->thread, "sPAPR HPT prepare", + hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); + + spapr->pending_hpt =3D pending; + + /* In theory we could estimate the time more accurately based on + * the new size, but there's not much point */ + return H_LONG_BUSY_ORDER_100_MSEC; +} + +static int rehash_hpt(PowerPCCPU *cpu, + void *old_hpt, uint64_t oldsize, + void *new_hpt, uint64_t newsize) +{ + g_assert_not_reached(); + return 0; +} + +static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) +{ + int ret; + + cpu_synchronize_state(cs); + + ret =3D kvmppc_put_books_sregs(POWERPC_CPU(cs)); + if (ret < 0) { + error_report("failed to push sregs to KVM: %s", strerror(-ret)); + exit(1); + } +} + +static void push_sregs_to_kvm_pr(SpaprMachineState *spapr) +{ + CPUState *cs; + + /* + * This is a hack for the benefit of KVM PR - it abuses the SDR1 + * slot in kvm_sregs to communicate the userspace address of the + * HPT + */ + if (!kvm_enabled() || !spapr->htab) { + return; + } + + CPU_FOREACH(cs) { + run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); + } +} + +static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong shift =3D args[1]; + SpaprPendingHpt *pending =3D spapr->pending_hpt; + int rc; + size_t newsize; + + if (spapr->resize_hpt =3D=3D SPAPR_RESIZE_HPT_DISABLED) { + return H_AUTHORITY; + } + + if (!spapr->htab_shift) { + /* Radix guest, no HPT */ + return H_NOT_AVAILABLE; + } + + trace_spapr_h_resize_hpt_commit(flags, shift); + + rc =3D kvmppc_resize_hpt_commit(cpu, flags, shift); + if (rc !=3D -ENOSYS) { + rc =3D resize_hpt_convert_rc(rc); + if (rc =3D=3D H_SUCCESS) { + /* Need to set the new htab_shift in the machine state */ + spapr->htab_shift =3D shift; + } + return rc; + } + + if (flags !=3D 0) { + return H_PARAMETER; + } + + if (!pending || (pending->shift !=3D shift)) { + /* no matching prepare */ + return H_CLOSED; + } + + if (!pending->complete) { + /* prepare has not completed */ + return H_BUSY; + } + + /* Shouldn't have got past PREPARE without an HPT */ + g_assert(spapr->htab_shift); + + newsize =3D 1ULL << pending->shift; + rc =3D rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), + pending->hpt, newsize); + if (rc =3D=3D H_SUCCESS) { + qemu_vfree(spapr->htab); + spapr->htab =3D pending->hpt; + spapr->htab_shift =3D pending->shift; + + push_sregs_to_kvm_pr(spapr); + + pending->hpt =3D NULL; /* so it's not free()d */ + } + + /* Clean up */ + spapr->pending_hpt =3D NULL; + free_pending_hpt(pending); + + return rc; +} + +static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + cpu_synchronize_state(CPU(cpu)); + cpu->env.spr[SPR_SPRG0] =3D args[0]; + + return H_SUCCESS; +} + +static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + if (!has_spr(cpu, SPR_DABR)) { + return H_HARDWARE; /* DABR register not available */ + } + cpu_synchronize_state(CPU(cpu)); + + if (has_spr(cpu, SPR_DABRX)) { + cpu->env.spr[SPR_DABRX] =3D 0x3; /* Use Problem and Privileged st= ate */ + } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ + return H_RESERVED_DABR; + } + + cpu->env.spr[SPR_DABR] =3D args[0]; + return H_SUCCESS; +} + +static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong dabrx =3D args[1]; + + if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { + return H_HARDWARE; + } + + if ((dabrx & ~0xfULL) !=3D 0 || (dabrx & H_DABRX_HYPERVISOR) !=3D 0 + || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) =3D=3D 0) { + return H_PARAMETER; + } + + cpu_synchronize_state(CPU(cpu)); + cpu->env.spr[SPR_DABRX] =3D dabrx; + cpu->env.spr[SPR_DABR] =3D args[0]; + + return H_SUCCESS; +} + +static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong flags =3D args[0]; + hwaddr dst =3D args[1]; + hwaddr src =3D args[2]; + hwaddr len =3D TARGET_PAGE_SIZE; + uint8_t *pdst, *psrc; + target_long ret =3D H_SUCCESS; + + if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE + | H_COPY_PAGE | H_ZERO_PAGE)) { + qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx = "\n", + flags); + return H_PARAMETER; + } + + /* Map-in destination */ + if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) !=3D 0) { + return H_PARAMETER; + } + pdst =3D cpu_physical_memory_map(dst, &len, true); + if (!pdst || len !=3D TARGET_PAGE_SIZE) { + return H_PARAMETER; + } + + if (flags & H_COPY_PAGE) { + /* Map-in source, copy to destination, and unmap source again */ + if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) !=3D = 0) { + ret =3D H_PARAMETER; + goto unmap_out; + } + psrc =3D cpu_physical_memory_map(src, &len, false); + if (!psrc || len !=3D TARGET_PAGE_SIZE) { + ret =3D H_PARAMETER; + goto unmap_out; + } + memcpy(pdst, psrc, len); + cpu_physical_memory_unmap(psrc, len, 0, len); + } else if (flags & H_ZERO_PAGE) { + memset(pdst, 0, len); /* Just clear the destination page = */ + } + + if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) !=3D 0) { + kvmppc_dcbst_range(cpu, pdst, len); + } + if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { + if (kvm_enabled()) { + kvmppc_icbi_range(cpu, pdst, len); + } else { + tb_flush(CPU(cpu)); + } + } + +unmap_out: + cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); + return ret; +} + +#define FLAGS_REGISTER_VPA 0x0000200000000000ULL +#define FLAGS_REGISTER_DTL 0x0000400000000000ULL +#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL +#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL +#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL +#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL + +static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + uint16_t size; + uint8_t tmp; + + if (vpa =3D=3D 0) { + hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); + return H_HARDWARE; + } + + if (vpa % env->dcache_line_size) { + return H_PARAMETER; + } + /* FIXME: bounds check the address */ + + size =3D lduw_be_phys(cs->as, vpa + 0x4); + + if (size < VPA_MIN_SIZE) { + return H_PARAMETER; + } + + /* VPA is not allowed to cross a page boundary */ + if ((vpa / 4096) !=3D ((vpa + size - 1) / 4096)) { + return H_PARAMETER; + } + + spapr_cpu->vpa_addr =3D vpa; + + tmp =3D ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET= ); + tmp |=3D VPA_SHARED_PROC_VAL; + stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); + + return H_SUCCESS; +} + +static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) +{ + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + if (spapr_cpu->slb_shadow_addr) { + return H_RESOURCE; + } + + if (spapr_cpu->dtl_addr) { + return H_RESOURCE; + } + + spapr_cpu->vpa_addr =3D 0; + return H_SUCCESS; +} + +static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) +{ + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + uint32_t size; + + if (addr =3D=3D 0) { + hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); + return H_HARDWARE; + } + + size =3D ldl_be_phys(CPU(cpu)->as, addr + 0x4); + if (size < 0x8) { + return H_PARAMETER; + } + + if ((addr / 4096) !=3D ((addr + size - 1) / 4096)) { + return H_PARAMETER; + } + + if (!spapr_cpu->vpa_addr) { + return H_RESOURCE; + } + + spapr_cpu->slb_shadow_addr =3D addr; + spapr_cpu->slb_shadow_size =3D size; + + return H_SUCCESS; +} + +static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong ad= dr) +{ + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + spapr_cpu->slb_shadow_addr =3D 0; + spapr_cpu->slb_shadow_size =3D 0; + return H_SUCCESS; +} + +static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) +{ + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + uint32_t size; + + if (addr =3D=3D 0) { + hcall_dprintf("Can't cope with DTL at logical 0\n"); + return H_HARDWARE; + } + + size =3D ldl_be_phys(CPU(cpu)->as, addr + 0x4); + + if (size < 48) { + return H_PARAMETER; + } + + if (!spapr_cpu->vpa_addr) { + return H_RESOURCE; + } + + spapr_cpu->dtl_addr =3D addr; + spapr_cpu->dtl_size =3D size; + + return H_SUCCESS; +} + +static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) +{ + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + spapr_cpu->dtl_addr =3D 0; + spapr_cpu->dtl_size =3D 0; + + return H_SUCCESS; +} + +static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spa= pr, + target_ulong opcode, target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong procno =3D args[1]; + target_ulong vpa =3D args[2]; + target_ulong ret =3D H_PARAMETER; + PowerPCCPU *tcpu; + + tcpu =3D spapr_find_cpu(procno); + if (!tcpu) { + return H_PARAMETER; + } + + switch (flags) { + case FLAGS_REGISTER_VPA: + ret =3D register_vpa(tcpu, vpa); + break; + + case FLAGS_DEREGISTER_VPA: + ret =3D deregister_vpa(tcpu, vpa); + break; + + case FLAGS_REGISTER_SLBSHADOW: + ret =3D register_slb_shadow(tcpu, vpa); + break; + + case FLAGS_DEREGISTER_SLBSHADOW: + ret =3D deregister_slb_shadow(tcpu, vpa); + break; + + case FLAGS_REGISTER_DTL: + ret =3D register_dtl(tcpu, vpa); + break; + + case FLAGS_DEREGISTER_DTL: + ret =3D deregister_dtl(tcpu, vpa); + break; + } + + return ret; +} + +static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + env->msr |=3D (1ULL << MSR_EE); + hreg_compute_hflags(env); + + if (spapr_cpu->prod) { + spapr_cpu->prod =3D false; + return H_SUCCESS; + } + + if (!cpu_has_work(cs)) { + cs->halted =3D 1; + cs->exception_index =3D EXCP_HLT; + cs->exit_request =3D 1; + } + + return H_SUCCESS; +} + +/* + * Confer to self, aka join. Cede could use the same pattern as well, if + * EXCP_HLT can be changed to ECXP_HALTED. + */ +static target_ulong h_confer_self(PowerPCCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + if (spapr_cpu->prod) { + spapr_cpu->prod =3D false; + return H_SUCCESS; + } + cs->halted =3D 1; + cs->exception_index =3D EXCP_HALTED; + cs->exit_request =3D 1; + + return H_SUCCESS; +} + +static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + CPUState *cs; + bool last_unjoined =3D true; + + if (env->msr & (1ULL << MSR_EE)) { + return H_BAD_MODE; + } + + /* + * Must not join the last CPU running. Interestingly, no such restrict= ion + * for H_CONFER-to-self, but that is probably not intended to be used + * when H_JOIN is available. + */ + CPU_FOREACH(cs) { + PowerPCCPU *c =3D POWERPC_CPU(cs); + CPUPPCState *e =3D &c->env; + if (c =3D=3D cpu) { + continue; + } + + /* Don't have a way to indicate joined, so use halted && MSR[EE]= =3D0 */ + if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { + last_unjoined =3D false; + break; + } + } + if (last_unjoined) { + return H_CONTINUE; + } + + return h_confer_self(cpu); +} + +static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_long target =3D args[0]; + uint32_t dispatch =3D args[1]; + CPUState *cs =3D CPU(cpu); + SpaprCpuState *spapr_cpu; + + /* + * -1 means confer to all other CPUs without dispatch counter check, + * otherwise it's a targeted confer. + */ + if (target !=3D -1) { + PowerPCCPU *target_cpu =3D spapr_find_cpu(target); + uint32_t target_dispatch; + + if (!target_cpu) { + return H_PARAMETER; + } + + /* + * target =3D=3D self is a special case, we wait until prodded, wi= thout + * dispatch counter check. + */ + if (cpu =3D=3D target_cpu) { + return h_confer_self(cpu); + } + + spapr_cpu =3D spapr_cpu_state(target_cpu); + if (!spapr_cpu->vpa_addr || ((dispatch & 1) =3D=3D 0)) { + return H_SUCCESS; + } + + target_dispatch =3D ldl_be_phys(cs->as, + spapr_cpu->vpa_addr + VPA_DISPATCH_COUNT= ER); + if (target_dispatch !=3D dispatch) { + return H_SUCCESS; + } + + /* + * The targeted confer does not do anything special beyond yielding + * the current vCPU, but even this should be better than nothing. + * At least for single-threaded tcg, it gives the target a chance = to + * run before we run again. Multi-threaded tcg does not really do + * anything with EXCP_YIELD yet. + */ + } + + cs->exception_index =3D EXCP_YIELD; + cs->exit_request =3D 1; + cpu_loop_exit(cs); + + return H_SUCCESS; +} + +static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_long target =3D args[0]; + PowerPCCPU *tcpu; + CPUState *cs; + SpaprCpuState *spapr_cpu; + + tcpu =3D spapr_find_cpu(target); + cs =3D CPU(tcpu); + if (!cs) { + return H_PARAMETER; + } + + spapr_cpu =3D spapr_cpu_state(tcpu); + spapr_cpu->prod =3D true; + cs->halted =3D 0; + qemu_cpu_kick(cs); + + return H_SUCCESS; +} + +static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong rtas_r3 =3D args[0]; + uint32_t token =3D rtas_ld(rtas_r3, 0); + uint32_t nargs =3D rtas_ld(rtas_r3, 1); + uint32_t nret =3D rtas_ld(rtas_r3, 2); + + return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, + nret, rtas_r3 + 12 + 4*nargs); +} + +static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spa= pr, + target_ulong opcode, target_ulong *args) +{ + CPUState *cs =3D CPU(cpu); + target_ulong size =3D args[0]; + target_ulong addr =3D args[1]; + + switch (size) { + case 1: + args[0] =3D ldub_phys(cs->as, addr); + return H_SUCCESS; + case 2: + args[0] =3D lduw_phys(cs->as, addr); + return H_SUCCESS; + case 4: + args[0] =3D ldl_phys(cs->as, addr); + return H_SUCCESS; + case 8: + args[0] =3D ldq_phys(cs->as, addr); + return H_SUCCESS; + } + return H_PARAMETER; +} + +static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *sp= apr, + target_ulong opcode, target_ulong *arg= s) +{ + CPUState *cs =3D CPU(cpu); + + target_ulong size =3D args[0]; + target_ulong addr =3D args[1]; + target_ulong val =3D args[2]; + + switch (size) { + case 1: + stb_phys(cs->as, addr, val); + return H_SUCCESS; + case 2: + stw_phys(cs->as, addr, val); + return H_SUCCESS; + case 4: + stl_phys(cs->as, addr, val); + return H_SUCCESS; + case 8: + stq_phys(cs->as, addr, val); + return H_SUCCESS; + } + return H_PARAMETER; +} + +static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *sp= apr, + target_ulong opcode, target_ulong *arg= s) +{ + CPUState *cs =3D CPU(cpu); + + target_ulong dst =3D args[0]; /* Destination address */ + target_ulong src =3D args[1]; /* Source address */ + target_ulong esize =3D args[2]; /* Element size (0=3D1,1=3D2,2=3D4,3= =3D8) */ + target_ulong count =3D args[3]; /* Element count */ + target_ulong op =3D args[4]; /* 0 =3D copy, 1 =3D invert */ + uint64_t tmp; + unsigned int mask =3D (1 << esize) - 1; + int step =3D 1 << esize; + + if (count > 0x80000000) { + return H_PARAMETER; + } + + if ((dst & mask) || (src & mask) || (op > 1)) { + return H_PARAMETER; + } + + if (dst >=3D src && dst < (src + (count << esize))) { + dst =3D dst + ((count - 1) << esize); + src =3D src + ((count - 1) << esize); + step =3D -step; + } + + while (count--) { + switch (esize) { + case 0: + tmp =3D ldub_phys(cs->as, src); + break; + case 1: + tmp =3D lduw_phys(cs->as, src); + break; + case 2: + tmp =3D ldl_phys(cs->as, src); + break; + case 3: + tmp =3D ldq_phys(cs->as, src); + break; + default: + return H_PARAMETER; + } + if (op =3D=3D 1) { + tmp =3D ~tmp; + } + switch (esize) { + case 0: + stb_phys(cs->as, dst, tmp); + break; + case 1: + stw_phys(cs->as, dst, tmp); + break; + case 2: + stl_phys(cs->as, dst, tmp); + break; + case 3: + stq_phys(cs->as, dst, tmp); + break; + } + dst =3D dst + step; + src =3D src + step; + } + + return H_SUCCESS; +} + +static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spa= pr, + target_ulong opcode, target_ulong *args) +{ + /* Nothing to do on emulation, KVM will trap this in the kernel */ + return H_SUCCESS; +} + +static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spa= pr, + target_ulong opcode, target_ulong *args) +{ + /* Nothing to do on emulation, KVM will trap this in the kernel */ + return H_SUCCESS; +} + +static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong mflags, + target_ulong value1, + target_ulong value2) +{ + if (value1) { + return H_P3; + } + if (value2) { + return H_P4; + } + + switch (mflags) { + case H_SET_MODE_ENDIAN_BIG: + spapr_set_all_lpcrs(0, LPCR_ILE); + spapr_pci_switch_vga(spapr, true); + return H_SUCCESS; + + case H_SET_MODE_ENDIAN_LITTLE: + spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); + spapr_pci_switch_vga(spapr, false); + return H_SUCCESS; + } + + return H_UNSUPPORTED_FLAG; +} + +static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, + target_ulong mflag= s, + target_ulong value= 1, + target_ulong value= 2) +{ + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + + if (!(pcc->insns_flags2 & PPC2_ISA207S)) { + return H_P2; + } + if (value1) { + return H_P3; + } + if (value2) { + return H_P4; + } + + if (mflags =3D=3D AIL_RESERVED) { + return H_UNSUPPORTED_FLAG; + } + + spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); + + return H_SUCCESS; +} + +static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong resource =3D args[1]; + target_ulong ret =3D H_P2; + + switch (resource) { + case H_SET_MODE_RESOURCE_LE: + ret =3D h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[= 3]); + break; + case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: + ret =3D h_set_mode_resource_addr_trans_mode(cpu, args[0], + args[2], args[3]); + break; + } + + return ret; +} + +static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%= s\n", + opcode, " (H_CLEAN_SLB)"); + return H_FUNCTION; +} + +static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *s= papr, + target_ulong opcode, target_ulong *ar= gs) +{ + qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%= s\n", + opcode, " (H_INVALIDATE_PID)"); + return H_FUNCTION; +} + +static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, + uint64_t patbe_old, uint64_t patbe_= new) +{ + /* + * We have 4 Options: + * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing + * HASH->RADIX : Free HPT + * RADIX->HASH : Allocate HPT + * NOTHING->HASH : Allocate HPT + * Note: NOTHING implies the case where we said the guest could choose + * later and so assumed radix and now it's called H_REG_PROC_TBL + */ + + if ((patbe_old & PATE1_GR) =3D=3D (patbe_new & PATE1_GR)) { + /* We assume RADIX, so this catches all the "Do Nothing" cases */ + } else if (!(patbe_old & PATE1_GR)) { + /* HASH->RADIX : Free HPT */ + spapr_free_hpt(spapr); + } else if (!(patbe_new & PATE1_GR)) { + /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ + spapr_setup_hpt(spapr); + } + return; +} + +#define FLAGS_MASK 0x01FULL +#define FLAG_MODIFY 0x10 +#define FLAG_REGISTER 0x08 +#define FLAG_RADIX 0x04 +#define FLAG_HASH_PROC_TBL 0x02 +#define FLAG_GTSE 0x01 + +static target_ulong h_register_process_table(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong proc_tbl =3D args[1]; + target_ulong page_size =3D args[2]; + target_ulong table_size =3D args[3]; + target_ulong update_lpcr =3D 0; + uint64_t cproc; + + if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ + return H_PARAMETER; + } + if (flags & FLAG_MODIFY) { + if (flags & FLAG_REGISTER) { + if (flags & FLAG_RADIX) { /* Register new RADIX process table = */ + if (proc_tbl & 0xfff || proc_tbl >> 60) { + return H_P2; + } else if (page_size) { + return H_P3; + } else if (table_size > 24) { + return H_P4; + } + cproc =3D PATE1_GR | proc_tbl | table_size; + } else { /* Register new HPT process table */ + if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tab= les */ + /* TODO - Not Supported */ + /* Technically caused by flag bits =3D> H_PARAMETER */ + return H_PARAMETER; + } else { /* Hash with SLB */ + if (proc_tbl >> 38) { + return H_P2; + } else if (page_size & ~0x7) { + return H_P3; + } else if (table_size > 24) { + return H_P4; + } + } + cproc =3D (proc_tbl << 25) | page_size << 5 | table_size; + } + + } else { /* Deregister current process table */ + /* + * Set to benign value: (current GR) | 0. This allows + * deregistration in KVM to succeed even if the radix bit + * in flags doesn't match the radix bit in the old PATE. + */ + cproc =3D spapr->patb_entry & PATE1_GR; + } + } else { /* Maintain current registration */ + if (!(flags & FLAG_RADIX) !=3D !(spapr->patb_entry & PATE1_GR)) { + /* Technically caused by flag bits =3D> H_PARAMETER */ + return H_PARAMETER; /* Existing Process Table Mismatch */ + } + cproc =3D spapr->patb_entry; + } + + /* Check if we need to setup OR free the hpt */ + spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); + + spapr->patb_entry =3D cproc; /* Save new process table */ + + /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ + if (flags & FLAG_RADIX) /* Radix must use process tables, also set= HR */ + update_lpcr |=3D (LPCR_UPRT | LPCR_HR); + else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ + update_lpcr |=3D LPCR_UPRT; + if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ + update_lpcr |=3D LPCR_GTSE; + + spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); + + if (kvm_enabled()) { + return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, + flags & FLAG_GTSE, cproc); + } + return H_SUCCESS; +} + +#define H_SIGNAL_SYS_RESET_ALL -1 +#define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 + +static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, target_ulong *= args) +{ + target_long target =3D args[0]; + CPUState *cs; + + if (target < 0) { + /* Broadcast */ + if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { + return H_PARAMETER; + } + + CPU_FOREACH(cs) { + PowerPCCPU *c =3D POWERPC_CPU(cs); + + if (target =3D=3D H_SIGNAL_SYS_RESET_ALLBUTSELF) { + if (c =3D=3D cpu) { + continue; + } + } + run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); + } + return H_SUCCESS; + + } else { + /* Unicast */ + cs =3D CPU(spapr_find_cpu(target)); + if (cs) { + run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); + return H_SUCCESS; + } + return H_PARAMETER; + } +} + +/* Returns either a logical PVR or zero if none was found */ +static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, + target_ulong *addr, bool *raw_mode_supported) +{ + bool explicit_match =3D false; /* Matched the CPU's real PVR */ + uint32_t best_compat =3D 0; + int i; + + /* + * We scan the supplied table of PVRs looking for two things + * 1. Is our real CPU PVR in the list? + * 2. What's the "best" listed logical PVR + */ + for (i =3D 0; i < 512; ++i) { + uint32_t pvr, pvr_mask; + + pvr_mask =3D ldl_be_phys(&address_space_memory, *addr); + pvr =3D ldl_be_phys(&address_space_memory, *addr + 4); + *addr +=3D 8; + + if (~pvr_mask & pvr) { + break; /* Terminator record */ + } + + if ((cpu->env.spr[SPR_PVR] & pvr_mask) =3D=3D (pvr & pvr_mask)) { + explicit_match =3D true; + } else { + if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { + best_compat =3D pvr; + } + } + } + + *raw_mode_supported =3D explicit_match; + + /* Parsing finished */ + trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); + + return best_compat; +} + +static +target_ulong do_client_architecture_support(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong vec, + target_ulong fdt_bufsize) +{ + target_ulong ov_table; /* Working address in data buffer */ + uint32_t cas_pvr; + SpaprOptionVector *ov1_guest, *ov5_guest; + bool guest_radix; + bool raw_mode_supported =3D false; + bool guest_xive; + CPUState *cs; + void *fdt; + uint32_t max_compat =3D spapr->max_compat_pvr; + + /* CAS is supposed to be called early when only the boot vCPU is activ= e. */ + CPU_FOREACH(cs) { + if (cs =3D=3D CPU(cpu)) { + continue; + } + if (!cs->halted) { + warn_report("guest has multiple active vCPUs at CAS, which is = not allowed"); + return H_MULTI_THREADS_ACTIVE; + } + } + + cas_pvr =3D cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); + if (!cas_pvr && (!raw_mode_supported || max_compat)) { + /* + * We couldn't find a suitable compatibility mode, and either + * the guest doesn't support "raw" mode for this CPU, or "raw" + * mode is disabled because a maximum compat mode is set. + */ + error_report("Couldn't negotiate a suitable PVR during CAS"); + return H_HARDWARE; + } + + /* Update CPUs */ + if (cpu->compat_pvr !=3D cas_pvr) { + Error *local_err =3D NULL; + + if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { + /* We fail to set compat mode (likely because running with KVM= PR), + * but maybe we can fallback to raw mode if the guest supports= it. + */ + if (!raw_mode_supported) { + error_report_err(local_err); + return H_HARDWARE; + } + error_free(local_err); + } + } + + /* For the future use: here @ov_table points to the first option vecto= r */ + ov_table =3D vec; + + ov1_guest =3D spapr_ovec_parse_vector(ov_table, 1); + if (!ov1_guest) { + warn_report("guest didn't provide option vector 1"); + return H_PARAMETER; + } + ov5_guest =3D spapr_ovec_parse_vector(ov_table, 5); + if (!ov5_guest) { + spapr_ovec_cleanup(ov1_guest); + warn_report("guest didn't provide option vector 5"); + return H_PARAMETER; + } + if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { + error_report("guest requested hash and radix MMU, which is invalid= ."); + exit(EXIT_FAILURE); + } + if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { + error_report("guest requested an invalid interrupt mode"); + exit(EXIT_FAILURE); + } + + guest_radix =3D spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); + + guest_xive =3D spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); + + /* + * HPT resizing is a bit of a special case, because when enabled + * we assume an HPT guest will support it until it says it + * doesn't, instead of assuming it won't support it until it says + * it does. Strictly speaking that approach could break for + * guests which don't make a CAS call, but those are so old we + * don't care about them. Without that assumption we'd have to + * make at least a temporary allocation of an HPT sized for max + * memory, which could be impossibly difficult under KVM HV if + * maxram is large. + */ + if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { + int maxshift =3D spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxra= m_size); + + if (spapr->resize_hpt =3D=3D SPAPR_RESIZE_HPT_REQUIRED) { + error_report( + "h_client_architecture_support: Guest doesn't support HPT = resizing, but resize-hpt=3Drequired"); + exit(1); + } + + if (spapr->htab_shift < maxshift) { + /* Guest doesn't know about HPT resizing, so we + * pre-emptively resize for the maximum permitted RAM. At + * the point this is called, nothing should have been + * entered into the existing HPT */ + spapr_reallocate_hpt(spapr, maxshift, &error_fatal); + push_sregs_to_kvm_pr(spapr); + } + } + + /* NOTE: there are actually a number of ov5 bits where input from the + * guest is always zero, and the platform/QEMU enables them independen= tly + * of guest input. To model these properly we'd want some sort of mask, + * but since they only currently apply to memory migration as defined + * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need + * to worry about this for now. + */ + + /* full range of negotiated ov5 capabilities */ + spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); + spapr_ovec_cleanup(ov5_guest); + + if (guest_radix) { + if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { + error_report("Guest requested unavailable MMU mode (radix)."); + exit(EXIT_FAILURE); + } + } else { + if (kvm_enabled() && kvmppc_has_cap_mmu_radix() + && !kvmppc_has_cap_mmu_hash_v3()) { + error_report("Guest requested unavailable MMU mode (hash)."); + exit(EXIT_FAILURE); + } + } + spapr->cas_pre_isa3_guest =3D !spapr_ovec_test(ov1_guest, OV1_PPC_3_00= ); + spapr_ovec_cleanup(ov1_guest); + + /* + * Ensure the guest asks for an interrupt mode we support; + * otherwise terminate the boot. + */ + if (guest_xive) { + if (!spapr->irq->xive) { + error_report( +"Guest requested unavailable interrupt mode (XIVE), try the ic-mode=3Dxive= or ic-mode=3Ddual machine property"); + exit(EXIT_FAILURE); + } + } else { + if (!spapr->irq->xics) { + error_report( +"Guest requested unavailable interrupt mode (XICS), either don't set the i= c-mode machine property or try ic-mode=3Dxics or ic-mode=3Ddual"); + exit(EXIT_FAILURE); + } + } + + spapr_irq_update_active_intc(spapr); + + /* + * Process all pending hot-plug/unplug requests now. An updated full + * rendered FDT will be returned to the guest. + */ + spapr_drc_reset_all(spapr); + spapr_clear_pending_hotplug_events(spapr); + + /* + * If spapr_machine_reset() did not set up a HPT but one is necessary + * (because the guest isn't going to use radix) then set it up here. + */ + if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { + /* legacy hash or new hash: */ + spapr_setup_hpt(spapr); + } + + fdt =3D spapr_build_fdt(spapr, false, fdt_bufsize); + + g_free(spapr->fdt_blob); + spapr->fdt_size =3D fdt_totalsize(fdt); + spapr->fdt_initial_size =3D spapr->fdt_size; + spapr->fdt_blob =3D fdt; + + return H_SUCCESS; +} + +static target_ulong h_client_architecture_support(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong vec =3D ppc64_phys_to_real(args[0]); + target_ulong fdt_buf =3D args[1]; + target_ulong fdt_bufsize =3D args[2]; + target_ulong ret; + SpaprDeviceTreeUpdateHeader hdr =3D { .version_id =3D 1 }; + + if (fdt_bufsize < sizeof(hdr)) { + error_report("SLOF provided insufficient CAS buffer " + TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)= ); + exit(EXIT_FAILURE); + } + + fdt_bufsize -=3D sizeof(hdr); + + ret =3D do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); + if (ret =3D=3D H_SUCCESS) { + _FDT((fdt_pack(spapr->fdt_blob))); + spapr->fdt_size =3D fdt_totalsize(spapr->fdt_blob); + spapr->fdt_initial_size =3D spapr->fdt_size; + + cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); + cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, + spapr->fdt_size); + trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); + } + + return ret; +} + +static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + uint64_t characteristics =3D H_CPU_CHAR_HON_BRANCH_HINTS & + ~H_CPU_CHAR_THR_RECONF_TRIG; + uint64_t behaviour =3D H_CPU_BEHAV_FAVOUR_SECURITY; + uint8_t safe_cache =3D spapr_get_cap(spapr, SPAPR_CAP_CFPC); + uint8_t safe_bounds_check =3D spapr_get_cap(spapr, SPAPR_CAP_SBBC); + uint8_t safe_indirect_branch =3D spapr_get_cap(spapr, SPAPR_CAP_IBS); + uint8_t count_cache_flush_assist =3D spapr_get_cap(spapr, + SPAPR_CAP_CCF_ASSIST); + + switch (safe_cache) { + case SPAPR_CAP_WORKAROUND: + characteristics |=3D H_CPU_CHAR_L1D_FLUSH_ORI30; + characteristics |=3D H_CPU_CHAR_L1D_FLUSH_TRIG2; + characteristics |=3D H_CPU_CHAR_L1D_THREAD_PRIV; + behaviour |=3D H_CPU_BEHAV_L1D_FLUSH_PR; + break; + case SPAPR_CAP_FIXED: + break; + default: /* broken */ + assert(safe_cache =3D=3D SPAPR_CAP_BROKEN); + behaviour |=3D H_CPU_BEHAV_L1D_FLUSH_PR; + break; + } + + switch (safe_bounds_check) { + case SPAPR_CAP_WORKAROUND: + characteristics |=3D H_CPU_CHAR_SPEC_BAR_ORI31; + behaviour |=3D H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; + break; + case SPAPR_CAP_FIXED: + break; + default: /* broken */ + assert(safe_bounds_check =3D=3D SPAPR_CAP_BROKEN); + behaviour |=3D H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; + break; + } + + switch (safe_indirect_branch) { + case SPAPR_CAP_FIXED_NA: + break; + case SPAPR_CAP_FIXED_CCD: + characteristics |=3D H_CPU_CHAR_CACHE_COUNT_DIS; + break; + case SPAPR_CAP_FIXED_IBS: + characteristics |=3D H_CPU_CHAR_BCCTRL_SERIALISED; + break; + case SPAPR_CAP_WORKAROUND: + behaviour |=3D H_CPU_BEHAV_FLUSH_COUNT_CACHE; + if (count_cache_flush_assist) { + characteristics |=3D H_CPU_CHAR_BCCTR_FLUSH_ASSIST; + } + break; + default: /* broken */ + assert(safe_indirect_branch =3D=3D SPAPR_CAP_BROKEN); + break; + } + + args[0] =3D characteristics; + args[1] =3D behaviour; + return H_SUCCESS; +} + +static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong dt =3D ppc64_phys_to_real(args[0]); + struct fdt_header hdr =3D { 0 }; + unsigned cb; + SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + void *fdt; + + cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); + cb =3D fdt32_to_cpu(hdr.totalsize); + + if (!smc->update_dt_enabled) { + return H_SUCCESS; + } + + /* Check that the fdt did not grow out of proportion */ + if (cb > spapr->fdt_initial_size * 2) { + trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, + fdt32_to_cpu(hdr.magic)); + return H_PARAMETER; + } + + fdt =3D g_malloc0(cb); + cpu_physical_memory_read(dt, fdt, cb); + + /* Check the fdt consistency */ + if (fdt_check_full(fdt, cb)) { + trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, + fdt32_to_cpu(hdr.magic)); + return H_PARAMETER; + } + + g_free(spapr->fdt_blob); + spapr->fdt_size =3D cb; + spapr->fdt_blob =3D fdt; + trace_spapr_update_dt(cb); + + return H_SUCCESS; +} + +static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; +static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCA= LL_BASE + 1]; +static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE)= / 4 + 1]; + +void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) +{ + spapr_hcall_fn *slot; + + if (opcode <=3D MAX_HCALL_OPCODE) { + assert((opcode & 0x3) =3D=3D 0); + + slot =3D &papr_hypercall_table[opcode / 4]; + } else if (opcode >=3D SVM_HCALL_BASE && opcode <=3D SVM_HCALL_MAX) { + /* we only have SVM-related hcall numbers assigned in multiples of= 4 */ + assert((opcode & 0x3) =3D=3D 0); + + slot =3D &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; + } else { + assert((opcode >=3D KVMPPC_HCALL_BASE) && (opcode <=3D KVMPPC_HCAL= L_MAX)); + + slot =3D &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; + } + + assert(!(*slot)); + *slot =3D fn; +} + +target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, + target_ulong *args) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + + if ((opcode <=3D MAX_HCALL_OPCODE) + && ((opcode & 0x3) =3D=3D 0)) { + spapr_hcall_fn fn =3D papr_hypercall_table[opcode / 4]; + + if (fn) { + return fn(cpu, spapr, opcode, args); + } + } else if ((opcode >=3D SVM_HCALL_BASE) && + (opcode <=3D SVM_HCALL_MAX)) { + spapr_hcall_fn fn =3D svm_hypercall_table[(opcode - SVM_HCALL_BASE= ) / 4]; + + if (fn) { + return fn(cpu, spapr, opcode, args); + } + } else if ((opcode >=3D KVMPPC_HCALL_BASE) && + (opcode <=3D KVMPPC_HCALL_MAX)) { + spapr_hcall_fn fn =3D kvmppc_hypercall_table[opcode - KVMPPC_HCALL= _BASE]; + + if (fn) { + return fn(cpu, spapr, opcode, args); + } + } + + qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx = "\n", + opcode); + return H_FUNCTION; +} + +static void hypercall_register_types(void) +{ + /* hcall-pft */ + spapr_register_hypercall(H_ENTER, h_enter); + spapr_register_hypercall(H_REMOVE, h_remove); + spapr_register_hypercall(H_PROTECT, h_protect); + spapr_register_hypercall(H_READ, h_read); + + /* hcall-bulk */ + spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); + + /* hcall-hpt-resize */ + spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); + spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); + + /* hcall-splpar */ + spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); + spapr_register_hypercall(H_CEDE, h_cede); + spapr_register_hypercall(H_CONFER, h_confer); + spapr_register_hypercall(H_PROD, h_prod); + + /* hcall-join */ + spapr_register_hypercall(H_JOIN, h_join); + + spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); + + /* processor register resource access h-calls */ + spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); + spapr_register_hypercall(H_SET_DABR, h_set_dabr); + spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); + spapr_register_hypercall(H_PAGE_INIT, h_page_init); + spapr_register_hypercall(H_SET_MODE, h_set_mode); + + /* In Memory Table MMU h-calls */ + spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); + spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); + spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table= ); + + /* hcall-get-cpu-characteristics */ + spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, + h_get_cpu_characteristics); + + /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenci= ate + * here between the "CI" and the "CACHE" variants, they will use whate= ver + * mapping attributes qemu is using. When using KVM, the kernel will + * enforce the attributes more strongly + */ + spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); + spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); + spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); + spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); + spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); + spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); + spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); + + /* qemu/KVM-PPC specific hcalls */ + spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); + + /* ibm,client-architecture-support support */ + spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); + + spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); +} + +type_init(hypercall_register_types) --=20 2.17.1 From nobody Mon Feb 9 15:24:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 22 Apr 2021 13:12:47 -0700 (PDT) Received: from localhost ([::1]:47342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZfgs-0007uG-4S for importer@patchew.org; Thu, 22 Apr 2021 16:12:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZfL6-00067W-LY; Thu, 22 Apr 2021 15:50:18 -0400 Received: from [201.28.113.2] (port=23502 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZfL0-0002SN-3e; Thu, 22 Apr 2021 15:50:14 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Thu, 22 Apr 2021 16:31:39 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id EC2C8800BEE; Thu, 22 Apr 2021 16:31:38 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH 3/4] hw/ppc: updated build rules to use new file Date: Thu, 22 Apr 2021 16:31:30 -0300 Message-Id: <20210422193131.22560-4-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> References: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 22 Apr 2021 19:31:39.0102 (UTC) FILETIME=[1D976FE0:01D737AE] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, lucas.araujo@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Updated meson.build to compile spapr_hcall_tcg_stub.c instead of spapr_hcall.c when disable-tcg option is used Signed-off-by: Lucas Mateus Castro (alqotel) --- hw/ppc/meson.build | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 218631c883..8b9b537c37 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -14,7 +14,6 @@ ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files( 'spapr_caps.c', 'spapr_vio.c', 'spapr_events.c', - 'spapr_hcall.c', 'spapr_iommu.c', 'spapr_rtas.c', 'spapr_pci.c', @@ -29,6 +28,15 @@ ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files( 'spapr_numa.c', 'pef.c', )) +tcg_ss =3D ss.source_set() +tcg_ss.add(when: 'CONFIG_TCG', if_true: files( + 'spapr_hcall.c', +), if_false: files( + 'spapr_hcall_tcg_stub.c', +)) + +ppc_ss.add_all(when: 'CONFIG_PSERIES', if_true: tcg_ss) + ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c')) ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_LINUX'], if_true: files( 'spapr_pci_vfio.c', --=20 2.17.1 From nobody Mon Feb 9 15:24:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 22 Apr 2021 13:03:26 -0700 (PDT) Received: from localhost ([::1]:57670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZfXo-0000Dl-Vb for importer@patchew.org; Thu, 22 Apr 2021 16:03:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZfLA-0006A3-UI; Thu, 22 Apr 2021 15:50:22 -0400 Received: from [201.28.113.2] (port=23502 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZfL8-0002SN-Py; Thu, 22 Apr 2021 15:50:20 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Thu, 22 Apr 2021 16:31:39 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id 6F9DC800BEE; Thu, 22 Apr 2021 16:31:39 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH 4/4] target/ppc: transfered functions to non-tcg-only files Date: Thu, 22 Apr 2021 16:31:31 -0300 Message-Id: <20210422193131.22560-5-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> References: <20210422193131.22560-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 22 Apr 2021 19:31:39.0602 (UTC) FILETIME=[1DE3BB20:01D737AE] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, lucas.araujo@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" moved the functions ppc_store_lpcr and ppc_hash64_filter_pagesizes to common-misc.c so they can be used in a disable-tcg build and added the necessary includes to files that call them. Created ppc_(store|load)_vscr to be used by both tcg and kvm. Signed-off-by: Lucas Mateus Castro (alqotel) --- hw/ppc/spapr.c | 1 + hw/ppc/spapr_caps.c | 1 + hw/ppc/spapr_cpu_core.c | 1 + hw/ppc/spapr_hcall.c | 1 + hw/ppc/spapr_hcall_tcg_stub.c | 1 + hw/ppc/spapr_rtas.c | 1 + target/ppc/common-misc.c | 86 +++++++++++++++++++++++++++++++++++ target/ppc/common-misc.h | 13 ++++++ target/ppc/int_helper.c | 10 ++-- target/ppc/meson.build | 1 + target/ppc/mmu-hash64.c | 67 +-------------------------- target/ppc/mmu-hash64.h | 4 -- 12 files changed, 110 insertions(+), 77 deletions(-) create mode 100644 target/ppc/common-misc.c create mode 100644 target/ppc/common-misc.h diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e4be00b732..f41accd5ec 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -52,6 +52,7 @@ #include "mmu-hash64.h" #include "mmu-book3s-v3.h" #include "cpu-models.h" +#include "common-misc.h" #include "hw/core/cpu.h" =20 #include "hw/boards.h" diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 9ea7ddd1e9..1bf55459b0 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -34,6 +34,7 @@ #include "kvm_ppc.h" #include "migration/vmstate.h" #include "sysemu/tcg.h" +#include "common-misc.h" =20 #include "hw/ppc/spapr.h" =20 diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 4f316a6f9d..62f19700f5 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -24,6 +24,7 @@ #include "sysemu/reset.h" #include "sysemu/hw_accel.h" #include "qemu/error-report.h" +#include "common-misc.h" =20 static void spapr_reset_vcpu(PowerPCCPU *cpu) { diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..e8a9bfbcbb 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -20,6 +20,7 @@ #include "hw/ppc/spapr_ovec.h" #include "mmu-book3s-v3.h" #include "hw/mem/memory-device.h" +#include "common-misc.h" =20 static bool has_spr(PowerPCCPU *cpu, int spr) { diff --git a/hw/ppc/spapr_hcall_tcg_stub.c b/hw/ppc/spapr_hcall_tcg_stub.c index 6682279b6e..7dca9ff2a9 100644 --- a/hw/ppc/spapr_hcall_tcg_stub.c +++ b/hw/ppc/spapr_hcall_tcg_stub.c @@ -20,6 +20,7 @@ #include "hw/ppc/spapr_ovec.h" #include "mmu-book3s-v3.h" #include "hw/mem/memory-device.h" +#include "common-misc.h" =20 static bool has_spr(PowerPCCPU *cpu, int spr) { diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8a79f9c628..8c8c50e498 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -35,6 +35,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" #include "kvm_ppc.h" +#include "common-misc.h" =20 #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" diff --git a/target/ppc/common-misc.c b/target/ppc/common-misc.c new file mode 100644 index 0000000000..5e860d6245 --- /dev/null +++ b/target/ppc/common-misc.c @@ -0,0 +1,86 @@ +#include "qemu/osdep.h" +#include "common-misc.h" +#include "mmu-hash64.h" +#include "fpu/softfloat-helpers.h" + +void ppc_store_vscr(CPUPPCState *env, uint64_t vscr) +{ + env->vscr =3D vscr & ~(1u << VSCR_SAT); + /* Which bit we set is completely arbitrary, but clear the rest. */ + env->vscr_sat.u64[0] =3D vscr & (1u << VSCR_SAT); + env->vscr_sat.u64[1] =3D 0; + set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); +} + +uint32_t ppc_load_vscr(CPUPPCState *env) +{ + uint32_t sat =3D (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) !=3D 0; + return env->vscr | (sat << VSCR_SAT); +} + +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) +{ + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *env =3D &cpu->env; + + env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; +} + +void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, + bool (*cb)(void *, uint32_t, uint32_t), + void *opaque) +{ + PPCHash64Options *opts =3D cpu->hash64_opts; + int i; + int n =3D 0; + bool ci_largepage =3D false; + + assert(opts); + + n =3D 0; + for (i =3D 0; i < ARRAY_SIZE(opts->sps); i++) { + PPCHash64SegmentPageSizes *sps =3D &opts->sps[i]; + int j; + int m =3D 0; + + assert(n <=3D i); + + if (!sps->page_shift) { + break; + } + + for (j =3D 0; j < ARRAY_SIZE(sps->enc); j++) { + PPCHash64PageSize *ps =3D &sps->enc[j]; + + assert(m <=3D j); + if (!ps->page_shift) { + break; + } + + if (cb(opaque, sps->page_shift, ps->page_shift)) { + if (ps->page_shift >=3D 16) { + ci_largepage =3D true; + } + sps->enc[m++] =3D *ps; + } + } + + /* Clear rest of the row */ + for (j =3D m; j < ARRAY_SIZE(sps->enc); j++) { + memset(&sps->enc[j], 0, sizeof(sps->enc[j])); + } + + if (m) { + n++; + } + } + + /* Clear the rest of the table */ + for (i =3D n; i < ARRAY_SIZE(opts->sps); i++) { + memset(&opts->sps[i], 0, sizeof(opts->sps[i])); + } + + if (!ci_largepage) { + opts->flags &=3D ~PPC_HASH64_CI_LARGEPAGE; + } +} diff --git a/target/ppc/common-misc.h b/target/ppc/common-misc.h new file mode 100644 index 0000000000..a12488476d --- /dev/null +++ b/target/ppc/common-misc.h @@ -0,0 +1,13 @@ +#ifndef COMMON_MISC_H +#define COMMON_MISC_H +#include "qemu/osdep.h" +#include "cpu.h" + +void ppc_store_vscr(CPUPPCState *env, uint64_t vscr); +uint32_t ppc_load_vscr(CPUPPCState *env); +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); +void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, + bool (*cb)(void *, uint32_t, uint32_t), + void *opaque); + +#endif diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 429de28494..892c7e2a63 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -27,6 +27,7 @@ #include "fpu/softfloat.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "common-misc.h" =20 #include "helper_regs.h" /*************************************************************************= ****/ @@ -461,17 +462,12 @@ SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX) =20 void helper_mtvscr(CPUPPCState *env, uint32_t vscr) { - env->vscr =3D vscr & ~(1u << VSCR_SAT); - /* Which bit we set is completely arbitrary, but clear the rest. */ - env->vscr_sat.u64[0] =3D vscr & (1u << VSCR_SAT); - env->vscr_sat.u64[1] =3D 0; - set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); + ppc_store_vscr(env, vscr); } =20 uint32_t helper_mfvscr(CPUPPCState *env) { - uint32_t sat =3D (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) !=3D 0; - return env->vscr | (sat << VSCR_SAT); + return ppc_load_vscr(env); } =20 static inline void set_vscr_sat(CPUPPCState *env) diff --git a/target/ppc/meson.build b/target/ppc/meson.build index b369a6bcd0..b5a89df296 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -3,6 +3,7 @@ ppc_ss.add(files( 'cpu-models.c', 'cpu.c', 'gdbstub.c', + 'common-misc.c', )) =20 ppc_ss.add(libdecnumber) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0fabc10302..22b9a99608 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "hw/hw.h" #include "mmu-book3s-v3.h" +#include "common-misc.h" =20 /* #define DEBUG_SLB */ =20 @@ -1119,14 +1120,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, targ= et_ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) -{ - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); - CPUPPCState *env =3D &cpu->env; - - env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; -} - void helper_store_lpcr(CPUPPCState *env, target_ulong val) { PowerPCCPU *cpu =3D env_archcpu(env); @@ -1197,61 +1190,3 @@ const PPCHash64Options ppc_hash64_opts_POWER7 =3D { } }; =20 -void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, - bool (*cb)(void *, uint32_t, uint32_t), - void *opaque) -{ - PPCHash64Options *opts =3D cpu->hash64_opts; - int i; - int n =3D 0; - bool ci_largepage =3D false; - - assert(opts); - - n =3D 0; - for (i =3D 0; i < ARRAY_SIZE(opts->sps); i++) { - PPCHash64SegmentPageSizes *sps =3D &opts->sps[i]; - int j; - int m =3D 0; - - assert(n <=3D i); - - if (!sps->page_shift) { - break; - } - - for (j =3D 0; j < ARRAY_SIZE(sps->enc); j++) { - PPCHash64PageSize *ps =3D &sps->enc[j]; - - assert(m <=3D j); - if (!ps->page_shift) { - break; - } - - if (cb(opaque, sps->page_shift, ps->page_shift)) { - if (ps->page_shift >=3D 16) { - ci_largepage =3D true; - } - sps->enc[m++] =3D *ps; - } - } - - /* Clear rest of the row */ - for (j =3D m; j < ARRAY_SIZE(sps->enc); j++) { - memset(&sps->enc[j], 0, sizeof(sps->enc[j])); - } - - if (m) { - n++; - } - } - - /* Clear the rest of the table */ - for (i =3D n; i < ARRAY_SIZE(opts->sps); i++) { - memset(&opts->sps[i], 0, sizeof(opts->sps[i])); - } - - if (!ci_largepage) { - opts->flags &=3D ~PPC_HASH64_CI_LARGEPAGE; - } -} diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 87729d48b3..4b8b8e7950 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -15,12 +15,8 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte0, target_ulong pte1); unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, uint64_t pte0, uint64_t pte1); -void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); void ppc_hash64_init(PowerPCCPU *cpu); void ppc_hash64_finalize(PowerPCCPU *cpu); -void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, - bool (*cb)(void *, uint32_t, uint32_t), - void *opaque); #endif =20 /* --=20 2.17.1