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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id c77sm2677248wme.37.2021.04.22.03.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cabhLB4yC3EX0HW1DUz6q6/H4n+t/Hox0M7vQX6zFMs=; b=sM9yfjzXHmaKdXQ32dW+cKif/mNfv1FC+kAz/OFjlULw6BkWml+a30iojZcqhqYrmC PDdv4bbEkMbnn4S/der7UPpngCfaZV91bZkOhO8iLDsCIJCR2eRGvRGCuy7OAfKNNDCA tXS6KnZLcClDkvbPlZclGl1EFRyJvCxkDTOpgbnd4vIO780+q93g5Ikv1gJr0NUvjWho Z5EjbzS0Q4DDK2WXA6bTUuqxgvDRY/f9iCgQfoPFIGGMng3GiEPDrRvWvEKsQRNkT1Kg S0DhUIfZhU5+iuMJjlm+iKTLwHEmhZqLcgJAuKeKSafgUa1B4fQA0w35afSpSenLD2HD mHYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cabhLB4yC3EX0HW1DUz6q6/H4n+t/Hox0M7vQX6zFMs=; b=HcBUZHxDC8IzTc5QG94X2ReEXouilLCdSBwUIIPhP6a9ZbX4J0Ngwljhr1Rjw2b07c zLGgee5whxmOOgqgL4829A/uvloFKphiaUIFzzvdfXBk7V5CLQKxQjLIHTHiMNfEJzIj 55v3M3BYCdsgC6uVKA9w3rEI/ckF6SJ7FUMwzjzH4zr9+4Zwp7VONPFXb6dZ2ARyvm9K qyhZDCXOHoSRxDibl8CiVhp/CJgkhlRwDF7SX0p7gKE3w4RXoZYKZs4wVw5M75ENiDuU RaBSieZ3EN3iXl0RDEsqWYrgT4fqKDAEYy6zC1WnCrSv8/8wiOAAcj2IMH59pcCc7z9v +Z0g== X-Gm-Message-State: AOAM530duzjGo4ZmJjsuLUQC0LCg7A5OQ5oFMkiGhB550ZMuHNk77Txc LiX72hkd2zHzAH8Zgaknvjs= X-Google-Smtp-Source: ABdhPJwazTsh46NNhk80r4RCU7P9fMNFfoekNBu0OVtSkKZmrhqdefqrTuZzF0RmGOphw7/R3jC12g== X-Received: by 2002:a5d:62cd:: with SMTP id o13mr3327678wrv.77.1619088467299; Thu, 22 Apr 2021 03:47:47 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Michael Rolnik , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , Cornelia Huck , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v5 07/15] cpu: Move CPUClass::vmsd to SysemuCPUOps Date: Thu, 22 Apr 2021 12:46:56 +0200 Message-Id: <20210422104705.2454166-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. - Move the CPUClass::vmsd field to SysemuCPUOps, - restrict VMSTATE_CPU() macro to sysemu, - vmstate_dummy is now unused, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Since v3: Merged in patch 1 (Eduardo) therefore removed Richard R-b. 'vmsd' is not a 'system operation' prototype but a const pointer field, so it belongs to a const structure, but maybe this structure could be better named than SysemuCPUOps? This field comes from: commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4 Author: Andreas F=C3=A4rber Date: Sun Jan 20 20:23:22 2013 +0100 cpu: Register VMStateDescription through CPUState In comparison to DeviceClass::vmsd, CPU VMState is split in two, "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1. Therefore add a CPU-specific CPUClass::vmsd field. Unlike the legacy CPUArchState registration, rather register CPUState. --- include/hw/core/cpu.h | 7 ++----- include/hw/core/sysemu-cpu-ops.h | 4 ++++ include/migration/vmstate.h | 2 -- cpu.c | 18 ++++++++---------- stubs/vmstate.c | 2 -- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 7 +++++++ target/openrisc/cpu.c | 3 ++- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 6 ++++++ target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 5 +++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 7 +++++++ target/unicore32/cpu.c | 3 ++- target/xtensa/cpu.c | 5 +++-- target/ppc/translate_init.c.inc | 2 +- 27 files changed, 65 insertions(+), 41 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 24cb05c5476..bdc702894bf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,7 +124,6 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -179,7 +178,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); @@ -1057,10 +1055,8 @@ bool target_words_bigendian(void); #ifdef NEED_CPU_H =20 #ifdef CONFIG_SOFTMMU + extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy -#endif =20 #define VMSTATE_CPU() { = \ .name =3D "parent_obj", = \ @@ -1069,6 +1065,7 @@ extern const VMStateDescription vmstate_cpu_common; .flags =3D VMS_STRUCT, = \ .offset =3D 0, = \ } +#endif /* CONFIG_SOFTMMU */ =20 #endif /* NEED_CPU_H */ =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e54a08ea25e..05f19b22070 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,10 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @vmsd: State description for migration. + */ + const VMStateDescription *vmsd; } SysemuCPUOps; =20 #endif /* SYSEMU_CPU_OPS_H */ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 075ee800960..8df7b69f389 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,8 +194,6 @@ struct VMStateDescription { const VMStateDescription **subsections; }; =20 -extern const VMStateDescription vmstate_dummy; - extern const VMStateInfo vmstate_info_bool; =20 extern const VMStateInfo vmstate_info_int8; diff --git a/cpu.c b/cpu.c index bfbe5a66f95..64e17537e21 100644 --- a/cpu.c +++ b/cpu.c @@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); +#endif =20 cpu_list_add(cpu); =20 @@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) } #endif /* CONFIG_TCG */ =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else +#ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } =20 void cpu_exec_unrealizefn(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/stubs/vmstate.c b/stubs/vmstate.c index cc4fe41dfc2..8513d9204e4 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,8 +1,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" =20 -const VMStateDescription vmstate_dummy =3D {}; - int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index cd01d34d92f..73d1945b136 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .vmsd =3D &vmstate_alpha_cpu, }; #endif =20 @@ -242,7 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_alpha_cpu; + cc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 73a236486df..6421877c978 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .vmsd =3D &vmstate_arm_cpu, }; #endif =20 @@ -1987,7 +1988,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 78ef4473c50..20a48bdfbab 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .vmsd =3D &vms_avr_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 394df655c9f..5fa2a3f20f1 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .vmsd =3D &vmstate_cris_cpu, }; #endif =20 @@ -298,7 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_cris_cpu; + cc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6605c42e509..16ba76cfafd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .vmsd =3D &vmstate_hppa_cpu, }; #endif =20 @@ -167,7 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_hppa_cpu; + cc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69858dcb243..a0cce7aafda 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .vmsd =3D &vmstate_x86_cpu, }; #endif =20 @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 15935ae7ceb..4ff54fd9204 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps lm32_sysemu_ops =3D { + .vmsd =3D &vmstate_lm32_cpu, }; #endif =20 @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_lm32_cpu; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 600812d682b..840196c93e4 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .vmsd =3D &vmstate_m68k_cpu, }; #endif =20 @@ -539,7 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_m68k_cpu; + cc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c6a10b1a52b..d8fc137b3e7 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .vmsd =3D &vmstate_mb_cpu, }; #endif =20 @@ -392,7 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - dc->vmsd =3D &vmstate_mb_cpu; + cc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 493331bf7bb..03fc4ef1962 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .vmsd =3D &vmstate_mips_cpu, }; #endif =20 @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 2cd631a7304..1e87f07ca73 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static const struct SysemuCPUOps moxie_sysemu_ops =3D { + .vmsd =3D &vmstate_moxie_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 296ccc0ed3c..a785f3ea7b6 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -25,6 +25,7 @@ #include "exec/log.h" #include "exec/gdbstub.h" #include "hw/qdev-properties.h" +#include "migration/vmstate.h" =20 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { @@ -208,7 +209,13 @@ static Property nios2_properties[] =3D { }; =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_nios2_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .vmsd =3D &vmstate_nios2_cpu, }; #endif =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cd8e3ae6754..b1f3f16820a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .vmsd =3D &vmstate_openrisc_cpu, }; #endif =20 @@ -209,7 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_openrisc_cpu; + cc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a6b909fa797..5d3a8dc2be4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + /* For now, mark unmigratable: */ + .vmsd =3D &vmstate_riscv_cpu, }; #endif =20 @@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->vmsd =3D &vmstate_riscv_cpu; cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index bbee1cb913f..f293f3630d0 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj) } =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_rx_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps rx_sysemu_ops =3D { + .vmsd =3D &vmstate_rx_cpu, }; #endif =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 36085035d1f..fe908d9bc40 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .vmsd =3D &vmstate_s390_cpu, }; #endif =20 @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 970d94a8a1a..a2dd8f93257 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail =3D &(env->movcal_backup); } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .vmsd =3D &vmstate_sh_cpu, }; #endif =20 @@ -268,7 +269,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - dc->vmsd =3D &vmstate_sh_cpu; + cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index a5dde9f7dd9..f5862e74baf 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .vmsd =3D &vmstate_sparc_cpu, }; #endif =20 @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8865fa18fce..9374f8440a0 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/error-report.h" +#include "migration/vmstate.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const VMStateDescription vmstate_tricore_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .vmsd =3D &vmstate_tricore_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index b67283ca592..ee5d2c5fd57 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static const struct SysemuCPUOps uc32_sysemu_ops =3D { + .vmsd =3D &vmstate_uc32_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -149,7 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_uc32_cpu; + cc->vmsd =3D &vmstate_uc32_cpu; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e93154de3e0..83dd8e4f6c9 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .vmsd =3D &vmstate_xtensa_cpu, }; #endif =20 @@ -224,7 +225,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; + cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 2a858cd0f2a..32fa62aded0 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .vmsd =3D &vmstate_ppc_cpu, }; #endif =20 @@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_ppc_cpu; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.3