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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id y8sm3398426wru.27.2021.04.22.03.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qHZkesTQ7iY0aT+GqCLFkQZuPGZupRkmvhvWLL3ejQQ=; b=fU/W7JOBizxBXgABfqaHuQ8B892lUWfRY5YOXDn71cd2A1wMrRhrZWFcBwqUve2ZZa jf1kKqs/duj7WWF4xB+L1bRxfloYnNS4HM20R2cN0n0ekoOyUNSoczrntuZ44VaRBCiy MIwKSeRXDnehpRZDsVSdmkc+3nl/Dc7j7v9/S36AykXm93GFrKUEXzhj92OLOQmfJs0N uAAyFbp53fPZ2wkaagB8EJ9NuMHeuuViF8Ocww5eJQIpVh1B4yVePefyYDsVbPejy25h VTlN+s98eMg9eIJFNYyx3fwELz83XuZGu4KVupa4Miw+kfwIBrr0FkiOUZoX550+2Khf dx+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qHZkesTQ7iY0aT+GqCLFkQZuPGZupRkmvhvWLL3ejQQ=; b=mMVcwVJNMKLrWvlCoRgTWmiWPd79tvxa753aYpFtciSgl+lfD0FZsEJBHBIILu2AT6 q3caFhugz29Oj42fbnZwaJ4cxOwf9W1NE5L7LPsE7bock5+B2dWlzovRPo096g9Yd7xI r0DQrWq/xFO/r4wCcnDBXKHth00pCvK6V1xeMFucUfeQPdFwCNQzbLxZ6Uet/A0PYQfy GIwKPb6iFHisHcnI62w0+7ag5YkBKFOT5HNSWGrncI6DmzMp9mWNrcbEf+T/Urq9v4yl RSX0Yuozq/EVHO7wYkkSYFpb2rKbfPnqLsnkVodQblt7EDkB+F2HDRT5e80hn7Va5D50 kp3g== X-Gm-Message-State: AOAM532IRkFDKRyF7nTHJhbPdYfVOzgdoz5CYdM3tCHZPDqh8lLzfhUM VHoQQuoj9VjQvPjcuUpI0ym/tCCIbSaPpQ== X-Google-Smtp-Source: ABdhPJzNC4BB9erAWVRLhhpwh1Zeqi5ghOGFzpiqQnj+JtfT+pJrHpsivyK3RstfYnX4BMN+3cJefg== X-Received: by 2002:a1c:6a06:: with SMTP id f6mr3077795wmc.179.1619088506542; Thu, 22 Apr 2021 03:48:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 14/15] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps Date: Thu, 22 Apr 2021 12:47:03 +0200 Message-Id: <20210422104705.2454166-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6dd60c3ada4..d0187798eea 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -93,7 +93,6 @@ struct AccelCPUClass; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -136,7 +135,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 460e7d63b0c..3f9a5199dd1 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 339bdfadd7a..7a8487d468f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->sysemu_ops->get_paging_enabled) { + return cc->sysemu_ops->get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b7317e43b4..feb71981efb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7162,12 +7162,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs) return cpu->apic_id; } =20 +#if !defined(CONFIG_USER_ONLY) static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 return cpu->env.cr[0] & CR0_PG_MASK; } +#endif /* !CONFIG_USER_ONLY */ =20 static void x86_cpu_set_pc(CPUState *cs, vaddr value) { @@ -7394,6 +7396,7 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_memory_mapping =3D x86_cpu_get_memory_mapping, + .get_paging_enabled =3D x86_cpu_get_paging_enabled, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7434,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3