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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id p18sm2821742wrs.68.2021.04.22.03.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kHEK4AhSZFQVUn4HZfyzLvc603glcsJJgxbrmPqHznQ=; b=Uc6wRXG14XGpPSQQcIVOJ3MJttZR2A1Z98NhO6Grx298pdcbUoze+NMMM3qcoQdzOb MIpCDwEka9ZHdatuEDQGeHGdutOboHpGVyioZ1juC8bk0h1uGnIK1c7LuYeix8FtTTDw THX8MeH6jwvDa08kAagjhL9KAznGs2aME4rqQxaZTS0v1T/JhUMSWUWhpjlsBqQgDL40 +k+X5SHbVCyenr4u5xTWmxXblwbaMo8QknAQZLkwlFkA9cK2HsFqac2AjwWIpNkgszC6 98mFk4kz0fpCzhwI0+M6h3dUb1vlgKSA1BoXQw2BrGKsjuIH9wLeKbj78O8jU+qifIRp mCSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kHEK4AhSZFQVUn4HZfyzLvc603glcsJJgxbrmPqHznQ=; b=ZAyPrzALbmu3dckECviMUVYbcF6l8T3zysIPAVFBvik3tp0tbocUrizmPNnwlZH2L0 xWCVoKI+GftWEH6aj8/n2t8ca49BPIsMYTACFF10khcGRWUI6FospjGeeBXdRyDPt/UJ TyxyVwZqGfz32K/GpUvdROTWU4Dds1ZgniWeF4RaqNBAVSXE6d9nhNP4kJAmCzyo6aBS uITvBc5jp89rdS5DD+/dfivIHVel3DkLkOMSxHMGMHo8uyyjPtbQ/qvLwmkeFApK3WqK dajpYXNpmoMlQ/fZ9Nh7mDUfAa1dalqfK8onSmcV3QtCSqkYg2j7UBDlbEF3XmWfU0Y3 s4DA== X-Gm-Message-State: AOAM532QrG35DE20wxiBQ6cFSm7dNI1HKp6YQ8zxOZKRXPW02oluGwMd gX04OFY20/ea+NJlz7E+EGU= X-Google-Smtp-Source: ABdhPJwJ7Lusw5e3bPm9iJOhRrfadTb9G3zuqtBL6T1Tm/9SAPsbc9Rn58zvn/RAPULUa9i/C8hQ7w== X-Received: by 2002:a5d:6d0a:: with SMTP id e10mr3414411wrq.161.1619088489529; Thu, 22 Apr 2021 03:48:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 11/15] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps Date: Thu, 22 Apr 2021 12:47:00 +0200 Message-Id: <20210422104705.2454166-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7095bc4192..28c4fc541a2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 60c667801ef..3c3f211136d 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c74390aafbf..c44229205ff 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 326ed9180cc..ff356094b13 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ee64461b43..5269fa484e1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -7434,7 +7435,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3