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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id u5sm5652369wmg.25.2021.04.22.03.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JQ0OTstwzXipk72lX8fvK3spe8ZEv2YAFM7sdltFU54=; b=aeWAH3G8EpW+AZHWNlu0nhIo7Ev+MF7JBLe5jkax6DTbA5/ZYpOOfY934gfXmDu5JC 6dszsbsd5Y3dkur/QuVT/iQgifazshNbCliHl6WlVx6sOYERCYw+7FoxnSO8CZ+Hyu6X nXPFPyrLULI5RQFyoE2QT2i0btOWhf0c9SuctODrXgwzHNYpEptoZOjpJY9PuVl5Bhz3 8JFD0Ycu9qGeOg8Wi3yjLBwkJT00waTp9SFo6hVYqXraLNhcMrQfLsl4Ukl1hPaotWP2 fXcBnlBaR5cYtCHZgLVaqa1NqLOJSyl8utbKSS2JpAGZxUqL1biLJN5r89Bwt05LWEfI q56Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JQ0OTstwzXipk72lX8fvK3spe8ZEv2YAFM7sdltFU54=; b=EviuZtlUThUV0wwItuePfhgeOEw3UwmdixaWMOKJ+bRtfcFIj+QsHPhOZMUlCe1/ce OiSxx/jz5R52h40M48FXfbtupYUGLt4kVPFdtO0lE3ivBbrN4KM7fZZSWnHJgHA/upgl 7G7F+2znVFgR7El6hLGHg2b8meXgAN8cVHd9r4anWdsf9cwxZt8DS3Mf1qgGS7OhuUCl FIo0WwxiTczD0Dk3X2ox3ymV9cYZBbai/3ZtBtCdAscTvGVZWxFLectRhjU5CNeTmN/G H/Q4yihLQxT4Q7H9j74VngO7ISTa0c3DWbA0lfR4chs5hdweZyrq+ZRwfASanJGSS7iB A60A== X-Gm-Message-State: AOAM5320TZRJSyK+1kCpGv5Ct8X2A6Xtb3/v8DCNJ16Jh8JRi3oZv/Lk DOGrhHzkKUhWg6GHo8RQ2Lw= X-Google-Smtp-Source: ABdhPJz/WC6deB0nmXvQB74PAxd0ybntnrTAgAB15yge+i6yIm8WEWU2aEpYitF/ViJxBdW48aq46A== X-Received: by 2002:adf:84e6:: with SMTP id 93mr3193295wrg.376.1619088432924; Thu, 22 Apr 2021 03:47:12 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 01/15] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Thu, 22 Apr 2021 12:46:50 +0200 Message-Id: <20210422104705.2454166-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c68bc3ba8af..9338e80aa4b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -580,18 +580,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -603,12 +593,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -617,17 +602,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..4dce35f832f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu, error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619088440; cv=none; d=zohomail.com; s=zohoarc; b=QWiSrodjJPtdBMxHs58TbdrU2zmUtVtzn9HwuTYbN31Lad69quExkOu1Wk3cENyOG/8CIcPMlY76OxMo+lOc7JUaQiecfy8N5laAshLTKLIzDFBHFuQ974z3kvvctIfyq8YI1WJwBcbLlrcLNkgUk2+M0W8w7lwYhDx5vqN2vbE= ARC-Message-Signature: i=1; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id a22sm2930800wrc.59.2021.04.22.03.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MQSyM2Tdm6K0DCg9lxDEVBIxpe6wKmVXubqRoSivHac=; b=glF10+sSKyBVREb+NIXktdrlLbdnKfTuEJkVMT+s0ZNmjemcMtVD2GKugI3/LYMpeS 7AjJ9V/kO7+oPrlpukyQIP5HpFb0+FboPQqr06hr968i8Hqbunh4sO9gHzZVJHwDq3IT OcS78It5Ht8LQ9TCYT1PDVKeDGzpYZNbswmpje0aUK/A2tok/GaQUue1CgHVgsVh0m0x dh4E6fBctFtGFRTBjeQ6zPLYgftqMFEin03ObP3W60CBak2hSrGh3BxEHHA44OjLh8LA Ketut1C9204hszCNwkHmXyTW7YrpGFTP6wBwhOeAO5xj+rstGtoMkCf6PjXUbrc+UsFo B/bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=MQSyM2Tdm6K0DCg9lxDEVBIxpe6wKmVXubqRoSivHac=; b=RqIJmBMQg7w+DfMO3YS2qC1FQ4YAlDmBmNrdJZj5W6P8Age7Gnd20abOicZJAEdbf/ qOM312PM3unm/QDkbBe3HZm3a/0i+w2fsr2lSbrktxEJ30NhHXyd7k8XVnteXKgwydxe EDo8BBx9ohLL0S7/bidOzP7cuGTC+POy5Jr+iAyxonigJIU8l1APIBTePSzrnc4DbIKl wAOGHACKUWoQj5mtMS8GqzorgXDv1DkHwdxHCvyZ08fEXCw8uwKwXiJ81neWSM+M/Ogm 0/upsK8exuoBEEU0cclTVNlKmF73BI1KyyMvfK0hBwKxAliHSfpum9wPum0QRU2WT3Vr ZwfQ== X-Gm-Message-State: AOAM530bmDuzjqwdQyekXP2ZI1TXpuuEvZmYs0issuTTU4tF4KeTRNt0 /QMiF/le6VqGed7JQ2P6HSA= X-Google-Smtp-Source: ABdhPJwO1Cwswco/l6ZWPs37RTpkRgvapQAPv53s1T2xV5cC9g/R4KLAivq/pSSMlH3AXR/U/vGVpg== X-Received: by 2002:adf:bc09:: with SMTP id s9mr3237820wrg.329.1619088438305; Thu, 22 Apr 2021 03:47:18 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 02/15] cpu: Introduce cpu_virtio_is_big_endian() Date: Thu, 22 Apr 2021 12:46:51 +0200 Message-Id: <20210422104705.2454166-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Similarly to commit bf7663c4bd8 ("cpu: introduce CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method name to hint this handler shouldn't be called anywhere but from the virtio code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v5: Reword description to justify 'virtio' in name --- include/hw/core/cpu.h | 9 +++++++++ hw/core/cpu.c | 8 ++++++-- hw/virtio/virtio.c | 4 +--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9338e80aa4b..08af2c383a5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -604,6 +604,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr ad= dr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ =20 /** diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 4dce35f832f..daaff56a79e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +bool cpu_virtio_is_big_endian(CPUState *cpu) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->virtio_is_big_endian) { + return cc->virtio_is_big_endian(cpu); + } return target_words_bigendian(); } =20 @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; - k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 07f4e60b309..8a364496fd5 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - CPUClass *cc =3D CPU_GET_CLASS(current_cpu); - - if (cc->virtio_is_big_endian(current_cpu)) { + if (cpu_virtio_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619088445; cv=none; d=zohomail.com; s=zohoarc; b=dXtLFCSaczZVKI5xXcuWH4mUyS44wA9Bp2BiaYwsCgafc4jy+io1XxfM08LjMhrwLjHv6YIlCQVW/qW6XnQKyiFhi8IYYv44rHyRHUbz/HJrGu7S28nbG9R7K9BZpQQ45OnrK5S5m/asRjQHFce6LH7Hb+w+v4qEgAANMTbQLao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088445; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J6YQeevinF+UxncXXirBs+TNeTtBEGxrSMPU7gVD3MU=; b=CdYSkRrV/5LJyjhUxRTsz4dQ3UfCPXLEtRYZHauRI5gIv9tgoha4G6gzD9wFpK7yFnBWHwYD5vIGwUxQG/SGsG3zXKNTsuWIpMGmvBoOLq+f+OtWtPjuMDJw7GIKDtqpNdmonKTSgZGYgWvBwpLPFVonG6vHXdwiYrmdBAtennQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 1619088445660178.24385085856102; Thu, 22 Apr 2021 03:47:25 -0700 (PDT) Received: by mail-wm1-f46.google.com with SMTP id y124-20020a1c32820000b029010c93864955so2968207wmy.5 for ; Thu, 22 Apr 2021 03:47:25 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id f6sm2768689wrt.19.2021.04.22.03.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J6YQeevinF+UxncXXirBs+TNeTtBEGxrSMPU7gVD3MU=; b=SPMN0H58jaHy0OX/UysQKeTE2Rhtc7A1t+nFo8oh3564mNJm90y1sv3Zk1eyrjRGm3 bpNNXVST+Zuo63EXV1xc/3+MTGD/FgL8u1tgDTpslvaLEDWyzirtOTkOOiOYSu1jvNkT 46xq6ELy/biINIn2FxOMWY33tJAO8rbvsb6jE/hqRZBLm3GwkgEQju5NDcCdfrdIy2Ip ZyChfiqZfUqwMwhRg6H4z/jpJYjis1ZnutC7dzzi/1/JHnTBwe2zHJIw9UaNaJEPOf/f z2Gj9E7UpVqMn13DgxSH8d8W8MsLm2lPfRZnmAeb/pka5MSjSV+4Cb7jWmoY5ODosZjI 06VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J6YQeevinF+UxncXXirBs+TNeTtBEGxrSMPU7gVD3MU=; b=dOGo/ZoUM3+AZUJNjWL+qDj5/pm3RkfntN2rgBzm7zcUdhNNl+6+lr7GsfUucUbh1R 4oGryfSfs11WPuqVbYc9vZz6h45Vv2uWo+rMfpzZKstwUAToW0ayI37EKpXj+1XAiYaS HuwruXHc+SnO9X9NJd62CH768FZSVyXrDqasdfPuotdJ5ayEd3LXH0v1vbvDJpSbxsMC PnMdSvQl0iPRjPlgvoSpl2KbDrhj7Qgy+Ui+8swFI3pIFwBjm7Tz5Lf1Cq+pAYvbI3MA K/4w/Z4dXZHyiEke4e0ioXILX5LXglmOKQk2Nqw3dC/jjVl4dw3P0lBEr5HUhYBNwrlQ +org== X-Gm-Message-State: AOAM533SrVZN+ThtAA5GFBKRgO/prwvCtYsueSYxUAYpcQnup9ssuu4C 9fMylBJfnoAGN8qpyLk/aoA= X-Google-Smtp-Source: ABdhPJwNE277zfbHJw8ofaurHJkJ3I0dHiDB5LhPo5J75HLMPOIjjUXuipWzaaONrEOcNlM6Q5iBVw== X-Received: by 2002:a1c:7fcd:: with SMTP id a196mr14897761wmd.180.1619088443920; Thu, 22 Apr 2021 03:47:23 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 03/15] cpu: Directly use cpu_write_elf*() fallback handlers in place Date: Thu, 22 Apr 2021 12:46:52 +0200 Message-Id: <20210422104705.2454166-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:440: k->write_elf32_qemunote =3D cpu_common_write_elf32_= qemunote; hw/core/cpu.c:441: k->write_elf32_note =3D cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote =3D cpu_common_write_elf64_= qemunote; hw/core/cpu.c:443: k->write_elf64_note =3D cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note =3D arm_cpu_write_elf64_no= te; target/arm/cpu.c:2305: cc->write_elf32_note =3D arm_cpu_write_elf32_no= te; target/i386/cpu.c:7425: cc->write_elf64_note =3D x86_cpu_write_elf64_n= ote; target/i386/cpu.c:7426: cc->write_elf64_qemunote =3D x86_cpu_write_elf= 64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note =3D x86_cpu_write_elf32_n= ote; target/i386/cpu.c:7428: cc->write_elf32_qemunote =3D x86_cpu_write_elf= 32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note =3D ppc64_= cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note =3D ppc32_= cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note =3D s390_cpu_write_elf64_= note; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 43 ++++++++++++------------------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index daaff56a79e..a9ee2c74ec5 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_qemunote) { + return 0; + } return (*cc->write_elf32_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_note) { + return -1; + } return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_qemunote) { + return 0; + } return (*cc->write_elf64_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_note) { + return -1; + } return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - - static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) { return 0; @@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; - k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; - k->write_elf32_note =3D cpu_common_write_elf32_note; - k->write_elf64_qemunote =3D cpu_common_write_elf64_qemunote; - k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619088451; cv=none; d=zohomail.com; s=zohoarc; b=MnpUeDV/3jgD+5muAHhNSqQNGQFbSsyUbvhvA4IGe26AGBk5i3ov5bi8lV04cGwHILdQk2p9dJpUoLVRv46rXyQrTOS1U13oaCtQody1SkR3Y95YRY8rnEWimZdbVMMYWBcJISDTS2zBYptghzpHLSZi0/0Vtmh0QFvbR5M+DGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088451; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y73DhisXrZCkQN7S3qTtV5uihkPH6tpgdxs7MXvhbiA=; b=LOWT94TRXTuoyHmDyxyskHlY90cYEzX4dOeSxywfuxCVhPyBZEXYkkbmMS9xgPZGeQKYCI66LnAlxnNi1SD0hqdK0+MbFgM2E8P1ifRFxdwjc26ogiY2vpTfQ7fs9EyfnREaMwcvIG8srlCl+VFgDD9hqz5fvqCrW5RFDytygWU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1619088451187237.13513345596334; Thu, 22 Apr 2021 03:47:31 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id s7so44220406wru.6 for ; Thu, 22 Apr 2021 03:47:30 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id l7sm3280863wrb.35.2021.04.22.03.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y73DhisXrZCkQN7S3qTtV5uihkPH6tpgdxs7MXvhbiA=; b=undSZNoGnciSySVrOpga/wm4OMA7T7l91EHCRUVeSb8dRpaKKZaLBSLlUb5ilRqF5/ X4h+62CD/GXfIg3IIIBk16+Um/9QVK0kEvSmV2YJYb9g1fJr9H+8qSaBxckOLhx0+OQe ZvltPLaewLuiI4FiCokosjwWArim01IEVrLaJrI68Yoi92nKq0fHcjecSb8lpSbOIBrn dR7xJgXRjd+ELG83Jxupjgv6t4YRwtwc3ua0CaKC8TV2eWP5WeDadqAhk6IxP3D/4JFc 0ZeOefZ+dt19jFYtrac1FtSN3mTyYlpy3uCrdGzKpd2gO1TE58cgLncDLxEY39zg00nb f+sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Y73DhisXrZCkQN7S3qTtV5uihkPH6tpgdxs7MXvhbiA=; b=KXqF9RLDegqBdDPq0YWrE+0NvsfwXO7NLcQU7HAmMc0qKHxb6ErZOTe0DeTOPe9/PT bFU18Ewgqwe7loU+yVkFrni+/mbIb70Zeejac5hH+zM7h48QoH3YfkUVU1mP3g0xfFHt H59K3k2SF5IBWqDNDOIKwNSGu0PXAo+H7UHk2TQ1WSRAsY9CXqSsUwBGQYFSXuRIOxdF ixL4oyCwYpxCNIMyhQPRQLoRaN/9WulmKK0y+A1ALHb2f3/l8bSNQaMx8wbuduKOy2Ej PNYtFjZuqraIeUqYCGV++6n82ZTBn0Kft+IjbvdOuXDieNBYKgIYVaXpDXpmnLHEHDST NEqQ== X-Gm-Message-State: AOAM531l3royoLfaknoyKmREtmfXns5zvDoX+u22AIr3RCEGBwDhaCoV Yukr4pI1NMHAzKzfdqawSxs= X-Google-Smtp-Source: ABdhPJx72+wi4LyhqOEl+CCrKDQyMmLDmXOtS+MIAtPg7mFF/nBWScy18VBztKeu1wFvLYW2S6kPyg== X-Received: by 2002:a5d:5146:: with SMTP id u6mr3309964wrt.408.1619088449329; Thu, 22 Apr 2021 03:47:29 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 04/15] cpu: Directly use get_paging_enabled() fallback handlers in place Date: Thu, 22 Apr 2021 12:46:53 +0200 Message-Id: <20210422104705.2454166-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled =3D cpu_common_get_paging_ena= bled; target/i386/cpu.c:7418: cc->get_paging_enabled =3D x86_cpu_get_paging_= enabled; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index a9ee2c74ec5..1de00bbb474 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->get_paging_enabled(cpu); -} + if (cc->get_paging_enabled) { + return cc->get_paging_enabled(cpu); + } =20 -static bool cpu_common_get_paging_enabled(const CPUState *cpu) -{ return false; } =20 @@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619088456; cv=none; d=zohomail.com; s=zohoarc; b=Es5TR3EIZo5RDkfnpp5k1XNiaSdGcj9Ps9ZTyKOKKrnHjPmFp43Yu0Cqq5sbhAbuQwEmJfmzKkyZC+JhN3bYIvCII2k1X/Kr63C/nJNHts8P2sWT1Rom6qdHgIo4P/dOEHhd0DQspNZJ+QNIxfuaYe7C9kRn3wHEbyoffKtD4oc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088456; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AsKH3RYUFA9evmZE7qWhREuizy9iouUOsbLguH/0Dwo=; b=b/zZS8P842TOW/fkFBF0d5Q5Y6R6EpKLoKloVyffgCLmHr5FNaqMgZIl67k8LowuEAK49ChuimcZWmB0ZEMlfwbDnJGgUdU2myybLAW8SrxE5SFwci9nkeJ8eRgjCZbUZ2DJ9A0fV2odw2Vi+jLc+iRI09tZU+tpjOGgABb+I/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1619088456418654.4691894111218; Thu, 22 Apr 2021 03:47:36 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id w4so40584279wrt.5 for ; Thu, 22 Apr 2021 03:47:35 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q17sm2931911wro.33.2021.04.22.03.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AsKH3RYUFA9evmZE7qWhREuizy9iouUOsbLguH/0Dwo=; b=PHby2C+q7Qpy2K19+TtUakRQosfU2qUjQbLwtOpzIxZHU117tOuDuV17z7raLMPzig zRO2bIt7NfEHnKEcYWJ/7/dT0g2fxBD8wWk2fBypMan9AhJgcNbme44OlnNSYXxyUeoO +rBTamBbsxhkPQpcqkPC9PjcjlAQguo47kNsHgYcRQx89sS5w9t049zBZHcoRR239Tiv oJAR6apMHrqEVsAcEJATYSTfxFlMcRen8vR9VSOqBAaUrtQzAEz1XcsvJSNc8xbPzCVW /XJDI2tuzJG8mRVIc6o5Pr1CnorZESQhvQGTdpk8eI97hRKsBb4RGHryEMG848IJA9Qx p9VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AsKH3RYUFA9evmZE7qWhREuizy9iouUOsbLguH/0Dwo=; b=ZK/q1uaeW6Ul2L4jdH1Z+ZE7JUQIumR6fN6O8th4iSAdOAYJiMTJ5NBnhZjXI0MWK1 JsA3Bu9K6qGTd7PmQQtcrC945vnod7XOwftP2faNBo0h85NBZKvWOMkBYwo7S7b0LYY1 r5lcZGqDqZgRxsfWW5S0QWljlgk6hdqmKv2M8P1LpYXTOJjzlFECHowoMgW/7l/0g9Lt BjjjZmznhjhr4eacdCyM2njtK6r6/YtByJO1AEUKC3+PsGwYooKAWuRatNGbDb4sI5Pc f7WM43wKGxfgLlOlksgku+Ipa5V4ABTqqdRimqOe52YFRf+u7DuhXf1+bF8TR68slQnD c61A== X-Gm-Message-State: AOAM530a/pmvKQGJ252/U6BVP7KGUtIXOplKuBOhAvBTp/0ik8earh+w +B2ULkKDlIfZpRp81g99cR0= X-Google-Smtp-Source: ABdhPJyt/JrPTuXIEEPy5JUAGWTeYdmJ248XgzKoq8icKnbgDAgzSYsIyTNT7vtqwh9cmD49TJzhUQ== X-Received: by 2002:adf:dd50:: with SMTP id u16mr3396495wrm.380.1619088454641; Thu, 22 Apr 2021 03:47:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 05/15] cpu: Directly use get_memory_mapping() fallback handlers in place Date: Thu, 22 Apr 2021 12:46:54 +0200 Message-Id: <20210422104705.2454166-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping =3D cpu_common_get_memory_map= ping; target/i386/cpu.c:7422: cc->get_memory_mapping =3D x86_cpu_get_memory_= mapping; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1de00bbb474..5abf8bed2e4 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappin= gList *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->get_memory_mapping(cpu, list, errp); -} + if (cc->get_memory_mapping) { + cc->get_memory_mapping(cpu, list, errp); + return; + } =20 -static void cpu_common_get_memory_mapping(CPUState *cpu, - MemoryMappingList *list, - Error **errp) -{ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 @@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619088462; cv=none; d=zohomail.com; s=zohoarc; b=gBf6c6iy1oBTxdisW2qY/oSMitsKgOQ2TtjkkfqME3Ip9r8YCPrmWkfT5XKDoFw82K5txYZciDcAUGN6Cj/rx3MredSneYlFrpdQ8gMw2DROZqNJo4agJ6jYf+MjWP+p8EGNhRr3dcTs3vuvB7EUmAulNNPvYI1W9XMkZ37MEVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088462; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5qsXp8OKDDW+PlplyGz+QwsT/qhDxPykmsnrnmWldzQ=; b=KGcZIC59fCzVN3qwqFa8rT7WW02Jm/S0///HFQ5f+UeexyGQGkai9PBKQILQGWz1V+9dlDgrxjUr7vUsYvqu7uZ6xqtK8ZpBnqyqTdoikGJa8tDpnV0P0HJXx29H/i5s3D9PL6qYHGhwEDgxUj0nWo9rTqNnNagYgr+6R27l+Bg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1619088462916892.2223736253459; Thu, 22 Apr 2021 03:47:42 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id n127so12042735wmb.5 for ; Thu, 22 Apr 2021 03:47:42 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id o18sm2514220wmp.26.2021.04.22.03.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5qsXp8OKDDW+PlplyGz+QwsT/qhDxPykmsnrnmWldzQ=; b=Ae+uN+lHmLTzIW1JkUZTYSeaXBZjcPZr04dWJKBQwtRWSevhNItsQBJSfiI3yqgh9E crDl9I9Dgzw2l6+HBMxlJUbw0Xf7OtPflk40lrZkzXEfFmJwECVSATVIb3uuxq3GrXbA LpRgUOEu4k8h2XVUFSY2amwtUTpdtJ9y/FWt/E7vfMM8WcVJCcVQ4c1jgRqMzjxVzCno 8vJ/UG+60J8sgZ6oEvn73sd7u8kuyISc301qiKZ9ze6txVwERhXykAHoGIxIzvgF5lJF rdjpHP0U4YFAgaQeiw6/DY4NsJ0yRfwuOpFP/thUVZQHLcj1q62EOQHMd0E5H6E8kQ7/ xJDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5qsXp8OKDDW+PlplyGz+QwsT/qhDxPykmsnrnmWldzQ=; b=j9kaLByWEOi10o503HYa1E3wwT2EwdMW+esDwMOi/jdwiAkCgJdYKR4e/eSXAPzRUa 5tWdCtYr08ewYa1ri3nvdsjEGhG/ZZrmvrBjmw9lzsOODko490UUnzE9I0cBlL9gKTox owhgpE5nbuyOBlaWGBI6Vn7VFcY5bfkZ+WZ4PelSzRKuoroxudGdXl8Soo7UgUvic3Cs 3qlcwzaJ1cPipif8Oy5STsQedHQ04za+bRVjlBYS58SGuntZwwAoEuB1GZKtmNqoH728 WWSKfAPKKXfWNDkLQmyaL/v7wsh5vFl6exzw/g1EPFlFG73qGUClXlH5HQS6A2NC5jb0 C2zw== X-Gm-Message-State: AOAM532+nRmZRlh/eDz+v5iuyIuNkboURKqCDHMxZ1VeNuP8AqAEOL+Y N68U+AkYPXWuwGHIz3VqUbo= X-Google-Smtp-Source: ABdhPJxqRkL2nhVgK+4xqQPerI6VCl5Zj27vBUIiNjMNMw1fWywtfPM3lkaZXVhiXwNHsTKpoIUznA== X-Received: by 2002:a1c:7ed3:: with SMTP id z202mr3113196wmc.136.1619088460857; Thu, 22 Apr 2021 03:47:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , Michael Rolnik , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Cornelia Huck , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v5 06/15] cpu: Introduce SysemuCPUOps structure Date: Thu, 22 Apr 2021 12:46:55 +0200 Message-Id: <20210422104705.2454166-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce a structure to hold handler specific to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +++++ include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++ target/alpha/cpu.c | 6 ++++++ target/arm/cpu.c | 6 ++++++ target/avr/cpu.c | 4 ++++ target/cris/cpu.c | 6 ++++++ target/hppa/cpu.c | 6 ++++++ target/i386/cpu.c | 6 ++++++ target/lm32/cpu.c | 6 ++++++ target/m68k/cpu.c | 6 ++++++ target/microblaze/cpu.c | 6 ++++++ target/mips/cpu.c | 6 ++++++ target/moxie/cpu.c | 4 ++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 6 ++++++ target/riscv/cpu.c | 6 ++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 6 ++++++ target/sh4/cpu.c | 6 ++++++ target/sparc/cpu.c | 6 ++++++ target/tricore/cpu.c | 4 ++++ target/unicore32/cpu.c | 4 ++++ target/xtensa/cpu.c | 6 ++++++ target/ppc/translate_init.c.inc | 6 ++++++ 24 files changed, 152 insertions(+) create mode 100644 include/hw/core/sysemu-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 08af2c383a5..24cb05c5476 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 +#include "hw/core/sysemu-cpu-ops.h" + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -190,6 +192,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; }; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h new file mode 100644 index 00000000000..e54a08ea25e --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..cd01d34d92f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps alpha_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps alpha_tcg_ops =3D { @@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; + cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0dd623e5909..73a236486df 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1943,6 +1943,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps arm_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, @@ -1986,6 +1991,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; + cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..78ef4473c50 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) qemu_fprintf(f, "\n"); } =20 +static const struct SysemuCPUOps avr_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps avr_tcg_ops =3D { @@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->vmsd =3D &vms_avr_cpu; + cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..394df655c9f 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps cris_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps crisv10_tcg_ops =3D { @@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; + cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..6605c42e509 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps hppa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps hppa_tcg_ops =3D { @@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; + cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ad99cad0e7c..69858dcb243 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7391,6 +7391,11 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps i386_sysemu_ops =3D { +}; +#endif + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -7432,6 +7437,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; + cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..15935ae7ceb 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps lm32_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps lm32_tcg_ops =3D { @@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; + cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index a14874b4da2..600812d682b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -503,6 +503,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }; #endif =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps m68k_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps m68k_tcg_ops =3D { @@ -535,6 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; + cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..c6a10b1a52b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *c= pu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mb_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps mb_tcg_ops =3D { @@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; + cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bde..493331bf7bb 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -680,6 +680,11 @@ static Property mips_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mips_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; + cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..2cd631a7304 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) return oc; } =20 +static const struct SysemuCPUOps moxie_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps moxie_tcg_ops =3D { @@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; + cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; } =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..296ccc0ed3c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,11 @@ static Property nios2_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps nios2_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps nios2_tcg_ops =3D { @@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..cd8e3ae6754 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps openrisc_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps openrisc_tcg_ops =3D { @@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; + cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b6..a6b909fa797 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -581,6 +581,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState = *cs, const char *xmlname) return NULL; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps riscv_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps riscv_tcg_ops =3D { @@ -625,6 +630,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; + cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..bbee1cb913f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps rx_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps rx_tcg_ops =3D { @@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 +#ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &rx_sysemu_ops; +#endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..36085035d1f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps s390_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; + cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..970d94a8a1a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu =3D { .unmigratable =3D 1, }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sh4_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps superh_tcg_ops =3D { @@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..a5dde9f7dd9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sparc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; + cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..8865fa18fce 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const struct SysemuCPUOps tricore_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps tricore_tcg_ops =3D { @@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..b67283ca592 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu =3D { .unmigratable =3D 1, }; =20 +static const struct SysemuCPUOps uc32_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps uc32_tcg_ops =3D { @@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_uc32_cpu; + cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..e93154de3e0 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu =3D= { .unmigratable =3D 1, }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps xtensa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps xtensa_tcg_ops =3D { @@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &xtensa_sysemu_ops; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index c03a7c4f526..2a858cd0f2a 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10878,6 +10878,11 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps ppc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -10921,6 +10926,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; + cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619088469; cv=none; d=zohomail.com; s=zohoarc; b=bA5ZMEtybqSqehkrNPauZZdxHMnz/EoiOdnExdodR7eHVwryMphkcaL+y8Nc7Ofvr4IL5fq/cJAzj6Gd1V+mef+gmh2J8OkYtgH9fQtaiY/2YGeU0CN7Z2N4D720vcJeS7SGeQE8Csj4vXa/ocH3Rd/72/9/gYrgB34daTwfuSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id c77sm2677248wme.37.2021.04.22.03.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cabhLB4yC3EX0HW1DUz6q6/H4n+t/Hox0M7vQX6zFMs=; b=sM9yfjzXHmaKdXQ32dW+cKif/mNfv1FC+kAz/OFjlULw6BkWml+a30iojZcqhqYrmC PDdv4bbEkMbnn4S/der7UPpngCfaZV91bZkOhO8iLDsCIJCR2eRGvRGCuy7OAfKNNDCA tXS6KnZLcClDkvbPlZclGl1EFRyJvCxkDTOpgbnd4vIO780+q93g5Ikv1gJr0NUvjWho Z5EjbzS0Q4DDK2WXA6bTUuqxgvDRY/f9iCgQfoPFIGGMng3GiEPDrRvWvEKsQRNkT1Kg S0DhUIfZhU5+iuMJjlm+iKTLwHEmhZqLcgJAuKeKSafgUa1B4fQA0w35afSpSenLD2HD mHYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cabhLB4yC3EX0HW1DUz6q6/H4n+t/Hox0M7vQX6zFMs=; b=HcBUZHxDC8IzTc5QG94X2ReEXouilLCdSBwUIIPhP6a9ZbX4J0Ngwljhr1Rjw2b07c zLGgee5whxmOOgqgL4829A/uvloFKphiaUIFzzvdfXBk7V5CLQKxQjLIHTHiMNfEJzIj 55v3M3BYCdsgC6uVKA9w3rEI/ckF6SJ7FUMwzjzH4zr9+4Zwp7VONPFXb6dZ2ARyvm9K qyhZDCXOHoSRxDibl8CiVhp/CJgkhlRwDF7SX0p7gKE3w4RXoZYKZs4wVw5M75ENiDuU RaBSieZ3EN3iXl0RDEsqWYrgT4fqKDAEYy6zC1WnCrSv8/8wiOAAcj2IMH59pcCc7z9v +Z0g== X-Gm-Message-State: AOAM530duzjGo4ZmJjsuLUQC0LCg7A5OQ5oFMkiGhB550ZMuHNk77Txc LiX72hkd2zHzAH8Zgaknvjs= X-Google-Smtp-Source: ABdhPJwazTsh46NNhk80r4RCU7P9fMNFfoekNBu0OVtSkKZmrhqdefqrTuZzF0RmGOphw7/R3jC12g== X-Received: by 2002:a5d:62cd:: with SMTP id o13mr3327678wrv.77.1619088467299; Thu, 22 Apr 2021 03:47:47 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Michael Rolnik , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , Cornelia Huck , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v5 07/15] cpu: Move CPUClass::vmsd to SysemuCPUOps Date: Thu, 22 Apr 2021 12:46:56 +0200 Message-Id: <20210422104705.2454166-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. - Move the CPUClass::vmsd field to SysemuCPUOps, - restrict VMSTATE_CPU() macro to sysemu, - vmstate_dummy is now unused, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Since v3: Merged in patch 1 (Eduardo) therefore removed Richard R-b. 'vmsd' is not a 'system operation' prototype but a const pointer field, so it belongs to a const structure, but maybe this structure could be better named than SysemuCPUOps? This field comes from: commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4 Author: Andreas F=C3=A4rber Date: Sun Jan 20 20:23:22 2013 +0100 cpu: Register VMStateDescription through CPUState In comparison to DeviceClass::vmsd, CPU VMState is split in two, "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1. Therefore add a CPU-specific CPUClass::vmsd field. Unlike the legacy CPUArchState registration, rather register CPUState. --- include/hw/core/cpu.h | 7 ++----- include/hw/core/sysemu-cpu-ops.h | 4 ++++ include/migration/vmstate.h | 2 -- cpu.c | 18 ++++++++---------- stubs/vmstate.c | 2 -- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 7 +++++++ target/openrisc/cpu.c | 3 ++- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 6 ++++++ target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 5 +++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 7 +++++++ target/unicore32/cpu.c | 3 ++- target/xtensa/cpu.c | 5 +++-- target/ppc/translate_init.c.inc | 2 +- 27 files changed, 65 insertions(+), 41 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 24cb05c5476..bdc702894bf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,7 +124,6 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -179,7 +178,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); @@ -1057,10 +1055,8 @@ bool target_words_bigendian(void); #ifdef NEED_CPU_H =20 #ifdef CONFIG_SOFTMMU + extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy -#endif =20 #define VMSTATE_CPU() { = \ .name =3D "parent_obj", = \ @@ -1069,6 +1065,7 @@ extern const VMStateDescription vmstate_cpu_common; .flags =3D VMS_STRUCT, = \ .offset =3D 0, = \ } +#endif /* CONFIG_SOFTMMU */ =20 #endif /* NEED_CPU_H */ =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e54a08ea25e..05f19b22070 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,10 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @vmsd: State description for migration. + */ + const VMStateDescription *vmsd; } SysemuCPUOps; =20 #endif /* SYSEMU_CPU_OPS_H */ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 075ee800960..8df7b69f389 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,8 +194,6 @@ struct VMStateDescription { const VMStateDescription **subsections; }; =20 -extern const VMStateDescription vmstate_dummy; - extern const VMStateInfo vmstate_info_bool; =20 extern const VMStateInfo vmstate_info_int8; diff --git a/cpu.c b/cpu.c index bfbe5a66f95..64e17537e21 100644 --- a/cpu.c +++ b/cpu.c @@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); +#endif =20 cpu_list_add(cpu); =20 @@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) } #endif /* CONFIG_TCG */ =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else +#ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } =20 void cpu_exec_unrealizefn(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/stubs/vmstate.c b/stubs/vmstate.c index cc4fe41dfc2..8513d9204e4 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,8 +1,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" =20 -const VMStateDescription vmstate_dummy =3D {}; - int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index cd01d34d92f..73d1945b136 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .vmsd =3D &vmstate_alpha_cpu, }; #endif =20 @@ -242,7 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_alpha_cpu; + cc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 73a236486df..6421877c978 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .vmsd =3D &vmstate_arm_cpu, }; #endif =20 @@ -1987,7 +1988,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 78ef4473c50..20a48bdfbab 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .vmsd =3D &vms_avr_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 394df655c9f..5fa2a3f20f1 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .vmsd =3D &vmstate_cris_cpu, }; #endif =20 @@ -298,7 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_cris_cpu; + cc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6605c42e509..16ba76cfafd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .vmsd =3D &vmstate_hppa_cpu, }; #endif =20 @@ -167,7 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_hppa_cpu; + cc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69858dcb243..a0cce7aafda 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .vmsd =3D &vmstate_x86_cpu, }; #endif =20 @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 15935ae7ceb..4ff54fd9204 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps lm32_sysemu_ops =3D { + .vmsd =3D &vmstate_lm32_cpu, }; #endif =20 @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_lm32_cpu; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 600812d682b..840196c93e4 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .vmsd =3D &vmstate_m68k_cpu, }; #endif =20 @@ -539,7 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_m68k_cpu; + cc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c6a10b1a52b..d8fc137b3e7 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .vmsd =3D &vmstate_mb_cpu, }; #endif =20 @@ -392,7 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - dc->vmsd =3D &vmstate_mb_cpu; + cc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 493331bf7bb..03fc4ef1962 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .vmsd =3D &vmstate_mips_cpu, }; #endif =20 @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 2cd631a7304..1e87f07ca73 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static const struct SysemuCPUOps moxie_sysemu_ops =3D { + .vmsd =3D &vmstate_moxie_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 296ccc0ed3c..a785f3ea7b6 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -25,6 +25,7 @@ #include "exec/log.h" #include "exec/gdbstub.h" #include "hw/qdev-properties.h" +#include "migration/vmstate.h" =20 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { @@ -208,7 +209,13 @@ static Property nios2_properties[] =3D { }; =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_nios2_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .vmsd =3D &vmstate_nios2_cpu, }; #endif =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cd8e3ae6754..b1f3f16820a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .vmsd =3D &vmstate_openrisc_cpu, }; #endif =20 @@ -209,7 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_openrisc_cpu; + cc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a6b909fa797..5d3a8dc2be4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + /* For now, mark unmigratable: */ + .vmsd =3D &vmstate_riscv_cpu, }; #endif =20 @@ -628,8 +630,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->vmsd =3D &vmstate_riscv_cpu; cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index bbee1cb913f..f293f3630d0 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj) } =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_rx_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps rx_sysemu_ops =3D { + .vmsd =3D &vmstate_rx_cpu, }; #endif =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 36085035d1f..fe908d9bc40 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .vmsd =3D &vmstate_s390_cpu, }; #endif =20 @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 970d94a8a1a..a2dd8f93257 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail =3D &(env->movcal_backup); } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .vmsd =3D &vmstate_sh_cpu, }; #endif =20 @@ -268,7 +269,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - dc->vmsd =3D &vmstate_sh_cpu; + cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index a5dde9f7dd9..f5862e74baf 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .vmsd =3D &vmstate_sparc_cpu, }; #endif =20 @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8865fa18fce..9374f8440a0 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/error-report.h" +#include "migration/vmstate.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const VMStateDescription vmstate_tricore_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .vmsd =3D &vmstate_tricore_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index b67283ca592..ee5d2c5fd57 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static const struct SysemuCPUOps uc32_sysemu_ops =3D { + .vmsd =3D &vmstate_uc32_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -149,7 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_uc32_cpu; + cc->vmsd =3D &vmstate_uc32_cpu; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e93154de3e0..83dd8e4f6c9 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .vmsd =3D &vmstate_xtensa_cpu, }; #endif =20 @@ -224,7 +225,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; + cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 2a858cd0f2a..32fa62aded0 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .vmsd =3D &vmstate_ppc_cpu, }; #endif =20 @@ -10925,7 +10926,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_ppc_cpu; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619088474; cv=none; d=zohomail.com; s=zohoarc; b=JEvacP77+jTtFqMvoCUzBA434myEQGVMJHA1Kdvtmx9+GKojx4Kor6huLBO1FJp1u5R4leWLizVmilFDrvWqdQ1nk5DISSXYF0/khMdGC/wK2SXmAfUQ8vVxCTfKgbn59ca/qZBm1rH0dLax1ePc/yGsOS+kysHU6blFr5SH7Fg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088474; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id i4sm3002746wrx.56.2021.04.22.03.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tP2J+wCmSfixgkbUO0OS9j1xOz4RXS1xTWip+OxPRIE=; b=nqlgUw5wBnL4GCJe/3bzAWYmKr20OCo60bg7OuF4yKfsI14YIYr4fE07FCb8ZiHPgK v+Yi+jD9MCFIo0Z1XABbiSVix/GD3S9isn8LVLDipUBDYDA36SiAuRSbmOJoHENx0sNa DifpMGHR+5E53ANUHJNgOHCyQKr7hUdwrqPkntg08upCxGTwAOEULJc7ZLHlEy5VtJS8 bDsq6ejLYbgCTqpZ8J/wcjqTz1QGBmPYEV/WWisrbW3laraIZ2WMqbYEDw46s+HqTFRU JS0wJbVIR/6ubWcf4Id19IbyPZdmNva81cYQ1/D+qHuTF83MM2HjN+Ph/xxlspjpRMSp CLPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tP2J+wCmSfixgkbUO0OS9j1xOz4RXS1xTWip+OxPRIE=; b=TaBai114IVcSs5dfhmf2wq229WLDCbhmva3SXrBwaOpmZGL9ncQjKhHH5hMMVEUaLq xaUp3lBBb44Pc1LvaljRatyHUnjp6sW1tcBaxZHKHqV91vp2DxySUrk6qdPvVX1Cl87P Lp9N1o/a4W+NkPM5S3ZE4MqVgEICBkdMrI0adpM9KXibYZ1NpvgGnuhBW8iSp+WlDqQv T96IzjtG8/VDxRejdrICTiq1r6Ul/TvinfhuutTbqJETWqfHQG/DjKQzr4kyTGTtz1SV VlwS3Kac4OLqgFPY3Isyx5gAosUVNyH7mh6ZiOEGHCEugDnWRF5/Mv/fdQZgo/t/NjBp IXHQ== X-Gm-Message-State: AOAM530Nw3mNTHPhfez7jqyZIP6zQchXnlqvPrXOB856Wt/wLvwXKUbO NBseP/7VYAV+gHtb54fSa5s= X-Google-Smtp-Source: ABdhPJwf2KUOcN4rfcqd4xZAzNqlCGTmwdOudbp+f2BJG/rbHG9p2bX+R//Y/C+ck98SpAqhB/3qGA== X-Received: by 2002:a7b:cd85:: with SMTP id y5mr14783816wmj.93.1619088472900; Thu, 22 Apr 2021 03:47:52 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , David Gibson Subject: [PATCH v5 08/15] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps Date: Thu, 22 Apr 2021 12:46:57 +0200 Message-Id: <20210422104705.2454166-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) VirtIO devices are only meaningful with system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 ----- include/hw/core/sysemu-cpu-ops.h | 8 ++++++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/ppc/translate_init.c.inc | 4 +--- 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bdc702894bf..e3c702b8b74 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,10 +89,6 @@ struct AccelCPUClass; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurab= le - * CPUs can use the default implementation of this method. This method sho= uld - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -151,7 +147,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 05f19b22070..9c3ac4f2280 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,14 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this me= thod. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); /** * @vmsd: State description for migration. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 5abf8bed2e4..09eaa3fa49f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->virtio_is_big_endian) { - return cc->virtio_is_big_endian(cpu); + if (cc->sysemu_ops->virtio_is_big_endian) { + return cc->sysemu_ops->virtio_is_big_endian(cpu); } return target_words_bigendian(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6421877c978..edefcc340af 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .vmsd =3D &vmstate_arm_cpu, }; #endif @@ -1988,7 +1989,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 32fa62aded0..b8a095d3f3a 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .vmsd =3D &vmstate_ppc_cpu, }; #endif @@ -10948,9 +10949,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_core_xml_file =3D "power64-core.xml"; #else cc->gdb_core_xml_file =3D "power-core.xml"; -#endif -#ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif cc->disas_set_info =3D ppc_disas_set_info; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id b206sm2654028wmc.15.2021.04.22.03.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yUcZBsD9xDOXEB+nTKfFfC4Vo6h4KKYKLXyLvxGRN4A=; b=oZ1T7SAcX+5QgMEagUvuk7YpAxq0PVXkRcqrgDLTa3apcE4X/dHyGvdMAc8NBb6Ieg bVWU/KJQu0N1fx/Era151PDglMYqzVuM0BFUnisZb98NZ00eTlJoz1/OU7owPR1b8Nlu aV2cZnXLDDS2aJR1UsMmxOXdtwtKMnAzwC18lOTxECNJM5sB/4c/bq/mIe1hZywgSpKA VYvx6rC3lBn6+b9ZhtTdSviWK1w8bJztou6OLM9TRPLEd+BFlWJgWg2Fs8L7g9GpVx8n uV7WOdsr1DzYgf7UFiyy4hQaP4az9rSWO+1IoHPBJnmc+11+fvmYgNiXbI78JUW46g1F PazA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yUcZBsD9xDOXEB+nTKfFfC4Vo6h4KKYKLXyLvxGRN4A=; b=WP0CaoyqLsYH5A2AoZlkcv4p0VxQfCUtzBtRMgltQJ7qA04gK2FGTZphMzHr/yr1UL x3GyhdRlpF98EcNOYTyXMj7nfw2+eOiKAcKDonCbbJkaFl5cHgpNbGWrb04POzzid3vj yGEt5gGWgwt1GqM9u2fj12oniIAqqKaK+XCQ0F55KCIL5dAv36jgyuVnrXKVR66cma1t ZwvUhvfhFDmhnbkLS82Enwm/Jz5VAq5FCyAjy6102Tgmcgn22iC4nt31C+uqBd8f7fZZ ld2d7RAf92UoHx9zbfjzpyBqgNIgDo/grEUdPKUG3D0BcwqPEv6F9496GonouWEEgsiL 0kcg== X-Gm-Message-State: AOAM530CZPkRHBPPAT13XGVRGETbWnSUxfTGFYytydeBAfNGsz0ibOdJ HpOstQ6YSax4PN7nYczCAkM= X-Google-Smtp-Source: ABdhPJwJv4PFPjnIresrNNHLhqLInDgitpN/6v/srbaV75nNYDLTqBEDVOpHAuyQ9pVr0CLAqleTKA== X-Received: by 2002:a5d:4584:: with SMTP id p4mr3221188wrq.383.1619088478322; Thu, 22 Apr 2021 03:47:58 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , David Hildenbrand , Cornelia Huck , Thomas Huth Subject: [PATCH v5 09/15] cpu: Move CPUClass::get_crash_info to SysemuCPUOps Date: Thu, 22 Apr 2021 12:46:58 +0200 Message-Id: <20210422104705.2454166-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 1 - include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- target/s390x/cpu.c | 2 +- 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e3c702b8b74..4289cd0d78a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -150,7 +150,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9c3ac4f2280..b9ffca07665 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 09eaa3fa49f..0aebc18c41f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); GuestPanicInformation *res =3D NULL; =20 - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); + if (cc->sysemu_ops->get_crash_info) { + res =3D cc->sysemu_ops->get_crash_info(cpu); } return res; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a0cce7aafda..538104d4557 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_crash_info =3D x86_cpu_get_crash_info, .vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7432,7 +7433,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->get_crash_info =3D x86_cpu_get_crash_info; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index fe908d9bc40..fdc169bb0ac 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_crash_info =3D s390_cpu_get_crash_info, .vmsd =3D &vmstate_s390_cpu, }; #endif @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id 186sm5695110wme.10.2021.04.22.03.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UY9CLuzbrcKvJSjz7SjoqOSgCuukkepxY/XOW5jkuVw=; b=BqbvtmxSpqPlZL3VulUk4mOfycS1NHMfcjiNUTOrIyUe0nBP9/TpwLjI2n5RgYwgEq Ft+/CsHA0SllbCX+atHgGgYDIddgI7/sMrHjYa40NOkdv5R8SsLIohbK+pTTNsdZjvt8 mFj3y3kri/Gfa4RdNb2or3/juL1WxAVErhs/qS6cxJsJWrOWKPNkOTf+9gTfTNffxWYq EPWBn/77K7qSGPFm5d1J61vgrWylDUtw5GKRlUEkMg/PwLW+p7BzsO5s3VJrjF+9gSnT ZO0eaeny2G4JMDNzjQLHhRQnpn5pDX5G8dTglDlKJXn5VNMEw/gb604KhY6WNsPcnWgb WYRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UY9CLuzbrcKvJSjz7SjoqOSgCuukkepxY/XOW5jkuVw=; b=sdb3IcTBCS2lg6yXQJmlwnJ+VyVHx11L/A+OC6M/RcWpe9uIgM1o+jLB3hwm7m6y8w hLOLSMOwEuUlVJmUpS34TX6kqAclEOSF498ZivR0heKZeyLib2NB3F1bypIdQ2mOJwbX xzzFcPR3PvtGygv0BvrN9Nqj/fLvngswTig5eJtRHSGQRCu6a/eVqAl0rIRYxJFWVO0Y /YKaCViFK60agIdAp3TfVbDqtN1dJuxTicM5jvlKgSMzXONLchJPfqNuHfnV98tY2ok3 PJi3Xpg3igvYcbUtlAl8q0LyWDzxSoFuI7b7DlFZt05LBAXj/oSa5imvbPI6+K1H1cz5 Splg== X-Gm-Message-State: AOAM530u/0Yis41GG3ElNGJy5XZF5sZDdTMagSDNhQ0sQVA3SkCcqcFl MslFVHo0iGljoUIG30U5EgY= X-Google-Smtp-Source: ABdhPJzDNViwczZZcruavRsYuEP7wPRwHst/H/cWicE5gmDuRUPvu5ORu+VL3IjVU8mJLLREci5whQ== X-Received: by 2002:a7b:cd91:: with SMTP id y17mr3126793wmj.27.1619088484125; Thu, 22 Apr 2021 03:48:04 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Cornelia Huck , Thomas Huth , David Hildenbrand Subject: [PATCH v5 10/15] cpu: Move CPUClass::write_elf* to SysemuCPUOps Date: Thu, 22 Apr 2021 12:46:59 +0200 Message-Id: <20210422104705.2454166-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v4: Added target/riscv/cpu.c after rebasing --- include/hw/core/cpu.h | 17 ----------------- include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++ hw/core/cpu.c | 16 ++++++++-------- target/arm/cpu.c | 4 ++-- target/i386/cpu.c | 8 ++++---- target/riscv/cpu.c | 4 ++-- target/s390x/cpu.c | 2 +- target/ppc/translate_init.c.inc | 6 ++---- 8 files changed, 43 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4289cd0d78a..b7095bc4192 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -112,14 +112,6 @@ struct AccelCPUClass; * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -163,15 +155,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index b9ffca07665..60c667801ef 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,30 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 0aebc18c41f..c74390aafbf 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_qemunote) { + if (!cc->sysemu_ops->write_elf32_qemunote) { return 0; } - return (*cc->write_elf32_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_note) { + if (!cc->sysemu_ops->write_elf32_note) { return -1; } - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); } =20 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_qemunote) { + if (!cc->sysemu_ops->write_elf64_qemunote) { return 0; } - return (*cc->write_elf64_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_note) { + if (!cc->sysemu_ops->write_elf64_note) { return -1; } - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edefcc340af..326ed9180cc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .write_elf32_note =3D arm_cpu_write_elf32_note, + .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .vmsd =3D &vmstate_arm_cpu, }; @@ -1989,8 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->write_elf64_note =3D arm_cpu_write_elf64_note; - cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 538104d4557..4ee64461b43 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7394,6 +7394,10 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_crash_info =3D x86_cpu_get_crash_info, + .write_elf32_note =3D x86_cpu_write_elf32_note, + .write_elf64_note =3D x86_cpu_write_elf64_note, + .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, + .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, .vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7433,10 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->write_elf64_note =3D x86_cpu_write_elf64_note; - cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; - cc->write_elf32_note =3D x86_cpu_write_elf32_note; - cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5d3a8dc2be4..8734e530cc5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .write_elf64_note =3D riscv_cpu_write_elf64_note, + .write_elf32_note =3D riscv_cpu_write_elf32_note, /* For now, mark unmigratable: */ .vmsd =3D &vmstate_riscv_cpu, }; @@ -631,8 +633,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; - cc->write_elf64_note =3D riscv_cpu_write_elf64_note; - cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index fdc169bb0ac..2b249f47eb9 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { .get_crash_info =3D s390_cpu_get_crash_info, + .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, }; #endif @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index b8a095d3f3a..a55d1c54fcf 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,8 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .write_elf32_note =3D ppc32_cpu_write_elf32_note, + .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .vmsd =3D &vmstate_ppc_cpu, }; @@ -10929,10 +10931,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif -#if defined(CONFIG_SOFTMMU) - cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; - cc->write_elf32_note =3D ppc32_cpu_write_elf32_note; -#endif =20 cc->gdb_num_core_regs =3D 71; #ifndef CONFIG_USER_ONLY --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id p18sm2821742wrs.68.2021.04.22.03.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kHEK4AhSZFQVUn4HZfyzLvc603glcsJJgxbrmPqHznQ=; b=Uc6wRXG14XGpPSQQcIVOJ3MJttZR2A1Z98NhO6Grx298pdcbUoze+NMMM3qcoQdzOb MIpCDwEka9ZHdatuEDQGeHGdutOboHpGVyioZ1juC8bk0h1uGnIK1c7LuYeix8FtTTDw THX8MeH6jwvDa08kAagjhL9KAznGs2aME4rqQxaZTS0v1T/JhUMSWUWhpjlsBqQgDL40 +k+X5SHbVCyenr4u5xTWmxXblwbaMo8QknAQZLkwlFkA9cK2HsFqac2AjwWIpNkgszC6 98mFk4kz0fpCzhwI0+M6h3dUb1vlgKSA1BoXQw2BrGKsjuIH9wLeKbj78O8jU+qifIRp mCSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kHEK4AhSZFQVUn4HZfyzLvc603glcsJJgxbrmPqHznQ=; b=ZAyPrzALbmu3dckECviMUVYbcF6l8T3zysIPAVFBvik3tp0tbocUrizmPNnwlZH2L0 xWCVoKI+GftWEH6aj8/n2t8ca49BPIsMYTACFF10khcGRWUI6FospjGeeBXdRyDPt/UJ TyxyVwZqGfz32K/GpUvdROTWU4Dds1ZgniWeF4RaqNBAVSXE6d9nhNP4kJAmCzyo6aBS uITvBc5jp89rdS5DD+/dfivIHVel3DkLkOMSxHMGMHo8uyyjPtbQ/qvLwmkeFApK3WqK dajpYXNpmoMlQ/fZ9Nh7mDUfAa1dalqfK8onSmcV3QtCSqkYg2j7UBDlbEF3XmWfU0Y3 s4DA== X-Gm-Message-State: AOAM532QrG35DE20wxiBQ6cFSm7dNI1HKp6YQ8zxOZKRXPW02oluGwMd gX04OFY20/ea+NJlz7E+EGU= X-Google-Smtp-Source: ABdhPJwJ7Lusw5e3bPm9iJOhRrfadTb9G3zuqtBL6T1Tm/9SAPsbc9Rn58zvn/RAPULUa9i/C8hQ7w== X-Received: by 2002:a5d:6d0a:: with SMTP id e10mr3414411wrq.161.1619088489529; Thu, 22 Apr 2021 03:48:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 11/15] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps Date: Thu, 22 Apr 2021 12:47:00 +0200 Message-Id: <20210422104705.2454166-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b7095bc4192..28c4fc541a2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 60c667801ef..3c3f211136d 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c74390aafbf..c44229205ff 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 326ed9180cc..ff356094b13 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ee64461b43..5269fa484e1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -7434,7 +7435,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id v4sm2735471wme.14.2021.04.22.03.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VCgSNByfqZlHb2i83TUJTs9p8gSfeP+WhL6wKNVMsbk=; b=HNQXefQ2CT2o95hQGEdlMitmFRmAvAVl51M4NsxZDMxPZrc0JcdbUdzjrrM9Gs3gTN uqnKtJsjztgERV4oDdUJdj3bJVkIRFWkjUXMVh6ATQhSN4KO41bzSDpIKaOY9AJuqLPr Cb7xsHyRWvXtNoUWfMMpqyC5HMb272f5f1VjUxSpyf7bBaTCHnR1dPGweRT57cx3f6GA eH3/u3B0LirivoK061gVXa/+VCs15U0v4pcgswj2Vh9Pf9IvW19N85bRZ0DZnED6A+uE KPtSMRmaecQrX3qNGgnxYEna6h6Yx6n54JLYi0oX7h2yHhCiJM42y8SE2LubTx4dikB5 t1XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VCgSNByfqZlHb2i83TUJTs9p8gSfeP+WhL6wKNVMsbk=; b=Uu93xhTaklmNiqFvvgLjIZlPW3HvQLsURWEF0LZ/IiJEGSGISdMMOPdJdhnkUkm527 MFzVJiqIJG2zeND9NGPoA7SR15I/S+RKrahtTcLLHbvmjVVdTLuO2uLdAkiraCQa9tsh eATEEfSFWmQSwL7QT1MOKjmTHAltgQf35iJf7bZPm9IZ6/qI8PyUQUMjprOw+l9doPTl ZykIOsQ/KJ2cuSf24kiohm6jhLzlfH4lDnvo3HedjbuGUsZwtmWL6ULGd5E/FxtC0ePD TytA/5w8xVu8kUupu6gacfpvKADA+s7ITJ1HHHTE1eelP/rTpcVNWrdXfh2HfxHSWnIP vORw== X-Gm-Message-State: AOAM531dVPVv52IoLxWGORxdSN7+0VTQYjXPCjhncVlV8q6juM9UnIqj nFqLcYqOf2joitfMcKTM9eg= X-Google-Smtp-Source: ABdhPJwzQp7KICLoAZ+v0t02Q1yKB5Msfg61j1DH4IrRWSqQMWu9707WOKOZZf6iK59H77PiF3ZNUA== X-Received: by 2002:a1c:cc0e:: with SMTP id h14mr3181383wmb.4.1619088496214; Thu, 22 Apr 2021 03:48:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , Michael Rolnik , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , Cornelia Huck , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v5 12/15] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Date: Thu, 22 Apr 2021 12:47:01 +0200 Message-Id: <20210422104705.2454166-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 38 insertions(+), 35 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 28c4fc541a2..88a0a90ac7b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 3c3f211136d..0c8f616a565 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c44229205ff..6932781425a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 73d1945b136..fb350ca800f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, .vmsd =3D &vmstate_alpha_cpu, }; #endif @@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ff356094b13..8d6406c9e8a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1945,6 +1945,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 20a48bdfbab..436d001a679 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, .vmsd =3D &vms_avr_cpu, }; =20 @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 5fa2a3f20f1..6fa345a4f15 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, .vmsd =3D &vmstate_cris_cpu, }; #endif @@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 16ba76cfafd..46b69908fa3 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_hppa_cpu, }; #endif @@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5269fa484e1..18debeb645f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 4ff54fd9204..d31c33575f6 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps lm32_sysemu_ops =3D { + .get_phys_page_debug =3D lm32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_lm32_cpu, }; #endif @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 840196c93e4..8b48bcd740d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, .vmsd =3D &vmstate_m68k_cpu, }; #endif @@ -539,7 +540,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d8fc137b3e7..5827916b66f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, .vmsd =3D &vmstate_mb_cpu, }; #endif @@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; cc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 03fc4ef1962..c9994af8f99 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .vmsd =3D &vmstate_mips_cpu, }; #endif @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 1e87f07ca73..c488bbc894a 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static const struct SysemuCPUOps moxie_sysemu_ops =3D { + .get_phys_page_debug =3D moxie_cpu_get_phys_page_debug, .vmsd =3D &vmstate_moxie_cpu, }; =20 @@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D moxie_cpu_has_work; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; -#endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a785f3ea7b6..6fc73ed8693 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu =3D { }; =20 static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, .vmsd =3D &vmstate_nios2_cpu, }; #endif @@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b1f3f16820a..f7a987a6e04 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_openrisc_cpu, }; #endif @@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8734e530cc5..f660074f5ee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, /* For now, mark unmigratable: */ @@ -631,7 +632,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f293f3630d0..5f8226ed31c 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu =3D { }; =20 static const struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, .vmsd =3D &vmstate_rx_cpu, }; #endif @@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 2b249f47eb9..96e8342fb96 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index a2dd8f93257..f75275b3b92 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sh_cpu, }; #endif @@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f5862e74baf..b13d586f79d 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9374f8440a0..b1776c10205 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu =3D= { }; =20 static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, .vmsd =3D &vmstate_tricore_cpu, }; =20 @@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index ee5d2c5fd57..f015af28787 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static const struct SysemuCPUOps uc32_sysemu_ops =3D { + .get_phys_page_debug =3D uc32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_uc32_cpu, }; =20 @@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_uc32_cpu; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 83dd8e4f6c9..bdad82f460d 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_xtensa_cpu, }; #endif @@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->vmsd =3D &vmstate_xtensa_cpu; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index a55d1c54fcf..4cc210b1116 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10880,6 +10880,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10928,7 +10929,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id 18sm5709423wmo.47.2021.04.22.03.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9/x0sbee0gzO87Im7J0Upi0aYSK51jCOG4/iCv7QYG0=; b=XVoyPnqPEXFVncimCquNPhdHgXHJiJoO7ioPnl5TZBZb4QbF2BGG2rhGER+KK28rZy LHxYMR7EPdG/sQLFRPzSFGzX4E1Rz3LVJnr8nYHmOvQtRZ5wXOe2uRRVHbkVM9zlR/yI JBzBzl8IgiazX4PR+ESR3BDUzcA0h6u5uVn1BnMBXz+24nhh50Vn/8ij3WZxHCFIJT+F pxAPbg6aO+Hddk2oxoE/DGJ6w7PPdQd4itrv48xEemdufB8RIHB2fcoLZXoAiEQH83CW A5zj536ukP9arygIfOr86hhQbyLjSPLlpSdIh8hlbGH16ge9NuOsYHtoydX7eCS2kZpI Z9KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9/x0sbee0gzO87Im7J0Upi0aYSK51jCOG4/iCv7QYG0=; b=PzwAH5LsE/jnhK9ZlfD3Hrf/vlqxZnIltxwPgU7yzCAbxT9zcXzew0i3wuC7Nm2fbU 8QLiog6PNBEwagMTAcrh9Hz3lQ/Ez8ugFDGrBcUYKpTJjp6TUvs25KAAvvvLRf4qh9q9 CwEjrgIBFdApcnSPlopA7Yb7ph4r5/nLqKzLLobJmaOoJWjxWUdcJ5gSdmeY6qYN5hHH kAnkFH4BK5MLnDBh1rpLCUtU7BSP01DX0y9nnAyjbhXRKDWlNRY5i9dr+GStE1B7v/4j 4qClf804DM8oUswB01tfXHkLcSJsPi0t/wLaZwmIHBzotfoxz9/43qiRjRLxLhwT4aoW EdKA== X-Gm-Message-State: AOAM531P65eTu+7yUMxAVxZMEx8uB0bdVOBJQrwWQueO9CIx1YE+uITi zNmiFqlfXxhsnEU6c6lqXwc= X-Google-Smtp-Source: ABdhPJxyK0rvemR4i6yJ9QvbeEnCk34Y4uN83JFspsuLESFNq/0RWUC4YbwCySuicti7i0D3xmoNOA== X-Received: by 2002:a1c:e006:: with SMTP id x6mr14995174wmg.40.1619088501321; Thu, 22 Apr 2021 03:48:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 13/15] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps Date: Thu, 22 Apr 2021 12:47:02 +0200 Message-Id: <20210422104705.2454166-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 88a0a90ac7b..6dd60c3ada4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -94,7 +94,6 @@ struct AccelCPUClass; * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -138,8 +137,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 0c8f616a565..460e7d63b0c 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 6932781425a..339bdfadd7a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_memory_mapping) { - cc->get_memory_mapping(cpu, list, errp); + if (cc->sysemu_ops->get_memory_mapping) { + cc->sysemu_ops->get_memory_mapping(cpu, list, errp); return; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 18debeb645f..1b7317e43b4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7393,6 +7393,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7436,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619088508; cv=none; d=zohomail.com; s=zohoarc; b=G0EdnYVc/wyB8j+WI9SmPZF9fAvIXDN/uFZt/JVnAjvhH8o3i8zRyA8GXp00A0B5RB9DQyOvb89kxbD1Q1tk02O1Wsd7prOfQ4YnKha9Yg+lHL9KIsRCG1Q0OvScPM3uwtlorNAjoj5OQmzd5aiLmoqoTn+ZCPNRs3oOsqYcmX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088508; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qHZkesTQ7iY0aT+GqCLFkQZuPGZupRkmvhvWLL3ejQQ=; b=IJUS4Km3/pw5qc6qtOB/02c0GisNkDzBNmXpFcVO2FjaP9VowDE6nE0RQPz17fajDlU7cUkXGtxY7DPZ+jUByDVEv8XxgYL5h4DBdqP//+fps6L0fTcp7YESs6FPncwwAf8iLELgylFHeKBiRLDnDGt19d63MBKzwD60oErQWtU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.zohomail.com with SMTPS id 1619088508267208.32676191301528; Thu, 22 Apr 2021 03:48:28 -0700 (PDT) Received: by mail-wm1-f47.google.com with SMTP id n127so12044021wmb.5 for ; Thu, 22 Apr 2021 03:48:27 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id y8sm3398426wru.27.2021.04.22.03.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qHZkesTQ7iY0aT+GqCLFkQZuPGZupRkmvhvWLL3ejQQ=; b=fU/W7JOBizxBXgABfqaHuQ8B892lUWfRY5YOXDn71cd2A1wMrRhrZWFcBwqUve2ZZa jf1kKqs/duj7WWF4xB+L1bRxfloYnNS4HM20R2cN0n0ekoOyUNSoczrntuZ44VaRBCiy MIwKSeRXDnehpRZDsVSdmkc+3nl/Dc7j7v9/S36AykXm93GFrKUEXzhj92OLOQmfJs0N uAAyFbp53fPZ2wkaagB8EJ9NuMHeuuViF8Ocww5eJQIpVh1B4yVePefyYDsVbPejy25h VTlN+s98eMg9eIJFNYyx3fwELz83XuZGu4KVupa4Miw+kfwIBrr0FkiOUZoX550+2Khf dx+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qHZkesTQ7iY0aT+GqCLFkQZuPGZupRkmvhvWLL3ejQQ=; b=mMVcwVJNMKLrWvlCoRgTWmiWPd79tvxa753aYpFtciSgl+lfD0FZsEJBHBIILu2AT6 q3caFhugz29Oj42fbnZwaJ4cxOwf9W1NE5L7LPsE7bock5+B2dWlzovRPo096g9Yd7xI r0DQrWq/xFO/r4wCcnDBXKHth00pCvK6V1xeMFucUfeQPdFwCNQzbLxZ6Uet/A0PYQfy GIwKPb6iFHisHcnI62w0+7ag5YkBKFOT5HNSWGrncI6DmzMp9mWNrcbEf+T/Urq9v4yl RSX0Yuozq/EVHO7wYkkSYFpb2rKbfPnqLsnkVodQblt7EDkB+F2HDRT5e80hn7Va5D50 kp3g== X-Gm-Message-State: AOAM532IRkFDKRyF7nTHJhbPdYfVOzgdoz5CYdM3tCHZPDqh8lLzfhUM VHoQQuoj9VjQvPjcuUpI0ym/tCCIbSaPpQ== X-Google-Smtp-Source: ABdhPJzNC4BB9erAWVRLhhpwh1Zeqi5ghOGFzpiqQnj+JtfT+pJrHpsivyK3RstfYnX4BMN+3cJefg== X-Received: by 2002:a1c:6a06:: with SMTP id f6mr3077795wmc.179.1619088506542; Thu, 22 Apr 2021 03:48:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum Subject: [PATCH v5 14/15] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps Date: Thu, 22 Apr 2021 12:47:03 +0200 Message-Id: <20210422104705.2454166-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6dd60c3ada4..d0187798eea 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -93,7 +93,6 @@ struct AccelCPUClass; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -136,7 +135,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 460e7d63b0c..3f9a5199dd1 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 339bdfadd7a..7a8487d468f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->sysemu_ops->get_paging_enabled) { + return cc->sysemu_ops->get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b7317e43b4..feb71981efb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7162,12 +7162,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs) return cpu->apic_id; } =20 +#if !defined(CONFIG_USER_ONLY) static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 return cpu->env.cr[0] & CR0_PG_MASK; } +#endif /* !CONFIG_USER_ONLY */ =20 static void x86_cpu_set_pc(CPUState *cs, vaddr value) { @@ -7394,6 +7396,7 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_memory_mapping =3D x86_cpu_get_memory_mapping, + .get_paging_enabled =3D x86_cpu_get_paging_enabled, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7434,7 +7437,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3 From nobody Wed Dec 17 22:03:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619088514; cv=none; d=zohomail.com; s=zohoarc; b=DrQXu4bLrNjWmNMDNVTsO1MlgKyouKBu5rgsQyMyrGxJL8C1mYCfK6wGAuiTi0vvjWYLYlactfTdamiE7sdSvl3H169o96BTVheBYatMmOsqW71iAThSPVp6SsxpXO1FZMxsmJN+L9Z3sa9N2gHOOtpWwGQivEppzrOnGQhzqnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619088514; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DeCLhui4rg2rh6ax+66/y+81F2OHwJcABZRfsK+3aus=; b=H5HzM7j3wfi2QUTrHqOosua9n3KJaJbKC4kJPxmn4shd6Z56roghohnaOwAFha8HYaPuvH7ecLrmwGJl4BavhMs6JMV9suYOt0pUhe//gVJ80sGUZd4zQVpfasmlrUWEXcp/HkrkieLilsvV3x9gEw2CmENd4xeSLAPWEddnLyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1619088514793199.37701250993234; Thu, 22 Apr 2021 03:48:34 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id m9so31568511wrx.3 for ; Thu, 22 Apr 2021 03:48:34 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (39.red-81-40-121.staticip.rima-tde.net. [81.40.121.39]) by smtp.gmail.com with ESMTPSA id q5sm2911733wrv.17.2021.04.22.03.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 03:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DeCLhui4rg2rh6ax+66/y+81F2OHwJcABZRfsK+3aus=; b=S68PNGmveZoUqqbDeEsG0GzcSvYOD8opZKzRarns+HKmSOKnzEMFDz8wBNDdrg3AMP ofWcFL4UlkIXTnCxIQXM4HBtq4ZpDEvJd11Wnm2gjSsiOA2oriIuOeL3hfVTLoBlcjzG k0sJRd/HDir5G7tHr6ubFjCgN9LwHNtBsrhF3V4R5nHCGwQdo/Rr6G1uzVyjW3XlrUX6 sTUTEUwPbUHTSI8tYRcggE63E1/XNxKiFTfUu01U6ptY9kRG1l63XHm2eAuTnTbdhyTS H9pvSOFeQZa8liWHccw5k0oKBimEoQDSfmgxI6bgEwodAybJb1kYezm5kaBuIiwt5xqU TiBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DeCLhui4rg2rh6ax+66/y+81F2OHwJcABZRfsK+3aus=; b=uOCT9yOYfJPg+MJwtdiXQkwCUFDO8pcXqA7aWX6d27/USRiJargLymMdWqcbKEOLVM O/2cHdacaRIalMtL8oIGwlBWX6pUTq/jG0m5QoNRnB/OSoUMEKlRS7ir1zBkPlCbW81M jCBbl6keCdENNr0a9fMxUxCv9/DQynnRtQxqZmk/0UeC6Sd0JIIi3gAYJ0X42/Ul8V3Z eqrOSNh12PRfOeojPGWspKXM/fkqwBNhsAVxTqH2w3heUd8uM7yLE48+e1p6pYGD8Q0l ERmzEMjf/gSU4zKh63vvR1XBwVZUsREfMmyyBQh1ECCuqqmop35x7nvK1yjemAPyO2tO Gwuw== X-Gm-Message-State: AOAM5305pqmqCQK9ruS14awQz+DEa6KbLnnnGtXBfWcK+FPuAYFgzpR2 rvQrTrs95XnkbBt9B8um67g= X-Google-Smtp-Source: ABdhPJwJ8LvyBLx/E5uZKCaAgQSoppjg7uRXw7uTKZwU8E/0z7Pb23/DdKEk7MiJJp6GuCW1jl6o7g== X-Received: by 2002:a5d:4d02:: with SMTP id z2mr3296880wrt.190.1619088513005; Thu, 22 Apr 2021 03:48:33 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Claudio Fontana , Juan Quintela , Greg Kurz , Laurent Vivier , qemu-riscv@nongnu.org, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Peter Maydell , qemu-arm@nongnu.org, Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Taylor Simpson , Marcel Apfelbaum , Michael Rolnik , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Cornelia Huck , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [PATCH v5 15/15] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c Date: Thu, 22 Apr 2021 12:47:04 +0200 Message-Id: <20210422104705.2454166-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422104705.2454166-1-f4bug@amsat.org> References: <20210422104705.2454166-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"): We cannot in principle make the SysEmu Operations field definitions conditional on CONFIG_SOFTMMU in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the SysEmu fields to system emulation builds, is to move all sysemu operations into a separate header file, which is only included by system-specific code. This leaves just a NULL pointer in the cpu.h for the user-mode builds. Inspired-by: Claudio Fontana Reviewed-by: Taylor Simpson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 ++- target/alpha/cpu.h | 3 +++ target/arm/cpu.h | 3 +++ target/avr/cpu.h | 1 + target/cris/cpu.h | 3 +++ target/hexagon/cpu.h | 3 +++ target/hppa/cpu.h | 3 +++ target/i386/cpu.h | 3 +++ target/lm32/cpu.h | 3 +++ target/m68k/cpu.h | 3 +++ target/microblaze/cpu.h | 1 + target/mips/cpu.h | 3 +++ target/moxie/cpu.h | 3 +++ target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 3 +++ target/ppc/cpu.h | 3 +++ target/riscv/cpu.h | 3 +++ target/rx/cpu.h | 1 + target/s390x/cpu.h | 3 +++ target/sh4/cpu.h | 3 +++ target/sparc/cpu.h | 3 +++ target/tricore/cpu.h | 3 +++ target/unicore32/cpu.h | 3 +++ target/xtensa/cpu.h | 3 +++ cpu.c | 1 + hw/core/cpu.c | 1 + 26 files changed, 65 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d0187798eea..3422d405b49 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,7 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 -#include "hw/core/sysemu-cpu-ops.h" +/* see sysemu-cpu-ops.h */ +struct SysemuCPUOps; =20 /** * CPUClass: diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967b..f1218a27706 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fa..d9228d1d990 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a4..e0419649fa7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b64929096..4450f2268ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,6 +23,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define EXCP_NMI 1 #define EXCP_GURU 2 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index e04eac591c8..2a878e77f08 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState; #include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61178fa6a2a..94d2d4701c4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "exec/memory.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916878f..2f520cb6fc1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -25,6 +25,9 @@ #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ea7c01ca8b0..034183dad30 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 typedef struct CPULM32State CPULM32State; =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 402c86c8769..681dc0d1d13 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -23,6 +23,9 @@ =20 #include "exec/cpu-defs.h" #include "cpu-qom.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define OS_BYTE 0 #define OS_WORD 1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..3f5c2e048e5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -26,6 +26,7 @@ =20 typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..923ab71f8d7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -6,6 +6,9 @@ #include "fpu/softfloat-types.h" #include "hw/clock.h" #include "mips-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index bd6ab66084d..7a0a5e95d01 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -22,6 +22,9 @@ =20 #include "exec/cpu-defs.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc713..1b88b027063 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -27,6 +27,7 @@ =20 typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..2a6f9f48547 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -23,6 +23,9 @@ #include "exec/cpu-defs.h" #include "hw/core/cpu.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68d..f889c28e548 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -24,6 +24,9 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba8..90ac5097718 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,9 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7be..d9b7b63716a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -25,6 +25,7 @@ #include "cpu-qom.h" =20 #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 /* PSW define */ REG32(PSW, 0) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2464d4076c0..8f7233d97c2 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,6 +28,9 @@ #include "cpu-qom.h" #include "cpu_models.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define ELF_MACHINE_UNAME "S390X" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 01c43440822..6c3d3a29fc2 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4b2290650be..237ffc4fe66 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,9 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f8..a7636c0e870 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "tricore-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 struct tricore_boot_info; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 7a32e086ed3..de475d0fc2e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -14,6 +14,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 typedef struct CPUUniCore32State { /* Regs for current mode. */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3bd4f691c1a..ea4ee5338f3 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/cpu.c b/cpu.c index 64e17537e21..29dafee581f 100644 --- a/cpu.c +++ b/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else +#include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #endif #include "sysemu/tcg.h" diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 7a8487d468f..da7543be514 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -35,6 +35,7 @@ #include "trace/trace-root.h" #include "qemu/plugin.h" #include "sysemu/hw_accel.h" +#include "hw/core/sysemu-cpu-ops.h" =20 CPUState *cpu_by_arch_id(int64_t id) { --=20 2.26.3